jalr/ch32-dimmer-node
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Add PCB

Browse source
This commit is contained in:
Jakob Lechner 2025-08-20 11:07:16 +02:00
parent a9c79c8704
commit 8ecd7f3416
12 changed files with 34634 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

40
dimmer-pcb/.gitignore vendored Normal file
View file

@ -0,0 +1,40 @@
# For PCBs designed using KiCad: https://www.kicad.org/
# Format documentation: https://kicad.org/help/file-formats/
# Temporary files
*.000
*.bak
*.bck
*.kicad_pcb-bak
*.kicad_sch-bak
*-backups
*-cache*
*-bak
*-bak*
*~
~*
_autosave-*
\#auto_saved_files\#
*.tmp
*-save.pro
*-save.kicad_pcb
fp-info-cache
~*.lck
\#auto_saved_files#
# Netlist files (exported from Eeschema)
*.net
# Autorouter files (exported from Pcbnew)
*.dsn
*.ses
# Exported BOM files
*.xml
*.csv
# Archived Backups (KiCad 6.0)
**/*-backups/*.zip
# Local project settings
*.kicad_prl

1
dimmer-pcb/L_TECHFUSE_SL0420.kicad_mod Normal file
View file

@ -0,0 +1 @@
(footprint "L_Coilcraft_MSS1260T-XXX"(version 20241229) (generator "pcbnew") (generator_version "9.0")(layer "F.Cu" )(descr "Inductor, Coilcraft, MSS1260T-XXX, 12.0x12.0x6.0mm, (https://www.coilcraft.com/getmedia/ce88ed45-272e-474e-a25e-981003944639/mss1260t.pdf), generated with kicad-footprint-generator gen_inductor.py")(tags "Inductor mss")(property "Reference" "REF**"(at 0 -7 0)(layer "F.SilkS" )(uuid "9a7ada28-5148-4377-babe-dd21dce87330")(effects(font(size 1 1)(thickness 0.15))))(property "Value" "L_TECHFUSE_SL0420"(at 0 7 0)(layer "F.Fab" )(uuid "b23a84ce-8da0-4b44-bbbf-83f9a6d64b49")(effects(font(size 1 1)(thickness 0.15))))(property "Datasheet" ""(at 0 0 0)(layer "F.Fab" )(hide yes)(uuid "4a7ae4ff-69e7-4a6c-8a54-e5767493573f")(effects(font(size 1.27 1.27)(thickness 0.15))))(property "Description" ""(at 0 0 0)(layer "F.Fab" )(hide yes)(uuid "244bd214-0e7a-424d-b4cb-ec8e8ee5278f")(effects(font(size 1.27 1.27)(thickness 0.15))))(attr smd)(fp_line (start -6.26 -6.26) (end -6.26 -3.01)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "55db190c-ca42-4b61-8c68-5eeb3cd55db3"))(fp_line (start -6.26 -6.26) (end -4.61 -6.26)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "141f6cf9-c972-4d87-91c5-7324e585efd7"))(fp_line (start -6.26 6.26) (end -6.26 3.01)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "01f28edf-ff01-4076-89b9-0c89c3adeb32"))(fp_line (start -6.26 6.26) (end 6.26 6.26)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "e0475cc7-2c24-4de9-bd2b-806f27311307"))(fp_line (start -3.89 -6.26) (end 6.26 -6.26)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "100c7001-0d57-4ec4-9814-6fbc7a623084"))(fp_line (start 6.26 -6.26) (end 6.26 -3.01)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "866da21d-99c0-46d5-805a-3e5edf96df38"))(fp_line (start 6.26 6.26) (end 6.26 3.01)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "3358b76e-8cb6-494c-9d54-7defe47c26f6"))(fp_poly(pts(xy -4.25 -6.26)(xy -4.49 -6.59)(xy -4.01 -6.59)(xy -4.25 -6.26))(stroke (width 0.12) (type solid))(fill yes)(layer "F.SilkS" )(uuid "19427bf2-6765-46ad-b44b-fc322874c846"))(fp_line (start -6.5 -6.25) (end -6.5 6.25)(stroke (width 0.05) (type solid))(layer "F.CrtYd" )(uuid "f89e576d-ea92-4e96-a28c-b1628612d3de"))(fp_line (start -6.5 6.25) (end 6.5 6.25)(stroke (width 0.05) (type solid))(layer "F.CrtYd" )(uuid "9bae5f1c-3016-48e6-a04f-870e2d25f9bc"))(fp_line (start 6.5 -6.25) (end -6.5 -6.25)(stroke (width 0.05) (type solid))(layer "F.CrtYd" )(uuid "366484f2-a4d0-46b1-9236-c2c3d668b28d"))(fp_line (start 6.5 6.25) (end 6.5 -6.25)(stroke (width 0.05) (type solid))(layer "F.CrtYd" )(uuid "e1a158f1-d247-4f9c-8faa-79098dbcad67"))(fp_line (start -6 -5) (end -5 -6)(stroke (width 0.1) (type solid))(layer "F.Fab" )(uuid "96ab3b06-ba72-489f-a746-845a8ec7c0e2"))(fp_line (start -6 6) (end -6 -5)(stroke (width 0.1) (type solid))(layer "F.Fab" )(uuid "344874df-59a9-4879-a822-5599c17892cd"))(fp_line (start -5 -6) (end 6 -6)(stroke (width 0.1) (type solid))(layer "F.Fab" )(uuid "27de01ba-db5f-4fe1-954a-79a2f0b3fdb0"))(fp_line (start -4.25 4.8) (end -4.25 -4.8)(stroke (width 0.1) (type solid))(layer "F.Fab" )(uuid "e78d56ab-4ee2-47b7-bc3d-1d03076f71b5"))(fp_line (start 6 -6) (end 6 6)(stroke (width 0.1) (type solid))(layer "F.Fab" )(uuid "4470eb34-c430-47a7-8112-f994c02d3298"))(fp_line (start 6 6) (end -6 6)(stroke (width 0.1) (type solid))(layer "F.Fab" )(uuid "85492e00-218c-4ba2-8aa7-41bea817f863"))(fp_text user "${REFERENCE}"(at 0 0 0)(layer "F.Fab" )(uuid "fe8a5faf-7789-4f9e-92a0-5e74afc40e71")(effects(font(size 1 1)(thickness 0.15))))(pad "1" smd roundrect(at 2.475 0 )(size 0.99375 2.3)(layers "F.Cu" "F.Mask" "F.Paste")(roundrect_rratio 0.0625)(uuid "b3dab13c-3eef-4394-96b1-50e95a77e6dd"))(pad "2" smd roundrect(at -2.475 0 )(size 1 2.3)(layers "F.Cu" "F.Mask" "F.Paste")(roundrect_rratio 0.0625)(uuid "32149c47-0ccf-40d6-b630-83d775f5c0e1"))(embedded_fonts no)(model "${KICAD9_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Coilcraft_MSS1260T-XXX.wrl"(offset (xyz 0 0 0))(scale (xyz 1 1 1))(rotate (xyz 0 0 0))))

4669
dimmer-pcb/bom/ibom.html Normal file
View file

File diff suppressed because one or more lines are too long

132
dimmer-pcb/dimmer-pcb.kicad_dru Normal file
View file

@ -0,0 +1,132 @@
(version 1)
# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '<project>.kicad_dru' file).
#
# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities
#
# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules
#
# Inspiration
# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments)
# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments)
# TODO new rule: NPTH pads.
# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter.
# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)."
# TODO: new rule for plated slots: min diameter/width 0.5mm
# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad."
# TODO new rule: non-plated slots: min diameter/width 1.0mm
# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)""
(rule "Track width, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track'")
(constraint track_width (min 0.127mm))
)
(rule "Track spacing, outer layer (1oz copper)"
(layer outer)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.127mm))
)
(rule "Track width, inner layer"
(layer inner)
(condition "A.Type == 'track'")
(constraint track_width (min 0.09mm))
)
(rule "Track spacing, inner layer"
(layer inner)
(condition "A.Type == 'track' && B.Type == A.Type")
(constraint clearance (min 0.09mm))
)
(rule "Silkscreen text"
(layer "?.Silkscreen")
(condition "A.Type == 'Text' || A.Type == 'Text Box'")
(constraint text_thickness (min 0.15mm))
(constraint text_height (min 1mm))
)
(rule "Pad to Silkscreen"
(layer outer)
(condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'")
(constraint silk_clearance (min 0.15mm))
)
(rule "Edge (routed) to track clearance"
(condition "A.Type == 'track'")
(constraint edge_clearance (min 0.3mm))
)
#(rule "Edge (v-cut) to track clearance"
# (condition "A.Type == 'track'")
# (constraint edge_clearance (min 0.4mm))
#)
# JLCPCB restrictions ambiguous:
# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)"
# This rule handles diameter minimum and maximum for ALL holes.
# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH)
(rule "Hole diameter"
(constraint hole_size (min 0.2mm) (max 6.3mm))
)
(rule "Hole (NPTH) diameter"
(layer outer)
(condition "!A.isPlated()")
(constraint hole_size (min 0.5mm))
)
# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm
(rule "Hole (castellated) diameter"
(layer outer)
(condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'")
(constraint hole_size (min 0.6mm))
)
# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions)
# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production."
(rule "Annular ring width (via and PTH)"
(layer outer)
(condition "A.isPlated()")
(constraint annular_width (min 0.075mm))
)
(rule "Clearance: hole to hole (perimeter), different nets"
(layer outer)
(condition "A.Net != B.Net")
(constraint hole_to_hole (min 0.5mm))
)
(rule "Clearance: hole to hole (perimeter), same net"
(layer outer)
(condition "A.Net == B.Net")
(constraint hole_to_hole (min 0.254mm))
)
(rule "Clearance: track to NPTH hole (perimeter)"
# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net")
(condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.254mm))
)
(rule "Clearance: track to PTH hole perimeter"
(condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net")
(constraint hole_clearance (min 0.33mm))
)
# TODO: try combining with rule "Clearance: PTH to track, different nets"
(rule "Clearance: track to pad"
(condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net")
(constraint clearance (min 0.2mm))
)
(rule "Clearance: pad/via to pad/via"
(layer outer)
# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net")
(condition "A.isPlated() && B.isPlated() && A.Net != B.Net")
(constraint clearance (min 0.127mm))
)

17911
dimmer-pcb/dimmer-pcb.kicad_pcb Normal file
View file

File diff suppressed because it is too large Load diff

705
dimmer-pcb/dimmer-pcb.kicad_pro Normal file
View file

@ -0,0 +1,705 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"apply_defaults_to_fp_fields": false,
"apply_defaults_to_fp_shapes": false,
"apply_defaults_to_fp_text": false,
"board_outline_line_width": 0.05,
"copper_line_width": 0.2,
"copper_text_italic": false,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"copper_text_upright": false,
"courtyard_line_width": 0.05,
"dimension_precision": 4,
"dimension_units": 3,
"dimensions": {
"arrow_length": 1270000,
"extension_offset": 500000,
"keep_text_aligned": true,
"suppress_zeroes": true,
"text_position": 0,
"units_format": 0
},
"fab_line_width": 0.1,
"fab_text_italic": false,
"fab_text_size_h": 1.0,
"fab_text_size_v": 1.0,
"fab_text_thickness": 0.15,
"fab_text_upright": false,
"other_line_width": 0.1,
"other_text_italic": false,
"other_text_size_h": 1.0,
"other_text_size_v": 1.0,
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 0.8,
"height": 1.27,
"width": 2.54
},
"silk_line_width": 0.1,
"silk_text_italic": false,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.1,
"silk_text_upright": false,
"zones": {
"min_clearance": 0.25
}
},
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
},
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"creepage": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_filters_mismatch": "ignore",
"footprint_symbol_mismatch": "warning",
"footprint_type_mismatch": "ignore",
"hole_clearance": "error",
"hole_to_hole": "warning",
"holes_co_located": "warning",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"mirrored_text_on_front_layer": "warning",
"missing_courtyard": "ignore",
"missing_footprint": "warning",
"net_conflict": "warning",
"nonmirrored_text_on_back_layer": "warning",
"npth_inside_courtyard": "ignore",
"padstack": "warning",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_on_edge_cuts": "error",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_angle": "error",
"track_dangling": "warning",
"track_segment_length": "error",
"track_width": "error",
"tracks_crossing": "error",
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zones_intersect": "error"
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.2,
"min_microvia_drill": 0.1,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.8,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.0,
"min_via_annular_width": 0.1,
"min_via_diameter": 0.5,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_onpthpad": true,
"td_onroundshapesonly": false,
"td_onsmdpad": true,
"td_ontrackend": false,
"td_onvia": true
}
],
"teardrop_parameters": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_on_pad_in_zone": false,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.4,
1.5
],
"tuning_pattern_settings": {
"diff_pair_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 1.0
},
"diff_pair_skew_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
},
"single_track_defaults": {
"corner_radius_percentage": 80,
"corner_style": 1,
"max_amplitude": 1.0,
"min_amplitude": 0.2,
"single_sided": false,
"spacing": 0.6
}
},
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false
},
"ipc2581": {
"dist": "",
"distpn": "",
"internal_id": "",
"mfg": "",
"mpn": ""
},
"layer_pairs": [],
"layer_presets": [],
"viewports": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"footprint_filter": "ignore",
"footprint_link_issues": "warning",
"four_way_junction": "ignore",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"label_multiple_wires": "warning",
"lib_symbol_issues": "warning",
"lib_symbol_mismatch": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"same_local_global_label": "warning",
"similar_label_and_power": "warning",
"similar_labels": "warning",
"similar_power": "warning",
"simulation_model_issue": "ignore",
"single_global_label": "ignore",
"unannotated": "error",
"unconnected_wire_endpoint": "warning",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "dimmer-pcb.kicad_pro",
"version": 3
},
"net_settings": {
"classes": [
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2147483647,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.2,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "3V3",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.4,
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Power",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 1.5,
"via_diameter": 0.8,
"via_drill": 0.5,
"wire_width": 6
}
],
"meta": {
"version": 4
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": [
{
"netclass": "3V3",
"pattern": "+3V3"
}
]
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"plot": "",
"pos_files": "",
"specctra_dsn": "",
"step": "",
"svg": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"bom_export_filename": "${PROJECTNAME}.csv",
"bom_fmt_presets": [],
"bom_fmt_settings": {
"field_delimiter": ",",
"keep_line_breaks": false,
"keep_tabs": false,
"name": "CSV",
"ref_delimiter": ",",
"ref_range_delimiter": "",
"string_delimiter": "\""
},
"bom_presets": [],
"bom_settings": {
"exclude_dnp": false,
"fields_ordered": [
{
"group_by": false,
"label": "Reference",
"name": "Reference",
"show": true
},
{
"group_by": true,
"label": "Value",
"name": "Value",
"show": true
},
{
"group_by": true,
"label": "Footprint",
"name": "Footprint",
"show": true
},
{
"group_by": false,
"label": "Datasheet",
"name": "Datasheet",
"show": true
},
{
"group_by": false,
"label": "Description",
"name": "Description",
"show": false
},
{
"group_by": false,
"label": "Qty",
"name": "${QUANTITY}",
"show": true
},
{
"group_by": false,
"label": "#",
"name": "${ITEM_NUMBER}",
"show": false
},
{
"group_by": false,
"label": "Sim.Device",
"name": "Sim.Device",
"show": false
},
{
"group_by": false,
"label": "Sim.Pins",
"name": "Sim.Pins",
"show": false
},
{
"group_by": false,
"label": "Sim.Type",
"name": "Sim.Type",
"show": false
},
{
"group_by": true,
"label": "DNP",
"name": "${DNP}",
"show": true
},
{
"group_by": true,
"label": "Exclude from BOM",
"name": "${EXCLUDE_FROM_BOM}",
"show": true
},
{
"group_by": true,
"label": "Exclude from Board",
"name": "${EXCLUDE_FROM_BOARD}",
"show": true
}
],
"filter_string": "",
"group_symbols": true,
"include_excluded_from_bom": true,
"name": "",
"sort_asc": true,
"sort_field": "Reference"
},
"connection_grid_size": 50.0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.375,
"operating_point_overlay_i_precision": 3,
"operating_point_overlay_i_range": "~A",
"operating_point_overlay_v_precision": 3,
"operating_point_overlay_v_range": "~V",
"overbar_offset_ratio": 1.23,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.15
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"page_layout_descr_file": "",
"plot_directory": "",
"space_save_all_events": true,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_dissipations": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"22f3e72f-be7a-4846-ba04-c0c776fb01e9",
"Root"
]
],
"text_variables": {}
}

10966
dimmer-pcb/dimmer-pcb.kicad_sch Normal file
View file

File diff suppressed because it is too large Load diff

1
dimmer-pcb/fabrication-toolkit-options.json Normal file
View file

@ -0,0 +1 @@
{"EXTRA_LAYERS": "", "ALL_ACTIVE_LAYERS": false, "EXTEND_EDGE_CUT": false, "ALTERNATIVE_EDGE_CUT": false, "AUTO TRANSLATE": true, "AUTO FILL": true, "EXCLUDE DNP": false}

4
dimmer-pcb/fp-lib-table Normal file
View file

@ -0,0 +1,4 @@
(fp_lib_table
(version 7)
(lib (name "dimmer-pcb")(type "KiCad")(uri "/home/jalr/digitaler-dienst/dimmer/dimmer-pcb.pretty")(options "")(descr ""))
)

BIN
dimmer-pcb/production/backups/dimmer-pcb_2025-03-16_23-41-49.zip Normal file
View file

Binary file not shown.

BIN
dimmer-pcb/production/dimmer-pcb.zip Normal file
View file

Binary file not shown.

205
dimmer-pcb/production/netlist.ipc Normal file
View file

@ -0,0 +1,205 @@
P CODE 00
P UNITS CUST 0
P arrayDim N
317+3V3 VIA MD0118PA00X+068386Y-040984X0236Y0000R000S3
317+3V3 VIA MD0118PA00X+068327Y-039213X0236Y0000R000S3
317+3V3 VIA MD0118PA00X+069130Y-037799X0236Y0000R000S3
317GND VIA MD0118PA00X+066614Y-032441X0236Y0000R000S3
317GND VIA MD0118PA00X+066024Y-032598X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-044409X0236Y0000R000S3
317GND VIA MD0118PA00X+067913Y-031614X0236Y0000R000S3
317GND VIA MD0118PA00X+067913Y-032087X0236Y0000R000S3
317GND VIA MD0118PA00X+069094Y-033346X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-036063X0236Y0000R000S3
317GND VIA MD0118PA00X+069173Y-039488X0236Y0000R000S3
317GND VIA MD0118PA00X+069134Y-032362X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-033543X0236Y0000R000S3
317GND VIA MD0118PA00X+066024Y-032835X0236Y0000R000S3
317GND VIA MD0118PA00X+065157Y-033976X0236Y0000R000S3
317GND VIA MD0118PA00X+066752Y-043740X0236Y0000R000S3
317GND VIA MD0118PA00X+071299Y-038858X0236Y0000R000S3
317GND VIA MD0118PA00X+067913Y-031850X0236Y0000R000S3
317GND VIA MD0118PA00X+069094Y-033110X0236Y0000R000S3
317GND VIA MD0118PA00X+067677Y-031496X0236Y0000R000S3
317GND VIA MD0118PA00X+067835Y-045748X0236Y0000R000S3
317GND VIA MD0118PA00X+069321Y-043189X0236Y0000R000S3
317GND VIA MD0118PA00X+069094Y-032874X0236Y0000R000S3
317GND VIA MD0118PA00X+069094Y-032638X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-033268X0236Y0000R000S3
317GND VIA MD0118PA00X+071299Y-039134X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-036339X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-041614X0236Y0000R000S3
317GND VIA MD0118PA00X+069803Y-045748X0236Y0000R000S3
317GND VIA MD0118PA00X+070787Y-045748X0236Y0000R000S3
317GND VIA MD0118PA00X+066575Y-032756X0236Y0000R000S3
317GND VIA MD0118PA00X+069016Y-037480X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-041890X0236Y0000R000S3
317GND VIA MD0118PA00X+065433Y-032402X0236Y0000R000S3
317GND VIA MD0118PA00X+065669Y-032402X0236Y0000R000S3
317GND VIA MD0118PA00X+072717Y-044685X0236Y0000R000S3
317GND VIA MD0118PA00X+068819Y-045748X0236Y0000R000S3
317GND VIA MD0118PA00X+065906Y-032402X0236Y0000R000S3
317GND VIA MD0118PA00X+073406Y-030138X0236Y0000R000S3
317NET-(JP3-A) VIA MD0118PA00X+070020Y-042496X0236Y0000R000S3
317NET-(JP3-A) VIA MD0118PA00X+069465Y-041343X0236Y0000R000S3
317NET-(JP4-B) VIA MD0118PA00X+069164Y-041664X0236Y0000R000S3
317NET-(JP4-B) VIA MD0118PA00X+069779Y-042260X0236Y0000R000S3
317NET-(U4-EN) VIA MD0118PA00X+067165Y-033327X0236Y0000R000S3
317NET-(U4-EN) VIA MD0118PA00X+066654Y-033327X0236Y0000R000S3
317NET-(U1-PA7) VIA MD0118PA00X+070543Y-039075X0236Y0000R000S3
317NET-(U1-PA7) VIA MD0118PA00X+069941Y-039075X0236Y0000R000S3
327GND C10 -1 A01X+068602Y-037510X0354Y0374R270S2
327+3V3 C10 -2 A01X+068602Y-036900X0354Y0374R270S2
327NET-(U4-FB) R3 -1 A01X+066909Y-034980X0315Y0374R000S2
327NET-(C1-PAD2) R3 -2 A01X+067559Y-034980X0315Y0374R000S2
327GND JP4 -1 A01X+070787Y-045343X0394Y0197R270S2
327NET-(JP4-B) JP4 -2 A01X+070787Y-044831X0394Y0197R270S2
367N/C REF** D1260UA00X+077953Y-044882X1260Y0000R000S0
327+24V C4 -1 A01X+065610Y-031969X0394Y0571R090S2
327GND C4 -2 A01X+065610Y-032717X0394Y0571R090S2
367N/C REF** D1260UA00X+062992Y-044882X1260Y0000R000S0
327+3V3 C8 -1 A01X+068120Y-039665X0354Y0374R000S2
327GND C8 -2 A01X+068730Y-039665X0354Y0374R000S2
327+3V3 C9 -1 A01X+068455Y-043524X0354Y0374R000S2
327GND C9 -2 A01X+069065Y-043524X0354Y0374R000S2
367N/C REF** D1260UA00X+062992Y-029921X1260Y0000R000S0
327CAN_RX TP2 -1 A01X+069291Y-036220X0591Y0000R000S2
327PWM_CW R6 -1 A01X+071161Y-035561X0315Y0374R090S2
327GND R6 -2 A01X+071161Y-036211X0315Y0374R090S2
327+3V3 R1 -1 A01X+068730Y-034350X0315Y0374R180S2
327NET-(C1-PAD2) R1 -2 A01X+068081Y-034350X0315Y0374R180S2
327NET-(JP1-A) JP1 -1 A01X+067835Y-044831X0394Y0197R090S2
327GND JP1 -2 A01X+067835Y-045343X0394Y0197R090S2
327NET-(U1-PA2) R14 -1 A01X+070551Y-041161X0315Y0374R270S2
327PWM_G R14 -2 A01X+070551Y-040512X0315Y0374R270S2
327NET-(U1-PA3) R15 -1 A01X+070541Y-042136X0315Y0374R000S2
327PWM_B R15 -2 A01X+071191Y-042136X0315Y0374R000S2
327NET-(U4-FB) C1 -1 A01X+066909Y-034350X0354Y0374R000S2
327NET-(C1-PAD2) C1 -2 A01X+067520Y-034350X0354Y0374R000S2
327PWM_B R9 -1 A01X+071161Y-043278X0315Y0374R090S2
327GND R9 -2 A01X+071161Y-043927X0315Y0374R090S2
317+24V J3 -1 D0433PA00X+077717Y-042531X0689Y0689R270S0
317/OUT_B J3 -2 D0433PA00X+077717Y-041031X0689Y0000R270S0
317/OUT_G J3 -3 D0433PA00X+077717Y-039531X0689Y0000R270S0
317/OUT_R J3 -4 D0433PA00X+077717Y-038031X0689Y0000R270S0
327NET-(JP2-A) JP2 -1 A01X+068819Y-044831X0394Y0197R090S2
327GND JP2 -2 A01X+068819Y-045343X0394Y0197R090S2
327+3V3 C3 -1 A01X+069537Y-031516X1024Y0630R090S2
327GND C3 -2 A01X+069537Y-032933X1024Y0630R090S2
327PWM_R Q3 -1 A01X+072021Y-037174X0866Y0472R000S2
327/OUT_R Q3 -2 A01X+073842Y-037471X1201Y1083R000S3
327/OUT_R Q3 -2 A01X+073842Y-038672X1201Y1083R000S3
327/OUT_R Q3 -2 A01X+074501Y-038072X2520Y2283R000S2
327/OUT_R Q3 -2 A01X+075160Y-037471X1201Y1083R000S3
327/OUT_R Q3 -2 A01X+075160Y-038672X1201Y1083R000S3
327GND Q3 -3 A01X+072021Y-038969X0866Y0472R000S2
327GND U4 -1 A01X+067657Y-031895X0522Y0236R090S2
327NET-(U4-SW) U4 -2 A01X+067283Y-031895X0522Y0236R090S2
327+24V U4 -3 A01X+066909Y-031895X0522Y0236R090S2
327NET-(U4-FB) U4 -4 A01X+066909Y-032790X0522Y0236R090S2
327NET-(U4-EN) U4 -5 A01X+067283Y-032790X0522Y0236R090S2
327NET-(U4-BOOT) U4 -6 A01X+067657Y-032790X0522Y0236R090S2
317NET-(JP5-A) JP5 -1 D0315PA00X+065945Y-044587X0551Y0000R270S0
317+3V3 JP5 -2 D0315PA00X+065945Y-043587X0551Y0000R270S0
327PWM_G R8 -1 A01X+071161Y-040522X0315Y0374R090S2
327GND R8 -2 A01X+071161Y-041171X0315Y0374R090S2
327NET-(JP3-A) JP3 -1 A01X+069803Y-044831X0394Y0197R090S2
327GND JP3 -2 A01X+069803Y-045343X0394Y0197R090S2
317+24V J1 -1 D0433PA00X+063307Y-032913X0689Y0689R090S0
317GND J1 -2 D0433PA00X+063307Y-034413X0689Y0000R090S0
317/CANL J1 -3 D0433PA00X+063307Y-035913X0689Y0000R090S0
317/CANH J1 -4 D0433PA00X+063307Y-037413X0689Y0000R090S0
327PWM_R R7 -1 A01X+071161Y-037766X0315Y0374R090S2
327GND R7 -2 A01X+071161Y-038415X0315Y0374R090S2
327NET-(U4-FB) R2 -1 A01X+066909Y-033720X0315Y0374R000S2
327GND R2 -2 A01X+067559Y-033720X0315Y0374R000S2
317+3V3 J4 -1 D0394PA00X+065945Y-042142X0669Y0669R180S0
317/SWDIO J4 -2 D0394PA00X+065945Y-041142X0669Y0669R180S0
317/SWCLK J4 -3 D0394PA00X+065945Y-040142X0669Y0669R180S0
317GND J4 -4 D0394PA00X+065945Y-039142X0669Y0669R180S0
327NET-(U3-RS) R4 -1 A01X+066998Y-038681X0315Y0374R000S2
327GND R4 -2 A01X+067648Y-038681X0315Y0374R000S2
327NET-(U1-PA6) R16 -1 A01X+070551Y-036211X0315Y0374R270S2
327PWM_CW R16 -2 A01X+070551Y-035561X0315Y0374R270S2
327CAN_TX U3 -1 A01X+067805Y-037955X0768Y0236R180S2
327GND U3 -2 A01X+067805Y-037455X0768Y0236R180S2
327+3V3 U3 -3 A01X+067805Y-036955X0768Y0236R180S2
327CAN_RX U3 -4 A01X+067805Y-036455X0768Y0236R180S2
327+3V3 U3 -5 A01X+065856Y-036455X0768Y0236R180S2
327/CANL U3 -6 A01X+065856Y-036955X0768Y0236R180S2
327/CANH U3 -7 A01X+065856Y-037455X0768Y0236R180S2
327NET-(U3-RS) U3 -8 A01X+065856Y-037955X0768Y0236R180S2
327PWM_B Q5 -1 A01X+072021Y-042725X0866Y0472R000S2
327/OUT_B Q5 -2 A01X+073842Y-043023X1201Y1083R000S3
327/OUT_B Q5 -2 A01X+073842Y-044223X1201Y1083R000S3
327/OUT_B Q5 -2 A01X+074501Y-043623X2520Y2283R000S2
327/OUT_B Q5 -2 A01X+075160Y-043023X1201Y1083R000S3
327/OUT_B Q5 -2 A01X+075160Y-044223X1201Y1083R000S3
327GND Q5 -3 A01X+072021Y-044521X0866Y0472R000S2
327ET-(U1-~{RST}) C7 -1 A01X+067864Y-043524X0354Y0374R180S2
327GND C7 -2 A01X+067254Y-043524X0354Y0374R180S2
327PWM_WW Q1 -1 A01X+072021Y-031623X0866Y0472R000S2
327/OUT_WW Q1 -2 A01X+073842Y-031920X1201Y1083R000S3
327/OUT_WW Q1 -2 A01X+073842Y-033121X1201Y1083R000S3
327/OUT_WW Q1 -2 A01X+074501Y-032521X2520Y2283R000S2
327/OUT_WW Q1 -2 A01X+075160Y-031920X1201Y1083R000S3
327/OUT_WW Q1 -2 A01X+075160Y-033121X1201Y1083R000S3
327GND Q1 -3 A01X+072021Y-033418X0866Y0472R000S2
327CAN_TX TP1 -1 A01X+068898Y-038386X0591Y0000R000S2
327PWM_G Q4 -1 A01X+072021Y-039950X0866Y0472R000S2
327/OUT_G Q4 -2 A01X+073842Y-040247X1201Y1083R000S3
327/OUT_G Q4 -2 A01X+073842Y-041448X1201Y1083R000S3
327/OUT_G Q4 -2 A01X+074501Y-040847X2520Y2283R000S2
327/OUT_G Q4 -2 A01X+075160Y-040247X1201Y1083R000S3
327/OUT_G Q4 -2 A01X+075160Y-041448X1201Y1083R000S3
327GND Q4 -3 A01X+072021Y-041745X0866Y0472R000S2
327NET-(U1-PA1) R13 -1 A01X+070551Y-038406X0315Y0374R270S2
327PWM_R R13 -2 A01X+070551Y-037756X0315Y0374R270S2
327+24V C5 -1 A01X+066299Y-031939X0354Y0374R090S2
327GND C5 -2 A01X+066299Y-032549X0354Y0374R090S2
327PWM_CW Q2 -1 A01X+072021Y-034402X0866Y0472R000S2
327/OUT_CW Q2 -2 A01X+073842Y-034699X1201Y1083R000S3
327/OUT_CW Q2 -2 A01X+073842Y-035900X1201Y1083R000S3
327/OUT_CW Q2 -2 A01X+074501Y-035299X2520Y2283R000S2
327/OUT_CW Q2 -2 A01X+075160Y-034699X1201Y1083R000S3
327/OUT_CW Q2 -2 A01X+075160Y-035900X1201Y1083R000S3
327GND Q2 -3 A01X+072021Y-036197X0866Y0472R000S2
317+24V J2 -1 D0433PA00X+077717Y-035756X0689Y0689R270S0
317/OUT_CW J2 -2 D0433PA00X+077717Y-034256X0689Y0000R270S0
317/OUT_WW J2 -3 D0433PA00X+077717Y-032756X0689Y0000R270S0
327NET-(U4-EN) R10 -1 A01X+066201Y-033327X0315Y0374R180S2
327+24V R10 -2 A01X+065551Y-033327X0315Y0374R180S2
327NET-(JP5-A) U1 -1 A01X+067254Y-042662X0581Y0157R270S2
3271-OSC_IN-PAD2) U1 -2 A01X+067510Y-042662X0581Y0157R270S2
327-OSC_OUT-PAD3) U1 -3 A01X+067766Y-042662X0581Y0157R270S2
327ET-(U1-~{RST}) U1 -4 A01X+068022Y-042662X0581Y0157R270S2
327+3V3 U1 -5 A01X+068278Y-042662X0581Y0157R270S2
327NET-(JP1-A) U1 -6 A01X+068533Y-042662X0581Y0157R270S2
327NET-(U1-PA1) U1 -7 A01X+068789Y-042662X0581Y0157R270S2
327NET-(U1-PA2) U1 -8 A01X+069045Y-042662X0581Y0157R270S2
327NET-(U1-PA3) U1 -9 A01X+069301Y-042662X0581Y0157R270S2
327NET-(JP2-A) U1 -10 A01X+069557Y-042662X0581Y0157R270S2
327NET-(JP3-A) U1 -11 A01X+069557Y-040408X0581Y0157R270S2
327NET-(U1-PA6) U1 -12 A01X+069301Y-040408X0581Y0157R270S2
327NET-(U1-PA7) U1 -13 A01X+069045Y-040408X0581Y0157R270S2
327NET-(JP4-B) U1 -14 A01X+068789Y-040408X0581Y0157R270S2
327GND U1 -15 A01X+068533Y-040408X0581Y0157R270S2
327+3V3 U1 -16 A01X+068278Y-040408X0581Y0157R270S2
327CAN_RX U1 -17 A01X+068022Y-040408X0581Y0157R270S2
327CAN_TX U1 -18 A01X+067766Y-040408X0581Y0157R270S2
327/SWDIO U1 -19 A01X+067510Y-040408X0581Y0157R270S2
327/SWCLK U1 -20 A01X+067254Y-040408X0581Y0157R270S2
367N/C REF** D1260UA00X+077953Y-029921X1260Y0000R000S0
327NET-(U1-PA7) R17 -1 A01X+073002Y-030748X0315Y0374R180S2
327PWM_WW R17 -2 A01X+072352Y-030748X0315Y0374R180S2
327NET-(U4-EN) R11 -1 A01X+066201Y-033957X0315Y0374R180S2
327GND R11 -2 A01X+065551Y-033957X0315Y0374R180S2
327NET-(JP5-A) R12 -1 A01X+066752Y-044852X0315Y0374R270S2
327GND R12 -2 A01X+066752Y-044203X0315Y0374R270S2
327NET-(U4-SW) C6 -1 A01X+068268Y-032470X0354Y0374R090S2
327NET-(U4-BOOT) C6 -2 A01X+068268Y-033081X0354Y0374R090S2
327NET-(U4-SW) L1 -1 A01X+067175Y-030571X0391Y0906R180S2
327+3V3 L1 -2 A01X+068415Y-030571X0394Y0906R180S2
327PWM_WW R5 -1 A01X+072352Y-030118X0315Y0374R000S2
327GND R5 -2 A01X+073002Y-030118X0315Y0374R000S2
999