From 8ecd7f34164f8fce3589573faced6c0fe3b0c211 Mon Sep 17 00:00:00 2001 From: Jakob Lechner Date: Wed, 20 Aug 2025 11:07:16 +0200 Subject: [PATCH] Add PCB --- dimmer-pcb/.gitignore | 40 + dimmer-pcb/L_TECHFUSE_SL0420.kicad_mod | 1 + dimmer-pcb/bom/ibom.html | 4669 ++++ dimmer-pcb/dimmer-pcb.kicad_dru | 132 + dimmer-pcb/dimmer-pcb.kicad_pcb | 17911 ++++++++++++++++ dimmer-pcb/dimmer-pcb.kicad_pro | 705 + dimmer-pcb/dimmer-pcb.kicad_sch | 10966 ++++++++++ dimmer-pcb/fabrication-toolkit-options.json | 1 + dimmer-pcb/fp-lib-table | 4 + .../dimmer-pcb_2025-03-16_23-41-49.zip | Bin 0 -> 59849 bytes dimmer-pcb/production/dimmer-pcb.zip | Bin 0 -> 58041 bytes dimmer-pcb/production/netlist.ipc | 205 + 12 files changed, 34634 insertions(+) create mode 100644 dimmer-pcb/.gitignore create mode 100644 dimmer-pcb/L_TECHFUSE_SL0420.kicad_mod create mode 100644 dimmer-pcb/bom/ibom.html create mode 100644 dimmer-pcb/dimmer-pcb.kicad_dru create mode 100644 dimmer-pcb/dimmer-pcb.kicad_pcb create mode 100644 dimmer-pcb/dimmer-pcb.kicad_pro create mode 100644 dimmer-pcb/dimmer-pcb.kicad_sch create mode 100644 dimmer-pcb/fabrication-toolkit-options.json create mode 100644 dimmer-pcb/fp-lib-table create mode 100644 dimmer-pcb/production/backups/dimmer-pcb_2025-03-16_23-41-49.zip create mode 100644 dimmer-pcb/production/dimmer-pcb.zip create mode 100644 dimmer-pcb/production/netlist.ipc diff --git a/dimmer-pcb/.gitignore b/dimmer-pcb/.gitignore new file mode 100644 index 0000000..9d5df93 --- /dev/null +++ b/dimmer-pcb/.gitignore @@ -0,0 +1,40 @@ +# For PCBs designed using KiCad: https://www.kicad.org/ +# Format documentation: https://kicad.org/help/file-formats/ + +# Temporary files +*.000 +*.bak +*.bck +*.kicad_pcb-bak +*.kicad_sch-bak +*-backups +*-cache* +*-bak +*-bak* +*~ +~* +_autosave-* +\#auto_saved_files\# +*.tmp +*-save.pro +*-save.kicad_pcb +fp-info-cache +~*.lck +\#auto_saved_files# + +# Netlist files (exported from Eeschema) +*.net + +# Autorouter files (exported from Pcbnew) +*.dsn +*.ses + +# Exported BOM files +*.xml +*.csv + +# Archived Backups (KiCad 6.0) +**/*-backups/*.zip + +# Local project settings +*.kicad_prl diff --git a/dimmer-pcb/L_TECHFUSE_SL0420.kicad_mod b/dimmer-pcb/L_TECHFUSE_SL0420.kicad_mod new file mode 100644 index 0000000..18082f1 --- /dev/null +++ b/dimmer-pcb/L_TECHFUSE_SL0420.kicad_mod @@ -0,0 +1 @@ +(footprint "L_Coilcraft_MSS1260T-XXX"(version 20241229) (generator "pcbnew") (generator_version "9.0")(layer "F.Cu" )(descr "Inductor, Coilcraft, MSS1260T-XXX, 12.0x12.0x6.0mm, (https://www.coilcraft.com/getmedia/ce88ed45-272e-474e-a25e-981003944639/mss1260t.pdf), generated with kicad-footprint-generator gen_inductor.py")(tags "Inductor mss")(property "Reference" "REF**"(at 0 -7 0)(layer "F.SilkS" )(uuid "9a7ada28-5148-4377-babe-dd21dce87330")(effects(font(size 1 1)(thickness 0.15))))(property "Value" "L_TECHFUSE_SL0420"(at 0 7 0)(layer "F.Fab" )(uuid "b23a84ce-8da0-4b44-bbbf-83f9a6d64b49")(effects(font(size 1 1)(thickness 0.15))))(property "Datasheet" ""(at 0 0 0)(layer "F.Fab" )(hide yes)(uuid "4a7ae4ff-69e7-4a6c-8a54-e5767493573f")(effects(font(size 1.27 1.27)(thickness 0.15))))(property "Description" ""(at 0 0 0)(layer "F.Fab" )(hide yes)(uuid "244bd214-0e7a-424d-b4cb-ec8e8ee5278f")(effects(font(size 1.27 1.27)(thickness 0.15))))(attr smd)(fp_line (start -6.26 -6.26) (end -6.26 -3.01)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "55db190c-ca42-4b61-8c68-5eeb3cd55db3"))(fp_line (start -6.26 -6.26) (end -4.61 -6.26)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "141f6cf9-c972-4d87-91c5-7324e585efd7"))(fp_line (start -6.26 6.26) (end -6.26 3.01)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "01f28edf-ff01-4076-89b9-0c89c3adeb32"))(fp_line (start -6.26 6.26) (end 6.26 6.26)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid "e0475cc7-2c24-4de9-bd2b-806f27311307"))(fp_line (start -3.89 -6.26) (end 6.26 -6.26)(stroke (width 0.12) (type solid))(layer "F.SilkS" )(uuid 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roundrect(at 2.475 0 )(size 0.99375 2.3)(layers "F.Cu" "F.Mask" "F.Paste")(roundrect_rratio 0.0625)(uuid "b3dab13c-3eef-4394-96b1-50e95a77e6dd"))(pad "2" smd roundrect(at -2.475 0 )(size 1 2.3)(layers "F.Cu" "F.Mask" "F.Paste")(roundrect_rratio 0.0625)(uuid "32149c47-0ccf-40d6-b630-83d775f5c0e1"))(embedded_fonts no)(model "${KICAD9_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Coilcraft_MSS1260T-XXX.wrl"(offset (xyz 0 0 0))(scale (xyz 1 1 1))(rotate (xyz 0 0 0)))) \ No newline at end of file diff --git a/dimmer-pcb/bom/ibom.html b/dimmer-pcb/bom/ibom.html new file mode 100644 index 0000000..87d063c --- /dev/null +++ b/dimmer-pcb/bom/ibom.html @@ -0,0 +1,4669 @@ + + + + + + + Interactive BOM for KiCAD + + + + + + +
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+ Title + + Revision +
+ Company + + Date +
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Board statsFrontBackTotal
Components~~~
Groups~~~
SMD pads~~~
TH pads~
+ + + + + + + +
Checkboxes
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+
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+ +
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+
Save board image
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+ + X + +
+ +
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+ Config and checkbox state +
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+ Save bom table as +
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+ + + + diff --git a/dimmer-pcb/dimmer-pcb.kicad_dru b/dimmer-pcb/dimmer-pcb.kicad_dru new file mode 100644 index 0000000..21b84c1 --- /dev/null +++ b/dimmer-pcb/dimmer-pcb.kicad_dru @@ -0,0 +1,132 @@ +(version 1) +# Custom Design Rules (DRC) for KiCAD 7.0 (Stored in '.kicad_dru' file). +# +# Matching JLCPCB capabilities: https://jlcpcb.com/capabilities/pcb-capabilities +# +# KiCad documentation: https://docs.kicad.org/master/id/pcbnew/pcbnew_advanced.html#custom_design_rules +# +# Inspiration +# - https://gist.github.com/darkxst/f713268e5469645425eed40115fb8b49 (with comments) +# - https://gist.github.com/denniskupec/e163d13b0a64c2044bd259f64659485e (with comments) + +# TODO new rule: NPTH pads. +# Inner diameter of pad should be 0.4-0.5 mm larger than NPTH drill diameter. +# JLCPCB: "We make NPTH via dry sealing film process, if customer would like a NPTH but around with pad/copper, our engineer will dig out around pad/copper about 0.2mm-0.25mm, otherwise the metal potion will be flowed into the hole and it becomes a PTH. (there will be no copper dig out optimization for single board)." + +# TODO: new rule for plated slots: min diameter/width 0.5mm +# JLCPCB: "The minimum plated slot width is 0.5mm, which is drawn with a pad." + +# TODO new rule: non-plated slots: min diameter/width 1.0mm +# JLCPCB: "The minimum Non-Plated Slot Width is 1.0mm, please draw the slot outline in the mechanical layer(GML or GKO)"" + +(rule "Track width, outer layer (1oz copper)" + (layer outer) + (condition "A.Type == 'track'") + (constraint track_width (min 0.127mm)) +) + +(rule "Track spacing, outer layer (1oz copper)" + (layer outer) + (condition "A.Type == 'track' && B.Type == A.Type") + (constraint clearance (min 0.127mm)) +) + +(rule "Track width, inner layer" + (layer inner) + (condition "A.Type == 'track'") + (constraint track_width (min 0.09mm)) +) + +(rule "Track spacing, inner layer" + (layer inner) + (condition "A.Type == 'track' && B.Type == A.Type") + (constraint clearance (min 0.09mm)) +) + +(rule "Silkscreen text" + (layer "?.Silkscreen") + (condition "A.Type == 'Text' || A.Type == 'Text Box'") + (constraint text_thickness (min 0.15mm)) + (constraint text_height (min 1mm)) +) + +(rule "Pad to Silkscreen" + (layer outer) + (condition "A.Type == 'pad' && B.Layer == '?.Silkscreen'") + (constraint silk_clearance (min 0.15mm)) +) + +(rule "Edge (routed) to track clearance" + (condition "A.Type == 'track'") + (constraint edge_clearance (min 0.3mm)) +) + +#(rule "Edge (v-cut) to track clearance" +# (condition "A.Type == 'track'") +# (constraint edge_clearance (min 0.4mm)) +#) + +# JLCPCB restrictions ambiguous: +# Illustration: 0.2 mm, 1&2 layer: 0.3 mm, multilayer: "(0.15mm more costly)" +# This rule handles diameter minimum and maximum for ALL holes. +# Other specialized rules handle restrictions (e.g. Via, PTH, NPTH) +(rule "Hole diameter" + (constraint hole_size (min 0.2mm) (max 6.3mm)) +) + +(rule "Hole (NPTH) diameter" + (layer outer) + (condition "!A.isPlated()") + (constraint hole_size (min 0.5mm)) +) + +# TODO: Hole to board edge ≥ 1 mm. Min. board size 10 × 10 mm +(rule "Hole (castellated) diameter" + (layer outer) + (condition "A.Type == 'pad' && A.Fabrication_Property == 'Castellated pad'") + (constraint hole_size (min 0.6mm)) +) + +# JLCPCB: "Via diameter should be 0.1mm(0.15mm preferred) larger than Via hole size" (illustration shows diameters for both dimensions) +# JLCPCB: PTH: "The annular ring size will be enlarged to 0.15mm in production." +(rule "Annular ring width (via and PTH)" + (layer outer) + (condition "A.isPlated()") + (constraint annular_width (min 0.075mm)) +) + +(rule "Clearance: hole to hole (perimeter), different nets" + (layer outer) + (condition "A.Net != B.Net") + (constraint hole_to_hole (min 0.5mm)) +) + +(rule "Clearance: hole to hole (perimeter), same net" + (layer outer) + (condition "A.Net == B.Net") + (constraint hole_to_hole (min 0.254mm)) +) + +(rule "Clearance: track to NPTH hole (perimeter)" +# (condition "A.Pad_Type == 'NPTH, mechanical' && B.Type == 'track' && A.Net != B.Net") + (condition "!A.isPlated() && B.Type == 'track' && A.Net != B.Net") + (constraint hole_clearance (min 0.254mm)) +) + +(rule "Clearance: track to PTH hole perimeter" + (condition "A.isPlated() && B.Type == 'track' && A.Net != B.Net") + (constraint hole_clearance (min 0.33mm)) +) + +# TODO: try combining with rule "Clearance: PTH to track, different nets" +(rule "Clearance: track to pad" + (condition "A.Type == 'pad' && B.Type == 'track' && A.Net != B.Net") + (constraint clearance (min 0.2mm)) +) + +(rule "Clearance: pad/via to pad/via" + (layer outer) +# (condition "(A.Type == 'Pad' || A.Type == 'Via') && (B.Type == 'Pad' || B.Type == 'Via') && A.Net != B.Net") + (condition "A.isPlated() && B.isPlated() && A.Net != B.Net") + (constraint clearance (min 0.127mm)) +) \ No newline at end of file diff --git a/dimmer-pcb/dimmer-pcb.kicad_pcb b/dimmer-pcb/dimmer-pcb.kicad_pcb new file mode 100644 index 0000000..c206a01 --- /dev/null +++ b/dimmer-pcb/dimmer-pcb.kicad_pcb @@ -0,0 +1,17911 @@ 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0x00000000_00000000_55555555_5755f5ff) + (plot_on_all_layers_selection 0x00000000_00000000_00000000_00000000) + (disableapertmacros no) + (usegerberextensions no) + (usegerberattributes yes) + (usegerberadvancedattributes yes) + (creategerberjobfile yes) + (dashed_line_dash_ratio 12.000000) + (dashed_line_gap_ratio 3.000000) + (svgprecision 4) + (plotframeref no) + (mode 1) + (useauxorigin no) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (pdf_front_fp_property_popups yes) + (pdf_back_fp_property_popups yes) + (pdf_metadata yes) + (pdf_single_document no) + (dxfpolygonmode yes) + (dxfimperialunits yes) + (dxfusepcbnewfont yes) + (psnegative no) + (psa4output no) + (plot_black_and_white yes) + (plotinvisibletext no) + (sketchpadsonfab no) + (plotpadnumbers no) + (hidednponfab no) + (sketchdnponfab yes) + (crossoutdnponfab yes) + (subtractmaskfromsilk no) + (outputformat 1) + (mirror no) + (drillshape 1) + (scaleselection 1) + (outputdirectory "") + ) + ) + (net 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MD0118PA00X+072717Y-036063X0236Y0000R000S3 +317GND VIA MD0118PA00X+069173Y-039488X0236Y0000R000S3 +317GND VIA MD0118PA00X+069134Y-032362X0236Y0000R000S3 +317GND VIA MD0118PA00X+072717Y-033543X0236Y0000R000S3 +317GND VIA MD0118PA00X+066024Y-032835X0236Y0000R000S3 +317GND VIA MD0118PA00X+065157Y-033976X0236Y0000R000S3 +317GND VIA MD0118PA00X+066752Y-043740X0236Y0000R000S3 +317GND VIA MD0118PA00X+071299Y-038858X0236Y0000R000S3 +317GND VIA MD0118PA00X+067913Y-031850X0236Y0000R000S3 +317GND VIA MD0118PA00X+069094Y-033110X0236Y0000R000S3 +317GND VIA MD0118PA00X+067677Y-031496X0236Y0000R000S3 +317GND VIA MD0118PA00X+067835Y-045748X0236Y0000R000S3 +317GND VIA MD0118PA00X+069321Y-043189X0236Y0000R000S3 +317GND VIA MD0118PA00X+069094Y-032874X0236Y0000R000S3 +317GND VIA MD0118PA00X+069094Y-032638X0236Y0000R000S3 +317GND VIA MD0118PA00X+072717Y-033268X0236Y0000R000S3 +317GND VIA MD0118PA00X+071299Y-039134X0236Y0000R000S3 +317GND VIA MD0118PA00X+072717Y-036339X0236Y0000R000S3 +317GND VIA MD0118PA00X+072717Y-041614X0236Y0000R000S3 +317GND VIA MD0118PA00X+069803Y-045748X0236Y0000R000S3 +317GND VIA MD0118PA00X+070787Y-045748X0236Y0000R000S3 +317GND VIA MD0118PA00X+066575Y-032756X0236Y0000R000S3 +317GND VIA MD0118PA00X+069016Y-037480X0236Y0000R000S3 +317GND VIA MD0118PA00X+072717Y-041890X0236Y0000R000S3 +317GND VIA MD0118PA00X+065433Y-032402X0236Y0000R000S3 +317GND VIA MD0118PA00X+065669Y-032402X0236Y0000R000S3 +317GND VIA MD0118PA00X+072717Y-044685X0236Y0000R000S3 +317GND VIA MD0118PA00X+068819Y-045748X0236Y0000R000S3 +317GND VIA MD0118PA00X+065906Y-032402X0236Y0000R000S3 +317GND VIA MD0118PA00X+073406Y-030138X0236Y0000R000S3 +317NET-(JP3-A) VIA MD0118PA00X+070020Y-042496X0236Y0000R000S3 +317NET-(JP3-A) VIA MD0118PA00X+069465Y-041343X0236Y0000R000S3 +317NET-(JP4-B) VIA MD0118PA00X+069164Y-041664X0236Y0000R000S3 +317NET-(JP4-B) VIA MD0118PA00X+069779Y-042260X0236Y0000R000S3 +317NET-(U4-EN) VIA MD0118PA00X+067165Y-033327X0236Y0000R000S3 +317NET-(U4-EN) VIA MD0118PA00X+066654Y-033327X0236Y0000R000S3 +317NET-(U1-PA7) VIA MD0118PA00X+070543Y-039075X0236Y0000R000S3 +317NET-(U1-PA7) VIA MD0118PA00X+069941Y-039075X0236Y0000R000S3 +327GND C10 -1 A01X+068602Y-037510X0354Y0374R270S2 +327+3V3 C10 -2 A01X+068602Y-036900X0354Y0374R270S2 +327NET-(U4-FB) R3 -1 A01X+066909Y-034980X0315Y0374R000S2 +327NET-(C1-PAD2) R3 -2 A01X+067559Y-034980X0315Y0374R000S2 +327GND JP4 -1 A01X+070787Y-045343X0394Y0197R270S2 +327NET-(JP4-B) JP4 -2 A01X+070787Y-044831X0394Y0197R270S2 +367N/C REF** D1260UA00X+077953Y-044882X1260Y0000R000S0 +327+24V C4 -1 A01X+065610Y-031969X0394Y0571R090S2 +327GND C4 -2 A01X+065610Y-032717X0394Y0571R090S2 +367N/C REF** D1260UA00X+062992Y-044882X1260Y0000R000S0 +327+3V3 C8 -1 A01X+068120Y-039665X0354Y0374R000S2 +327GND C8 -2 A01X+068730Y-039665X0354Y0374R000S2 +327+3V3 C9 -1 A01X+068455Y-043524X0354Y0374R000S2 +327GND C9 -2 A01X+069065Y-043524X0354Y0374R000S2 +367N/C REF** D1260UA00X+062992Y-029921X1260Y0000R000S0 +327CAN_RX TP2 -1 A01X+069291Y-036220X0591Y0000R000S2 +327PWM_CW R6 -1 A01X+071161Y-035561X0315Y0374R090S2 +327GND R6 -2 A01X+071161Y-036211X0315Y0374R090S2 +327+3V3 R1 -1 A01X+068730Y-034350X0315Y0374R180S2 +327NET-(C1-PAD2) R1 -2 A01X+068081Y-034350X0315Y0374R180S2 +327NET-(JP1-A) JP1 -1 A01X+067835Y-044831X0394Y0197R090S2 +327GND JP1 -2 A01X+067835Y-045343X0394Y0197R090S2 +327NET-(U1-PA2) R14 -1 A01X+070551Y-041161X0315Y0374R270S2 +327PWM_G R14 -2 A01X+070551Y-040512X0315Y0374R270S2 +327NET-(U1-PA3) R15 -1 A01X+070541Y-042136X0315Y0374R000S2 +327PWM_B R15 -2 A01X+071191Y-042136X0315Y0374R000S2 +327NET-(U4-FB) C1 -1 A01X+066909Y-034350X0354Y0374R000S2 +327NET-(C1-PAD2) C1 -2 A01X+067520Y-034350X0354Y0374R000S2 +327PWM_B R9 -1 A01X+071161Y-043278X0315Y0374R090S2 +327GND R9 -2 A01X+071161Y-043927X0315Y0374R090S2 +317+24V J3 -1 D0433PA00X+077717Y-042531X0689Y0689R270S0 +317/OUT_B J3 -2 D0433PA00X+077717Y-041031X0689Y0000R270S0 +317/OUT_G J3 -3 D0433PA00X+077717Y-039531X0689Y0000R270S0 +317/OUT_R J3 -4 D0433PA00X+077717Y-038031X0689Y0000R270S0 +327NET-(JP2-A) JP2 -1 A01X+068819Y-044831X0394Y0197R090S2 +327GND JP2 -2 A01X+068819Y-045343X0394Y0197R090S2 +327+3V3 C3 -1 A01X+069537Y-031516X1024Y0630R090S2 +327GND C3 -2 A01X+069537Y-032933X1024Y0630R090S2 +327PWM_R Q3 -1 A01X+072021Y-037174X0866Y0472R000S2 +327/OUT_R Q3 -2 A01X+073842Y-037471X1201Y1083R000S3 +327/OUT_R Q3 -2 A01X+073842Y-038672X1201Y1083R000S3 +327/OUT_R Q3 -2 A01X+074501Y-038072X2520Y2283R000S2 +327/OUT_R Q3 -2 A01X+075160Y-037471X1201Y1083R000S3 +327/OUT_R Q3 -2 A01X+075160Y-038672X1201Y1083R000S3 +327GND Q3 -3 A01X+072021Y-038969X0866Y0472R000S2 +327GND U4 -1 A01X+067657Y-031895X0522Y0236R090S2 +327NET-(U4-SW) U4 -2 A01X+067283Y-031895X0522Y0236R090S2 +327+24V U4 -3 A01X+066909Y-031895X0522Y0236R090S2 +327NET-(U4-FB) U4 -4 A01X+066909Y-032790X0522Y0236R090S2 +327NET-(U4-EN) U4 -5 A01X+067283Y-032790X0522Y0236R090S2 +327NET-(U4-BOOT) U4 -6 A01X+067657Y-032790X0522Y0236R090S2 +317NET-(JP5-A) JP5 -1 D0315PA00X+065945Y-044587X0551Y0000R270S0 +317+3V3 JP5 -2 D0315PA00X+065945Y-043587X0551Y0000R270S0 +327PWM_G R8 -1 A01X+071161Y-040522X0315Y0374R090S2 +327GND R8 -2 A01X+071161Y-041171X0315Y0374R090S2 +327NET-(JP3-A) JP3 -1 A01X+069803Y-044831X0394Y0197R090S2 +327GND JP3 -2 A01X+069803Y-045343X0394Y0197R090S2 +317+24V J1 -1 D0433PA00X+063307Y-032913X0689Y0689R090S0 +317GND J1 -2 D0433PA00X+063307Y-034413X0689Y0000R090S0 +317/CANL J1 -3 D0433PA00X+063307Y-035913X0689Y0000R090S0 +317/CANH J1 -4 D0433PA00X+063307Y-037413X0689Y0000R090S0 +327PWM_R R7 -1 A01X+071161Y-037766X0315Y0374R090S2 +327GND R7 -2 A01X+071161Y-038415X0315Y0374R090S2 +327NET-(U4-FB) R2 -1 A01X+066909Y-033720X0315Y0374R000S2 +327GND R2 -2 A01X+067559Y-033720X0315Y0374R000S2 +317+3V3 J4 -1 D0394PA00X+065945Y-042142X0669Y0669R180S0 +317/SWDIO J4 -2 D0394PA00X+065945Y-041142X0669Y0669R180S0 +317/SWCLK J4 -3 D0394PA00X+065945Y-040142X0669Y0669R180S0 +317GND J4 -4 D0394PA00X+065945Y-039142X0669Y0669R180S0 +327NET-(U3-RS) R4 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A01X+070551Y-037756X0315Y0374R270S2 +327+24V C5 -1 A01X+066299Y-031939X0354Y0374R090S2 +327GND C5 -2 A01X+066299Y-032549X0354Y0374R090S2 +327PWM_CW Q2 -1 A01X+072021Y-034402X0866Y0472R000S2 +327/OUT_CW Q2 -2 A01X+073842Y-034699X1201Y1083R000S3 +327/OUT_CW Q2 -2 A01X+073842Y-035900X1201Y1083R000S3 +327/OUT_CW Q2 -2 A01X+074501Y-035299X2520Y2283R000S2 +327/OUT_CW Q2 -2 A01X+075160Y-034699X1201Y1083R000S3 +327/OUT_CW Q2 -2 A01X+075160Y-035900X1201Y1083R000S3 +327GND Q2 -3 A01X+072021Y-036197X0866Y0472R000S2 +317+24V J2 -1 D0433PA00X+077717Y-035756X0689Y0689R270S0 +317/OUT_CW J2 -2 D0433PA00X+077717Y-034256X0689Y0000R270S0 +317/OUT_WW J2 -3 D0433PA00X+077717Y-032756X0689Y0000R270S0 +327NET-(U4-EN) R10 -1 A01X+066201Y-033327X0315Y0374R180S2 +327+24V R10 -2 A01X+065551Y-033327X0315Y0374R180S2 +327NET-(JP5-A) U1 -1 A01X+067254Y-042662X0581Y0157R270S2 +3271-OSC_IN-PAD2) U1 -2 A01X+067510Y-042662X0581Y0157R270S2 +327-OSC_OUT-PAD3) U1 -3 A01X+067766Y-042662X0581Y0157R270S2 +327ET-(U1-~{RST}) U1 -4 A01X+068022Y-042662X0581Y0157R270S2 +327+3V3 U1 -5 A01X+068278Y-042662X0581Y0157R270S2 +327NET-(JP1-A) U1 -6 A01X+068533Y-042662X0581Y0157R270S2 +327NET-(U1-PA1) U1 -7 A01X+068789Y-042662X0581Y0157R270S2 +327NET-(U1-PA2) U1 -8 A01X+069045Y-042662X0581Y0157R270S2 +327NET-(U1-PA3) U1 -9 A01X+069301Y-042662X0581Y0157R270S2 +327NET-(JP2-A) U1 -10 A01X+069557Y-042662X0581Y0157R270S2 +327NET-(JP3-A) U1 -11 A01X+069557Y-040408X0581Y0157R270S2 +327NET-(U1-PA6) U1 -12 A01X+069301Y-040408X0581Y0157R270S2 +327NET-(U1-PA7) U1 -13 A01X+069045Y-040408X0581Y0157R270S2 +327NET-(JP4-B) U1 -14 A01X+068789Y-040408X0581Y0157R270S2 +327GND U1 -15 A01X+068533Y-040408X0581Y0157R270S2 +327+3V3 U1 -16 A01X+068278Y-040408X0581Y0157R270S2 +327CAN_RX U1 -17 A01X+068022Y-040408X0581Y0157R270S2 +327CAN_TX U1 -18 A01X+067766Y-040408X0581Y0157R270S2 +327/SWDIO U1 -19 A01X+067510Y-040408X0581Y0157R270S2 +327/SWCLK U1 -20 A01X+067254Y-040408X0581Y0157R270S2 +367N/C REF** D1260UA00X+077953Y-029921X1260Y0000R000S0 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