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add update boot, обновление скриптов сборки и прошивки

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pvvx 2024-02-25 06:41:34 +03:00
parent 947b371563
commit 6c3c1c920a
63 changed files with 15697 additions and 39 deletions
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27
README.md
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@ -21,6 +21,10 @@ Custom firmware for Tuya devices on the PHY622x2 chipset
| [TH05_V1.3](https://pvvx.github.io/TH05-v1.3) | BOOT_TH05D_v14.hex | TH05D_v14.bin | RSH-TH05-V1.3 с чипом BL55072 |
| [TH05F](https://pvvx.github.io/TH05F) | BOOT_TH05F_v14.hex | TH05F_v14.bin | TH05Y_V1.1, TH05Y_V1.2 с чипом QD01 2332 NT |
Основные файлы прошивок, BOOT_xxx_vxx.hex для программирования через USB-COM адаптер и xxx_vxx.bin для OTA, находятся в директории [bin](https://github.com/pvvx/THB2/tree/master/bin).
Файлы для обновления Boot по OTA находятся в директории [update_boot](https://github.com/pvvx/THB2/tree/master/update_boot). Если boot работает нормально, то обновлять на новую версию не требуется. О необходимости замены будет объявлено дополнительно. Актуальная версия boot - v1.4.
## Основные характеристики
! _При настройках по умолчанию_ !
@ -44,11 +48,11 @@ Custom firmware for Tuya devices on the PHY622x2 chipset
| 1.1 | Добавлен триггер - вывод TX2 срабатывающий по установленным значениям температуры и/или влажности с гистерезисами. Передача состояния вывода RX2 при connect. Для термометров с экраном добавлен показ смайлика с "комфортом". Дополнены: изменение имени и MAC устройства. |
| 1.2 | Обработка и передача событий open/close со счетчиком с вывода маркированного "RX2" (для THB2 - "RX1"). |
| 1.3 | Добавлен THB1 и TH05V1.3. Следующий этап уменьшения потребления для версий с LCD дисплеем и опция отключения дисплея. |
| 1.4 | Стабилизация соединения для всех вариантов устройств. Добавлен [TH05F](https://pvvx.github.io/TH05F). Коррекция хода RTC. Изменено BLE имя для TH05_V1.3 на "TH05D" |
| 1.4 | Стабилизация соединения для всех вариантов устройств. Добавлен [TH05F](https://pvvx.github.io/TH05F). Коррекция хода RTC. Изменено BLE имя для TH05_V1.3 на "TH05D". Добавлены файлы для обновления Boot по OTA. |
## Прошивка
Прошить устройство програмой Boot-OTA возможно через USB-COM адаптер с выходами на 3.3В:
Прошить устройство програмой Boot возможно через USB-COM адаптер с выходами на 3.3В:
1. Соединить GND, TX, RX, RTS–RESET, VCC (+3.3B).
@ -60,7 +64,7 @@ Custom firmware for Tuya devices on the PHY622x2 chipset
| RX | TX1 |
| RTS | RESET |
Если на адаптере отсутствует RST пин, во время запуска скрипта следует подключить RESET пин до GND (вомзожно потребуется несколько попыток)
Если на адаптере отсутствует RST пин, тогда следует замкнуть вывод RESET с GND(-Vbat) и быстро разомкнуть при старте скрипта (вомзожно потребуется несколько попыток)
Название контактов на устройстве смотреть в описании по ссылкам: [THB1](https://pvvx.github.io/THB1), [THB2](https://pvvx.github.io/THB2), [BTH01](https://pvvx.github.io/BTH01/), [TH05_V1.3](https://pvvx.github.io/TH05-v1.3), [TH05_V1.4](https://pvvx.github.io/TH-05)
@ -70,21 +74,23 @@ Custom firmware for Tuya devices on the PHY622x2 chipset
pip3 install -r requirements.txt
```
3. Запустить:
3. Скачать необходимый для конкретного устройства файл BOOT_xxx_vxx.hex из директории bin.
4. Запустить:
```txt
python3 rdwr_phy62x2.py -p COM11 -e -r wh BOOT_xxx_vxx.hex
```
4. Прошивка Boot-OTA завершена. Устройство работает. Адаптер можно отсоединить.
5. Прошивка Boot завершена. Устройство работает. Адаптер можно отсоединить.
5. Загружаем полную версию прошивки по OTA. Для этого:
6. Загружаем полную версию прошивки по OTA. Для этого:
1. Подаем питание на датчик (устройство).
2. Переходим на [PHY62x2BTHome.html](https://pvvx.github.io/THB2/web/PHY62x2BTHome.html).
3. Жмем кнопку `Cоединение`, ищем устройство, подключаемся.
3. Жмем кнопку `Соединение`, ищем устройство, подключаемся.
4. После подключение переходим на вкладку `OTA`, выбираем необходимую прошивку и жмем `Старт`.
6. Устройство должно перезагрузиться и быть готово для использования.
7. Устройство должно перезагрузиться и быть готово для использования.
Дополнительно:
@ -92,6 +98,11 @@ python3 rdwr_phy62x2.py -p COM11 -e -r wh BOOT_xxx_vxx.hex
* Для предварительного стирания рабочей области Flash используйте опцию `-e`.
* С помощью USB-COM адаптера возможно сразу дописать основную прошивку (APP)
```
python3 rdwr_phy62x2.py -p COM11 -r we 0x10000 xxx_vxx.bin
```
## Сохранение оригинальной прошивки
1. Соединить GND, TX, RX, RTS–RESET, VCC (+3.3B).

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bin/TH05D_v14.bin
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bin/TH05F_v14.bin
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bin/TH05_v14.bin
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bin/THB1_v14.bin
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bin/THB2_v14.bin
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2
bthome_phy6222/.gitignore vendored
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@ -1,3 +1,5 @@
bin
boot
Listings
Objects
TestTHB2.asm

8
bthome_phy6222/Makefile
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@ -117,11 +117,13 @@ CFLAGS += -Wl,--gc-sections
ifdef BOOT_OTA
LDSCRIPT ?= $(SDK_PATH)/misc/boot_ota_phy62x2.ld
DEFINES += -DOTA_TYPE=OTA_TYPE_BOOT
BIN_OTA =
BIN_OTA = $(OBJ_DIR)/$(PROJECT_NAME).bin
ADD_OPT = -w 0x2F00 -f ota_upboot.add
else
LDSCRIPT ?= $(SDK_PATH)/misc/phy6222.ld
DEFINES += -DOTA_TYPE=OTA_TYPE_NONE
BIN_OTA = $(OBJ_DIR)/$(PROJECT_NAME).bin
ADD_OPT =
endif
LDFLAGS := $(ARCH_FLAGS)
@ -279,7 +281,7 @@ all: directory $(SRC_O) $(OBJ_DIR)/$(PROJECT_NAME).elf $(OBJ_DIR)/$(PROJECT_NAME
%.bin: %.hex
@echo Make: $@
@$(PYTHON) ./phy62x2_ota.py $(OBJ_DIR)/$(PROJECT_NAME).hex
@$(PYTHON) ./phy62x2_ota.py $(ADD_OPT) $(OBJ_DIR)/$(PROJECT_NAME).hex
%.asm: %.elf
@echo OBJDUMP: $@
@ -301,7 +303,7 @@ flash:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex
flash_ota:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r we 0x10000 $(OBJ_DIR)/$(PROJECT_NAME).bin
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r we 0x10000 $(BIN_OTA)
erase_and_flash:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -e -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex

23
bthome_phy6222/SDK/components/driver/flash/flash.c
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@ -49,6 +49,29 @@ static xflash_Ctx_t s_xflashCtx = {
.spif_ref_clk = SYS_CLK_DLL_64M,
.rd_instr = XFRD_FCMD_READ_DUAL };
/*
void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy)
{
uint32_t temp = op << 0x18;
if (addrlen != 0) {
temp = temp | 0x80000 | addrlen * 0x10000 - 0x10000;
}
if (rdlen != 0) {
temp = temp | 0x800000 | rdlen * 0x100000 - 0x100000;
}
if (wrlen != 0) {
temp = temp | 0x8000 | wrlen * 0x1000 - 0x1000;
}
if (mbit != 0) {
temp = temp | 0x40000;
}
if (dummy != 0) {
temp = temp | dummy << 7;
}
AP_SPIF->fcmd = temp | 1;
...
}
*/
__ATTR_SECTION_SRAM__ static inline uint32_t spif_lock() {
HAL_ENTER_CRITICAL_SECTION();

13
bthome_phy6222/SDK/misc/ota_app_phy62x2.ld
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@ -46,18 +46,7 @@ SECTIONS
*.o(_section_standby_code_)
*.o(_section_sram_code_)
*patch.o(.text.*)
*patch_ext_adv.o(.text.*)
*rf_phy_driver.o(.text.*)
*pwrmgr.o(.text .text.*)
*timer.o(.text .text.*)
*flash.o(.text .text.*)
*clock.o(.text.*)
*phy_sec_ext.o(.text .text.*)
*main.o(.text.*)
*libgcc.a:*.o(.text .text.*)
_etextram = ABSOLUTE(.);

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bthome_phy6222/bin/BTH01_v14.bin
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bthome_phy6222/bin/TH05D_v14.bin
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bthome_phy6222/bin/TH05F_v14.bin
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bthome_phy6222/bin/TH05_v14.bin
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bthome_phy6222/bin/THB1_v14.bin
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bthome_phy6222/bin/THB2_v14.bin
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7
bthome_phy6222/mk_windows.cmd
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@ -3,6 +3,7 @@
@del /Q "build\THB2%SWVER%.hex"
@del /Q "build\THB2%SWVER%.bin"
@mkdir .\bin
@mkdir .\boot
@make -s clean
@make -s -j PROJECT_NAME=THB2%SWVER% POJECT_DEF="-DDEVICE=DEVICE_THB2"
@if not exist "build\THB2%SWVER%.hex" goto :error
@ -48,36 +49,42 @@
@make -s -j PROJECT_NAME=BOOT_THB2%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_THB2"
@if not exist "build\BOOT_THB2%SWVER%.hex" goto :error
@copy "build\BOOT_THB2%SWVER%.hex" .\bin
@copy "build\BOOT_THB2%SWVER%.bin" .\boot
@
@del /Q "build\BOOT_BTH01%SWVER%.hex"
@make -s clean
@make -s -j PROJECT_NAME=BOOT_BTH01%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_BTH01"
@if not exist "build\BOOT_BTH01%SWVER%.hex" goto :error
@copy "build\BOOT_BTH01%SWVER%.hex" .\bin
@copy "build\BOOT_BTH01%SWVER%.bin" .\boot
@
@del /Q "build\BOOT_TH05%SWVER%.hex"
@make -s clean
@make -s -j PROJECT_NAME=BOOT_TH05%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_TH05"
@if not exist "build\BOOT_TH05%SWVER%.hex" goto :error
@copy "build\BOOT_TH05%SWVER%.hex" .\bin
@copy "build\BOOT_TH05%SWVER%.bin" .\boot
@
@del /Q "build\BOOT_TH05D%SWVER%.hex"
@make -s clean
@make -s -j PROJECT_NAME=BOOT_TH05D%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_TH05D"
@if not exist "build\BOOT_TH05D%SWVER%.hex" goto :error
@copy "build\BOOT_TH05D%SWVER%.hex" .\bin
@copy "build\BOOT_TH05D%SWVER%.bin" .\boot
@
@del /Q "build\BOOT_TH05F%SWVER%.hex"
@make -s clean
@make -s -j PROJECT_NAME=BOOT_TH05F%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_TH05F"
@if not exist "build\BOOT_TH05F%SWVER%.hex" goto :error
@copy "build\BOOT_TH05F%SWVER%.hex" .\bin
@copy "build\BOOT_TH05F%SWVER%.bin" .\boot
@
@del /Q "build\BOOT_THB1%SWVER%.hex"
@make -s clean
@make -s -j PROJECT_NAME=BOOT_THB1%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_THB1"
@if not exist "build\BOOT_THB1%SWVER%.hex" goto :error
@copy "build\BOOT_THB1%SWVER%.hex" .\bin
@copy "build\BOOT_THB1%SWVER%.bin" .\boot
@exit
:error
@echo "Error!"

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bthome_phy6222/ota_upboot.add Normal file
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47
bthome_phy6222/phy62x2_ota.py
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@ -23,7 +23,7 @@ PHY_WR_BLK_SIZE = 0x2000
__progname__ = 'PHY62x2 OTA Utility'
__filename__ = 'phy62x2_ota.py'
__version__ = "23.01.24"
__version__ = "25.02.24"
def do_crc(s, c):
return zlib.crc32(s, c) & 0xffffffff
@ -84,10 +84,11 @@ class phy_ota:
size = 0x100
sections = 15
wfaddr = (wrfaddr & (MAX_FLASH_SIZE-1)) + size
wrfaddr = wfaddr;
faddr_min = MAX_FLASH_SIZE-1 # xip addr min
faddr_max = 0 # xip addr max
rsize = 0 # size ram data
hexf = bytearray(struct.pack('<IIII', otaid, len(hp), start, 0xffffffff))
hexf = bytearray(struct.pack('<IIII', otaid, len(hp)-1, start, 0xffffffff))
for ihp in hp:
if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM
rsize += len(ihp[1])
@ -154,6 +155,7 @@ def main():
parser.add_argument('--idota', '-i', help = 'Flag ID OTA (default: 0x%08x)' % START_UP_FLAG, type = arg_auto_int, default = START_UP_FLAG);
parser.add_argument('--runaddr', '-r', help = 'Application run-start address (default: 0x%08x)' % DEF_START_RUN_APP_ADDR, type = arg_auto_int, default = DEF_START_RUN_APP_ADDR);
parser.add_argument('--wraddr', '-w', help = 'Application write address (default: 0x%08x)' % DEF_START_WR_FLASH_ADDR, type = arg_auto_int, default = DEF_START_WR_FLASH_ADDR);
parser.add_argument('--fbup', '-f', help = 'Boot update file (default: none)', default = None);
parser.add_argument('--outfile', '-o', help = 'Output bin file')
parser.add_argument('filename', help = 'Name of hex file')
@ -162,15 +164,36 @@ def main():
print('=========================================================')
print('%s version %s' % (__progname__, __version__))
print('---------------------------------------------------------')
if args.fbup != None:
try:
fbup = open(args.fbup, 'rb')
except Exception as e:
print('Error: Open file %s, %s' % (args.fbup, e))
exit(1)
try:
datafbup = fbup.read();
except Exception as e:
print('Error: Read file %s,: %s' % (args.fbup, e))
exit(1)
fbup.close()
fbupid = int.from_bytes(datafbup[0:4], byteorder='little')
fbuplen = int.from_bytes(datafbup[12:16], byteorder='little')
print("Boot update file id: %08x:%08x" %(fbupid, fbuplen))
if (fbupid != START_UP_FLAG) or ((fbuplen + 4) != len(datafbup)) or (fbuplen > 4096) or (fbuplen <= 256):
print('Error: Boot update file %s format!' % args.fbup)
exit(2)
datafbup = bytearray(datafbup[0:-4])
phy = phy_ota()
hp = phy.ParseHexFile(args.filename, args.wraddr)
if hp == None:
sys.exit(2)
sys.exit(3)
hexf = phy.HexfHeader(hp, args.runaddr, args.wraddr, args.idota)
if hexf == None:
sys.exit(2)
sys.exit(4)
hp[0][1] = hexf
print ('---- File Structure -------------------------------------')
@ -182,15 +205,19 @@ def main():
fout = open(outfile, 'wb')
except:
print('No file opened', outfile)
sys.exit(3)
sys.exit(5)
fsize = 0
for ihp in hp:
fsize += len(ihp[1])
fillsize = 16 - fsize % 16
fsize += fillsize
segment = 0
crc = 0
try:
if args.fbup != None:
#print('size: %08x , %08x' % (fsize, fbuplen))
datafbup[12:16] = int.to_bytes(fsize + fbuplen, 4, byteorder='little')
datafbup[0xfc:0x100] = int.to_bytes((fbuplen + DEF_START_WR_FLASH_ADDR) | 0x11000000, 4, byteorder='little')
crc = do_crc(datafbup, crc)
fout.write(datafbup)
for ihp in hp:
if ihp[0] == 0:
print('Segment Table[%02d] <- Flash addr: %08x, Size: %08x' % (len(hp) - 1, ihp[2], len(ihp[1])))
@ -204,9 +231,9 @@ def main():
fout.write(bytearray(struct.pack('<I', crc)))
size = fout.tell()
fout.close()
except:
print('No write file', outfile)
sys.exit(3)
except Exception as e:
print('No write file %s, %s' % (outfile, e))
sys.exit(6)
print ('---------------------------------------------------------')
print ('Write to file: %s %u bytes - ok.' % (outfile, size))
sys.exit(0)

4
bthome_phy6222/rdwr_phy62x2.py
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@ -459,7 +459,7 @@ class phyflasher:
def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, raddr = DEF_START_WR_FLASH_ADDR):
if len(hp) > 1:
hexf = bytearray(b'\xff')*(0x100)
hexf[0:4] = int.to_bytes(len(hp), 4, byteorder='little')
hexf[0:4] = int.to_bytes(len(hp)-1, 4, byteorder='little')
hexf[8:12] = int.to_bytes(start, 4, byteorder='little')
#sections = 0
faddr_min = MAX_FLASH_SIZE-1
@ -592,8 +592,6 @@ def main():
print ('Error Flash read Unique ID!')
sys.exit(3)
print ('Flash Serial Number:', rb.hex()) # Unique ID
exit(0)
if args.operation == 'rc':
#filename = "r%08x-%08x.bin" % (addr, length)
if args.size == 0:

43
ota_boot/.autotools Normal file
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@ -0,0 +1,43 @@
<?xml version="1.0" encoding="UTF-8"?>
<configurations>
<configuration id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871">
<option id="configure" value="configure"/>
<option id="configdir" value=""/>
<option id="cache-file" value=""/>
<option id="help" value="false"/>
<option id="no-create" value="false"/>
<option id="quiet" value="false"/>
<option id="version" value="false"/>
<option id="host" value=""/>
<option id="build" value=""/>
<option id="target" value=""/>
<option id="prefix" value=""/>
<option id="exec-prefix" value=""/>
<option id="libdir" value=""/>
<option id="bindir" value=""/>
<option id="sbindir" value=""/>
<option id="includedir" value=""/>
<option id="datadir" value=""/>
<option id="sysconfdir" value=""/>
<option id="infodir" value=""/>
<option id="mandir" value=""/>
<option id="srcdir" value=""/>
<option id="localstatedir" value=""/>
<option id="sharedstatedir" value=""/>
<option id="libexecdir" value=""/>
<option id="oldincludedir" value=""/>
<option id="program-prefix" value=""/>
<option id="program-suffix" value=""/>
<option id="program-transform-name" value=""/>
<option id="env_vars" value=""/>
<option id="enable-maintainer-mode" value="false"/>
<flag id="CFLAGS" value="CFLAGS|CXXFLAGS">
<flagvalue id="cflags-debug" value="false"/>
<flagvalue id="cflags-gprof" value="false"/>
<flagvalue id="cflags-gcov" value="false"/>
</flag>
<option id="user" value=""/>
<option id="autogen" value="autogen.sh"/>
<option id="autogenOpts" value=""/>
</configuration>
</configurations>

346
ota_boot/.cproject Normal file
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@ -0,0 +1,346 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871" moduleId="org.eclipse.cdt.core.settings" name="Default">
<externalSettings/>
<extensions>
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration artifactName="${ProjName}" buildProperties="" description="" id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871" name="Default" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.dockerdpath=,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="org.eclipse.cdt.build.core.emptycfg">
<folderInfo id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871.266191087" name="/" resourcePath="">
<toolChain id="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.321694806" name="Arm Cross GCC" superClass="ilg.gnuarmeclipse.managedbuild.cross.toolchain.base">
<option id="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.2086137351" name="Architecture" superClass="ilg.gnuarmeclipse.managedbuild.cross.option.architecture" value="ilg.gnuarmeclipse.managedbuild.cross.option.architecture.arm" valueType="enumerated"/>
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7
ota_boot/.gitignore vendored Normal file
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@ -0,0 +1,7 @@
bin
Listings
Objects
TestTHB2.asm
TestTHB2.uvguix.*
TestTHB2.uvoptx
build

34
ota_boot/.project Normal file
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@ -0,0 +1,34 @@
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ota_boot</name>
<comment></comment>
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<nature>org.eclipse.cdt.core.ccnature</nature>
<nature>org.python.pydev.pythonNature</nature>
</natures>
</projectDescription>

5
ota_boot/.pydevproject Normal file
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@ -0,0 +1,5 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?eclipse-pydev version="1.0"?><pydev_project>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property>
<pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python interpreter</pydev_property>
</pydev_project>

15
ota_boot/.settings/language.settings.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project>
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109
ota_boot/.settings/org.eclipse.cdt.codan.core.prefs Normal file
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@ -0,0 +1,109 @@
eclipse.preferences.version=1
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org.eclipse.cdt.codan.internal.checkers.CopyrightProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Lack of copyright information\\")",regex\=>".*Copyright.*"}
org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem=Error
org.eclipse.cdt.codan.internal.checkers.DecltypeAutoProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid 'decltype(auto)' specifier\\")"}
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.FieldResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Field cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.FloatCompareProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Direct float comparison\\")"}
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.FunctionResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Function cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.GotoStatementProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Goto statement used\\")"}
org.eclipse.cdt.codan.internal.checkers.InvalidArguments=Error
org.eclipse.cdt.codan.internal.checkers.InvalidArguments.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid arguments\\")"}
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem=Error
org.eclipse.cdt.codan.internal.checkers.InvalidTemplateArgumentsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid template argument\\")"}
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem=Error
org.eclipse.cdt.codan.internal.checkers.LabelStatementNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Label statement not found\\")"}
org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MagicNumberProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Avoid magic numbers\\")",checkArray\=>true,checkOperatorParen\=>true,exceptions\=>(1,0,-1,2,1.0,0.0,-1.0)}
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem=Error
org.eclipse.cdt.codan.internal.checkers.MemberDeclarationNotFoundProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Member declaration not found\\")"}
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.MethodResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Method cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.MissCaseProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissCaseProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing cases in switch\\")"}
org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissDefaultProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing default in switch\\")",defaultWithAllEnums\=>false}
org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"}
org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"}
org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Multiple variable declaration\\")"}
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker=-Info
org.eclipse.cdt.codan.internal.checkers.NamingConventionFunctionChecker.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Name convention for function\\")",pattern\=>"^[a-z]",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem=Warning
org.eclipse.cdt.codan.internal.checkers.NoDiscardProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return value not evaluated\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem=Warning
org.eclipse.cdt.codan.internal.checkers.NonVirtualDestructorProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Class has a virtual method and non-virtual destructor\\")"}
org.eclipse.cdt.codan.internal.checkers.OverloadProblem=Error
org.eclipse.cdt.codan.internal.checkers.OverloadProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid overload\\")"}
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem=Error
org.eclipse.cdt.codan.internal.checkers.RedeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redeclaration\\")"}
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem=Error
org.eclipse.cdt.codan.internal.checkers.RedefinitionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Invalid redefinition\\")"}
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"}
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"}
org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Miss copy constructor or assignment operator\\")",onlynew\=>false}
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem=Warning
org.eclipse.cdt.codan.internal.checkers.StatementHasNoEffectProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Statement has no effect\\")",macro\=>true,exceptions\=>()}
org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.StaticVariableInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Static variable in header file\\")"}
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem=Warning
org.eclipse.cdt.codan.internal.checkers.SuggestedParenthesisProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suggested parenthesis around expression\\")",paramNot\=>false}
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem=Warning
org.eclipse.cdt.codan.internal.checkers.SuspiciousSemicolonProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Suspicious semicolon\\")",else\=>false,afterelse\=>false}
org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.SymbolShadowingProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol shadowing\\")",paramFuncParameters\=>true}
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.TypeResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Type cannot be resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true}
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning
org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")}
org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning
org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"}
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error
org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"}
org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error
org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"}

6
ota_boot/.settings/org.eclipse.cdt.core.prefs Normal file
View file

@ -0,0 +1,6 @@
doxygen/doxygen_new_line_after_brief=true
doxygen/doxygen_use_brief_tag=false
doxygen/doxygen_use_javadoc_tags=true
doxygen/doxygen_use_pre_tag=false
doxygen/doxygen_use_structural_commands=false
eclipse.preferences.version=1

13
ota_boot/.settings/org.eclipse.cdt.managedbuilder.core.prefs Normal file
View file

@ -0,0 +1,13 @@
eclipse.preferences.version=1
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPATH/delimiter=;
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPATH/operation=remove
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPLUS_INCLUDE_PATH/delimiter=;
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPLUS_INCLUDE_PATH/operation=remove
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/C_INCLUDE_PATH/delimiter=;
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/C_INCLUDE_PATH/operation=remove
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/append=true
environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/appendContributed=true
environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/LIBRARY_PATH/delimiter=;
environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/LIBRARY_PATH/operation=remove
environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/append=true
environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/appendContributed=true

2
ota_boot/.settings/org.eclipse.core.resources.prefs Normal file
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@ -0,0 +1,2 @@
eclipse.preferences.version=1
encoding/<project>=UTF-8

2
ota_boot/.settings/org.eclipse.embedcdt.managedbuild.cross.arm.core.prefs Normal file
View file

@ -0,0 +1,2 @@
eclipse.preferences.version=1
toolchain.path.1287942917=D\:\\MCU\\GNU_Tools_ARM_Embedded\\13.2.rel1\\bin

138
ota_boot/Makefile Normal file
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@ -0,0 +1,138 @@
##############################################################################
PROJECT_NAME ?= ota_upboot
#POJECT_DEF ?= -DDEVICE=DEVICE_THB2
##############################################################################
COM_PORT = COM11
##############################################################################
# Source
SRC_PATH = ./source
SRC_PRJ = main.c
INCLUDES = -I$(SRC_PATH)
INCLUDES += -I$(SRC_PATH)/include
INCLUDES += -I$(SRC_PATH)/misc
INCLUDES += -I$(SRC_PATH)/misc/CMSIS/include
INCLUDES += -I$(SRC_PATH)/misc/CMSIS/device/phyplus
STARTUP_ASM = $(SRC_PATH)/misc/CMSIS/device/phyplus/phy6222_start.s
SRCS = $(addprefix $(SRC_PATH)/, $(SRC_PRJ))
SRCS += $(SRC_PATH)/misc/CMSIS/device/phyplus/phy6222_vectors.c
##############################################################################
DEFINES += -D__GCC
DEFINES += $(POJECT_DEF)
DEFINES += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
##############################################################################
BIN_DIR = ./bin
OBJ_DIR = ./build
PYTHON = python3
GCC_PATH =
CC = $(GCC_PATH)arm-none-eabi-gcc
OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy
OBJDUMP = $(GCC_PATH)arm-none-eabi-objdump
SIZE = $(GCC_PATH)arm-none-eabi-size
READELF = $(GCC_PATH)arm-none-eabi-readelf
##############################################################################
ARCH_FLAGS := -mcpu=cortex-m0 -mthumb -mthumb-interwork
OPT_CFLAGS ?= -Os
DEB_CFLAGS ?= -g3 -ggdb
##############################################################################
ASFLAGS := $(ARCH_FLAGS) $(OPT_CFLAGS) $(DEB_CFLAGS)
CFLAGS := $(ARCH_FLAGS) $(OPT_CFLAGS) $(DEB_CFLAGS)
CFLAGS += -W -Wall --std=gnu99
CFLAGS += -fno-diagnostics-show-caret
CFLAGS += -fdata-sections -ffunction-sections
CFLAGS += -funsigned-char -funsigned-bitfields
#CFLAGS += -fpack-struct
#CFLAGS += -mno-unaligned-access
#CFLAGS += -munaligned-access
CFLAGS += -fms-extensions
CFLAGS += -specs=nosys.specs
CFLAGS += -Wl,--gc-sections
LDSCRIPT ?= $(SRC_PATH)/misc/ota_upboot.ld
#BIN_OTA = $(OBJ_DIR)/$(PROJECT_NAME).bin
BIN_OTA = ./$(PROJECT_NAME).add
LDFLAGS := $(ARCH_FLAGS)
LDFLAGS += --static -nostartfiles -nostdlib
LDFLAGS += -Wl,--gc-sections
LDFLAGS += -Wl,--script=$(LDSCRIPT)
LDFLAGS += -Wl,--just-symbols=$(SRC_PATH)/misc/bb_rom_sym_m0.gcc
LDFLAGS += -Wl,-Map=$(OBJ_DIR)/$(PROJECT_NAME).map
LIBS += -Wl,--start-group -lgcc -lnosys -Wl,--end-group
##############################################################################
CFLAGS += $(DEFINES) $(INCLUDES)
#SRC_O = $(patsubst %.c,%.o,$(patsubst sdk/%, $(SRC_PATH)%, $(SRCS)))
SRC_O = $(SRCS:%.c=%.o) $(STARTUP_ASM:%.s=%.o)
OBJS = $(patsubst %, $(OBJ_DIR)/%, $(patsubst ./%, %, $(SRC_O)))
DEPENDENCY_LIST = $(OBJS:%o=%d)
##############################################################################
.PHONY: all directory clean size flash erase_and_flash
all: directory $(SRC_O) $(OBJ_DIR)/$(PROJECT_NAME).elf $(OBJ_DIR)/$(PROJECT_NAME).hex $(BIN_OTA) $(OBJ_DIR)/$(PROJECT_NAME).asm size
%.elf %.map: $(SRC_O) $(LDSCRIPT) Makefile
@echo LD: $@
@$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o $@
%.hex: %.elf
@echo OBJCOPY: $@
@$(OBJCOPY) -O ihex $^ $@
%.add: %.hex
@echo Make: $@
$(PYTHON) ./phy62x2_ota.py -o $(BIN_OTA) $(OBJ_DIR)/$(PROJECT_NAME).hex
%.asm: %.elf
@echo OBJDUMP: $@
@$(OBJDUMP) -s -S $^ >$@
%.o : %.c
@echo CC: $<
@mkdir -p $(OBJ_DIR)/$(dir $@)
@$(CC) $(CFLAGS) $(INCFLAGS) -c $< -o $(OBJ_DIR)/$@
@$(CC) -MM $(CFLAGS) $(INCFLAGS) $< -MT $@ -MF $(OBJ_DIR)/$(patsubst %.o,%.d,$@)
%.o : %.s
@echo CC: $<
@mkdir -p $(OBJ_DIR)/$(dir $@)
@$(CC) $(CFLAGS) $(INCFLAGS) -c $< -o $(OBJ_DIR)/$@
@$(CC) -MM $(CFLAGS) $(INCFLAGS) $< -MT $@ -MF $(OBJ_DIR)/$(patsubst %.o,%.d,$@)
flash:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex
flash_ota:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r we 0x10000 $(BIN_OTA)
erase_and_flash:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -e -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex
reset:
@$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -r i
directory:
@mkdir -p $(OBJ_DIR)
size: $(OBJ_DIR)/$(PROJECT_NAME).elf
@echo size:
@$(SIZE) -t $^
@$(READELF) -l $^
@echo
clean:
@echo clean
@-rm -rf $(OBJ_DIR)
-include $(DEPENDENCY_LIST)
VPATH:=$(OBJ_DIR)

BIN
ota_boot/ota_upboot.add Normal file
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242
ota_boot/phy62x2_ota.py Normal file
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@ -0,0 +1,242 @@
#!/usr/bin/env python3
# phy62x2_ota.py 22.01.2024 pvvx #
import argparse
import io
import os
import struct
import sys
import zlib
START_UP_FLAG = 0x36594850 #"PHY6"
MAX_FLASH_SIZE = 0x200000
EXT_FLASH_ADD = 0x400000
DEF_START_RUN_APP_ADDR = 0x1FFF1838
DEF_START_WR_FLASH_ADDR = 0x010000
PHY_FLASH_SECTOR_SIZE = 4096
PHY_FLASH_SECTOR_MASK = 0xfffff000
PHY_WR_BLK_SIZE = 0x2000
__progname__ = 'PHY62x2 OTA Utility'
__filename__ = 'phy62x2_ota.py'
__version__ = "25.02.24"
def do_crc(s, c):
return zlib.crc32(s, c) & 0xffffffff
class phy_ota:
def ParseHexFile(self, hexfile, faddr = DEF_START_WR_FLASH_ADDR):
try:
fin = open(hexfile)
except:
print('No file opened', hexfile)
return None
table = []
result = bytearray()
addr = 0
naddr = 0
taddr = 0
addr_flg = 0
table.append([0, result, faddr])
for hexstr in fin.readlines():
hexstr = hexstr.strip()
if hexstr[7:9] == '04':
if(len(result)):
#print(hex(addr))
table.append([addr, result, 0])
addr = int(hexstr[9:13],16) << 16
addr_flg = 0
result = bytearray()
continue
if hexstr[7:9] == '05' or hexstr[7:9] == '01':
table.append([addr, result, 0])
break
taddr = (int(hexstr[3:7],16))
if addr_flg == 0:
addr_flg = 1
addr = addr | taddr
naddr = taddr
if taddr != naddr:
addr_flg = 1
table.append([addr, result, 0])
addr = (addr & 0xFFFF0000) | taddr
result = bytearray()
#print(hexstr[9:-3])
result.extend(bytearray.fromhex(hexstr[9:-2]))
naddr = taddr + int(hexstr[1:3],16)
fin.close()
return table
def WriteHexf(self, sn, ph):
offset = ph[2]
offset &= 0x00ffffff
idx = 0
size = len(ph[1])
return True
def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, wrfaddr = DEF_START_WR_FLASH_ADDR, otaid = START_UP_FLAG):
if len(hp) > 1:
if len(hp) > 15:
print('Maximum number of segments = 15!')
return None
size = 0x100
sections = 15
wfaddr = (wrfaddr & (MAX_FLASH_SIZE-1)) + size
wrfaddr = wfaddr;
faddr_min = MAX_FLASH_SIZE-1 # xip addr min
faddr_max = 0 # xip addr max
rsize = 0 # size ram data
hexf = bytearray(struct.pack('<IIII', otaid, len(hp)-1, start, 0xffffffff))
for ihp in hp:
if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM
rsize += len(ihp[1])
elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash (XIP)
offset = ihp[0] & (MAX_FLASH_SIZE-1)
if faddr_min > offset:
faddr_min = offset
send = offset + len(ihp[1])
if faddr_max <= send:
faddr_max = send
if (wrfaddr + rsize) >= faddr_min:
wrfaddr = (faddr_max + 3) & 0xfffffffc # start wr faddr ram data
#print('Test: Flash addr min: %08x, max: %08x, RAM addr: %08x' % (faddr_min, faddr_max, wrfaddr))
print ('---- Segments Table -------------------------------------')
for ihp in hp:
if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM
faddr = wrfaddr # wr faddr ram data
wrfaddr += (len(ihp[1])+3) & 0xfffffffc # next wr faddr ram data
elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash
faddr = ihp[0] & (MAX_FLASH_SIZE-1)
if wfaddr != faddr:
print('Error: The segment Flash addr: 0x%08x, Size: 0x%08x does not match the markup (0x%08x)!' % (ihp[0], len(ihp[1]), wfaddr))
return None
elif ihp[0] == 0:
continue
else:
print('Error: Invalid Segment Address 0x%08x!' % ihp[0])
return None
ihp[2] = faddr
sections -= 1
print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], faddr, len(ihp[1])))
crc = 0xffffffff - do_crc(ihp[1], 0)
hexf.extend(bytearray(struct.pack('<IIII', faddr, len(ihp[1]), ihp[0], crc)))
fill = len(ihp[1]) % 4
if fill != 0:
ihp[1].extend(bytearray(b'\xff')*(4 - fill))
size += len(ihp[1])
wfaddr += len(ihp[1])
if sections > 0:
hexf.extend(bytearray(b'\xff')*(0x10*sections))
fill = size % 16
if fill != 0:
hp[len(hp)-1][1].extend(bytearray(b'\xff')*(16 - fill))
size += 16 - fill
hexf[12:16] = int.to_bytes(size, 4, byteorder='little')
return hexf
return None
class FatalError(RuntimeError):
def __init__(self, message):
RuntimeError.__init__(self, message)
@staticmethod
def WithResult(message, result):
message += " (result was %s)" % hexify(result)
return FatalError(message)
def arg_auto_int(x):
return int(x, 0)
def main():
parser = argparse.ArgumentParser(description='%s version %s' % (__progname__, __version__), prog = __filename__)
parser.add_argument('--idota', '-i', help = 'Flag ID OTA (default: 0x%08x)' % START_UP_FLAG, type = arg_auto_int, default = START_UP_FLAG);
parser.add_argument('--runaddr', '-r', help = 'Application run-start address (default: 0x%08x)' % DEF_START_RUN_APP_ADDR, type = arg_auto_int, default = DEF_START_RUN_APP_ADDR);
parser.add_argument('--wraddr', '-w', help = 'Application write address (default: 0x%08x)' % DEF_START_WR_FLASH_ADDR, type = arg_auto_int, default = DEF_START_WR_FLASH_ADDR);
parser.add_argument('--fbup', '-f', help = 'Boot update file (default: none)', default = None);
parser.add_argument('--outfile', '-o', help = 'Output bin file')
parser.add_argument('filename', help = 'Name of hex file')
args = parser.parse_args()
print('=========================================================')
print('%s version %s' % (__progname__, __version__))
print('---------------------------------------------------------')
if args.fbup != None:
try:
fbup = open(args.fbup, 'rb')
except Exception as e:
print('Error: Open file %s, %s' % (args.fbup, e))
exit(1)
try:
datafbup = fbup.read();
except Exception as e:
print('Error: Read file %s,: %s' % (args.fbup, e))
exit(1)
fbup.close()
fbupid = int.from_bytes(datafbup[0:4], byteorder='little')
fbuplen = int.from_bytes(datafbup[12:16], byteorder='little')
print("Boot update file id: %08x:%08x" %(fbupid, fbuplen))
if (fbupid != START_UP_FLAG) or ((fbuplen + 4) != len(datafbup)) or (fbuplen > 4096) or (fbuplen <= 256):
print('Error: Boot update file %s format!' % args.fbup)
exit(2)
datafbup = bytearray(datafbup[0:-4])
phy = phy_ota()
hp = phy.ParseHexFile(args.filename, args.wraddr)
if hp == None:
sys.exit(3)
hexf = phy.HexfHeader(hp, args.runaddr, args.wraddr, args.idota)
if hexf == None:
sys.exit(4)
hp[0][1] = hexf
print ('---- File Structure -------------------------------------')
(outfile, ext) = os.path.splitext(args.filename)
outfile += '.bin'
if args.outfile != None:
outfile = args.outfile
try:
fout = open(outfile, 'wb')
except:
print('No file opened', outfile)
sys.exit(5)
fsize = 0
for ihp in hp:
fsize += len(ihp[1])
segment = 0
crc = 0
try:
if args.fbup != None:
#print('size: %08x , %08x' % (fsize, fbuplen))
datafbup[12:16] = int.to_bytes(fsize + fbuplen, 4, byteorder='little')
datafbup[0xfc:0x100] = int.to_bytes((fbuplen + DEF_START_WR_FLASH_ADDR) | 0x11000000, 4, byteorder='little')
crc = do_crc(datafbup, crc)
fout.write(datafbup)
for ihp in hp:
if ihp[0] == 0:
print('Segment Table[%02d] <- Flash addr: %08x, Size: %08x' % (len(hp) - 1, ihp[2], len(ihp[1])))
else:
print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], ihp[2], len(ihp[1])))
fout.write(ihp[1])
crc = do_crc(ihp[1], crc)
segment += 1
crc = 0xffffffff - crc
#print('CRC32: %04x' % crc)
fout.write(bytearray(struct.pack('<I', crc)))
size = fout.tell()
fout.close()
except Exception as e:
print('No write file %s, %s' % (outfile, e))
sys.exit(6)
print ('---------------------------------------------------------')
print ('Write to file: %s %u bytes - ok.' % (outfile, size))
sys.exit(0)
if __name__ == '__main__':
main()

738
ota_boot/rdwr_phy62x2.py Normal file
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@ -0,0 +1,738 @@
#!/usr/bin/env python3
# rdwr_phy62x2.py 11.01.2024 pvvx #
import serial;
import time;
import argparse
import io
import os
import struct
import sys
START_BAUD = 9600
DEF_RUN_BAUD = 115200
MAX_FLASH_SIZE = 0x200000
EXT_FLASH_ADD = 0x400000
DEF_START_RUN_APP_ADDR = 0x1FFF1838
DEF_START_WR_FLASH_ADDR = 0x05000
PHY_FLASH_SECTOR_SIZE = 4096
PHY_FLASH_SECTOR_MASK = 0xfffff000
PHY_WR_BLK_SIZE = 0x2000
__progname__ = 'PHY62x2 Utility'
__filename__ = 'rdwr_phy62x2.py'
__version__ = "24.02.24"
def ParseHexFile(hexfile):
try:
fin = open(hexfile)
except:
print('No file opened', hexfile)
return None
table = []
result = bytearray()
addr = 0
naddr = 0
taddr = 0
addr_flg = 0
table.append([0, result, 0x2000])
for hexstr in fin.readlines():
hexstr = hexstr.strip()
if hexstr[7:9] == '04':
if(len(result)):
#print(hex(addr))
table.append([addr, result, 0])
addr = int(hexstr[9:13],16) << 16
addr_flg = 0
result = bytearray()
continue
if hexstr[7:9] == '05' or hexstr[7:9] == '01':
table.append([addr, result, 0])
break
taddr = (int(hexstr[3:7],16))
if addr_flg == 0:
addr_flg = 1
addr = addr | taddr
naddr = taddr
if taddr != naddr:
addr_flg = 1
table.append([addr, result, 0])
addr = (addr & 0xFFFF0000) | taddr
result = bytearray()
#print(hexstr[9:-3])
result.extend(bytearray.fromhex(hexstr[9:-2]))
naddr = taddr + int(hexstr[1:3],16)
fin.close()
return table
class phyflasher:
def __init__(self, port='COM1'):
self.old_erase_start = EXT_FLASH_ADD
self.old_erase_end = EXT_FLASH_ADD
self.port = port
self.baud = START_BAUD
try:
self._port = serial.Serial(self.port, self.baud)
self._port.timeout = 1
except Exception as e:
print ('Error: Open %s, %d baud! Error: %s' % (self.port, self.baud, e))
sys.exit(1)
def SetAutoErase(self, enable = True):
self.autoerase = enable
def AddSectionToHead(self, addr, size):
#self.hexf.sec[0:4] = int.to_bytes(self.hexidx, 4, byteorder='little')
self.hexf.sec.extend(bytearray(struct.pack('<IIII', phy_head[secn][0], size, addr, 0xffffffff)))
return self.hexf
def write_cmd(self, pkt):
self._port.write(pkt.encode());
read = self._port.read(6);
return read == b'#OK>>:'
def SendResetCmd(self):
return self._port.write(str.encode('reset '));
def read_reg(self, addr):
pkt = 'rdreg%08x' % addr;
sent = self._port.write(pkt.encode());
read = self._port.read(17);
if len(read) == 17 and read[0:3] == b'=0x' and read[11:17] == b'#OK>>:':
return int(read[1:11], 16)
return None
def write_reg(self, addr, data):
return self.write_cmd('wrreg%08x %08x ' % (addr, data))
def ExpFlashSize(self):
if not self.write_reg(0x1fff0898, EXT_FLASH_ADD):
print('Error set ext.Flash size %08x!' % EXT_FLASH_ADD)
return False
return True
def wr_flash_cmd(self, cmd, data = 0, wrlen = 0, addr = 0, addrlen = 0, rdlen = 0, mbit = 0, dummy = 0):
regcmd = cmd << 24
if wrlen > 0:
regcmd = regcmd | 0x8000 | ((wrlen - 1) << 12)
if not self.write_reg(0x4000c8a8, data): #Flash Command Write Data Register
print('Error write Flash Data Register!')
return False
if addrlen > 0:
regcmd = regcmd | 0x80000 | ((addrlen - 1) << 16)
if not self.write_reg(0x4000c894, addr): #Flash Command Write Addr Register
print('Error write Flash Address Register!')
return False
if rdlen > 0:
regcmd = regcmd | 0x800000 | ((rdlen - 1) << 20)
if mbit > 0:
regcmd = regcmd | 0x40000
if dummy > 0:
regcmd = regcmd | (dummy << 7);
if not self.write_reg(0x4000c890, regcmd | 1):
print('Error write Flash Command Register!')
return False
return True
def flash_wait_idle(self):
i = 5;
while i > 0:
r = self.read_reg(0x4000c890)
if r == None:
return False
if (r & 2) == 0:
i = 5
while i > 0:
r = self.read_reg(0x4000c800)
if r == None:
return False
if (r & 0x80000000) != 0:
return True
i -= 1
return False
i -= 1
return False
def flash_read_unique_id(self):
if self.wr_flash_cmd(0x4B,0,0,0,4,8): # and self.flash_wait_idle():
r1 = self.read_reg(0x4000c8a0)
if r1 == None:
return None
r2 = self.read_reg(0x4000c8a4)
if r2 == None:
return None
ret = bytearray(8)
ret[0] = r1 & 0xff
ret[1] = (r1 >> 8) & 0xff
ret[2] = (r1 >> 16) & 0xff
ret[3] = (r1 >> 24) & 0xff
ret[4] = r2 & 0xff
ret[5] = (r2 >> 8) & 0xff
ret[6] = (r2 >> 16) & 0xff
ret[7] = (r2 >> 24) & 0xff
return ret
return None
def flash_read_status(self):
#Flash cmd: Read status
if self.wr_flash_cmd(5,0,0,0,0,1): # and self.flash_wait_idle():
r = self.read_reg(0x4000c8a0)
if r == None:
return None
return r & 0x0ff
return None
def FlashUnlock(self):
#Flash cmd: Write Enable, Write Status Register 0x00
return self.wr_flash_cmd(6) and self.wr_flash_cmd(1, 0, 1)
def ReadRevision(self):
#0x001364c8 6222M005 #OK>>:
self._port.write(str.encode('rdrev+ '));
self._port.timeout = 0.1
read = self._port.read(26);
if len(read) == 26 and read[0:2] == b'0x' and read[20:26] == b'#OK>>:':
print('Revision:', read[2:19])
if read[11:15] != b'6222':
print('Wrong Version!')
self.flash_id = int(read[2:11], 16)
self.flash_size = 1 << ((self.flash_id >> 16) & 0xff)
print('FlashID: %06x, size: %d kbytes' % (self.flash_id, self.flash_size >> 10))
return True
else:
print('Error read Revision!')
return False
def SetBaud(self, baud):
if self._port.baudrate != baud:
print ('Reopen %s port %i baud...' % (self.port, baud), end = ' '),
self._port.write(str.encode("uarts%i" % baud));
self._port.timeout = 1
read = self._port.read(3);
if read == b'#OK':
print ('ok')
self._port.close()
self.baud = baud
self._port.baudrate = baud
try:
self._port.open();
except Exception as e:
print ('Error: Open %s, %d baud! Error: %s' % (self.port, self.baud, e))
sys.exit(1)
else:
print ('error!')
print ('Error set %i baud on %s port!' % (baud, self.port))
self._port.close()
sys.exit(3)
return True
def Connect(self, baud=DEF_RUN_BAUD):
self._port.setDTR(True) #TM (lo)
self._port.setRTS(True) #RSTN (lo)
time.sleep(0.1)
self._port.flushOutput()
self._port.flushInput()
time.sleep(0.1)
self._port.setDTR(False) #TM (hi)
self._port.setRTS(False) #RSTN (hi)
self._port.timeout = 0.04
ttcl = 50;
fct_mode = False
pkt = 'UXTDWU' # UXTL16 UDLL48 UXTDWU
while ttcl > 0:
sent = self._port.write(pkt.encode());
read = self._port.read(6);
if read == b'cmd>>:' :
break
if read == b'fct>>:' :
fct_mode = True
break
ttcl = ttcl - 1
if ttcl < 1:
print('PHY62x2 - Error Reset!')
print('Check connection TX->RX, RX<-TX and Chip Power!')
self._port.close()
exit(4)
print('PHY62x2 - Reset Ok')
self._port.close()
self._port.baudrate = DEF_RUN_BAUD
self._port.open();
self._port.timeout = 0.2
if fct_mode:
print('PHY62x2 in FCT mode!')
return False
if not self.ReadRevision():
self._port.close()
exit(4)
if not self.FlashUnlock():
self._port.close()
exit(4)
if not self.write_reg(0x4000f054, 0):
print('PHY62x2 - Error init1!')
self._port.close()
exit(4)
if not self.write_reg(0x4000f140, 0):
print('PHY62x2 - Error init2!')
self._port.close()
exit(4)
if not self.write_reg(0x4000f144, 0):
print('PHY62x2 - Error init3!')
self._port.close()
exit(4)
print('PHY62x2 - connected Ok')
return self.SetBaud(baud)
def cmd_era4k(self, offset):
print ('Erase sector Flash at 0x%08x...' % offset, end = ' ')
tmp = self._port.timeout
self._port.timeout = 0.5
ret = self.write_cmd('era4k %X' % (offset | MAX_FLASH_SIZE))
self._port.timeout = tmp
if not ret:
print ('error!')
else:
print ('ok')
return ret
def cmd_era64k(self, offset):
print ('Erase block 64k Flash at 0x%08x...' % offset, end = ' '),
tmp = self._port.timeout
self._port.timeout = 2
ret = self.write_cmd('er64k %X' % (offset | MAX_FLASH_SIZE))
self._port.timeout = tmp
if not ret:
print ('error!')
else:
print ('ok')
return ret
def cmd_er512(self, offset = 0):
print ('Erase block 512k Flash at 0x%08x...' % offset, end = ' '),
tmp = self._port.timeout
self._port.timeout = 2
ret = self.write_cmd('er512 %X' % (offset | MAX_FLASH_SIZE))
self._port.timeout = tmp
if not ret:
print ('error!')
else:
print ('ok')
return ret
def cmd_erase_work_flash(self):
print ('Erase Flash work area...', end = ' '),
tmp = self._port.timeout
self._port.timeout = 7
ret = self.write_cmd('erall ')
self._port.timeout = tmp
if not ret:
print ('error!')
else:
print ('ok')
return ret
def cmd_erase_all_flash(self):
print ('Erase All Chip Flash...', end = ' '),
if self.wr_flash_cmd(6) and self.wr_flash_cmd(0x60): #Write Enable, Chip Erase
i = 77;
while i > 0:
r = self.flash_read_status()
if r == None:
print ('Error!')
return False
if (r & 1) == 0:
print ('ok')
return True
i -= 1
print ('Timeout!')
return False
def EraseSectorsFlash(self, offset = 0, size = MAX_FLASH_SIZE):
count = int((size + PHY_FLASH_SECTOR_SIZE - 1) / PHY_FLASH_SECTOR_SIZE)
offset &= PHY_FLASH_SECTOR_MASK
if count > 0 and count < 0x10000 and offset >= 0: # 1 byte .. 16 Mbytes
while count > 0:
if offset >= self.old_erase_start and offset < self.old_erase_end:
offset += PHY_FLASH_SECTOR_SIZE
count -= 1
continue
if (offset & 0x0FFFF) == 0 and count > 15:
if not self.cmd_era64k(offset):
return False
self.old_erase_start = offset
self.old_erase_end = offset + 0x10000
offset += 0x10000
count -= 16
else:
if not self.cmd_era4k(offset):
return False
self.old_erase_start = offset
self.old_erase_end = offset + PHY_FLASH_SECTOR_SIZE
offset += PHY_FLASH_SECTOR_SIZE
count -= 1
else:
return False
return True
def EraseSectorsFlash2(self, offset = 0, size = MAX_FLASH_SIZE):
count = int((size + PHY_FLASH_SECTOR_SIZE - 1) / PHY_FLASH_SECTOR_SIZE)
offset &= PHY_FLASH_SECTOR_MASK
if count > 0 and count < 0x10000 and offset >= 0: # 1 byte .. 16 Mbytes
while count > 0:
if (offset & 0x0FFFF) == 0 and count > 15:
if not self.cmd_era64k(offset):
return False
offset += 0x10000
count-=16
else:
if not self.cmd_era4k(offset):
return False
offset += PHY_FLASH_SECTOR_SIZE
count-=1
else:
return False
return True
def send_blk(self, stream, offset, size, blkcnt, blknum):
self._port.timeout = 1
print ('Write 0x%08x bytes to Flash at 0x%08x...' % (size, offset), end = ' '),
if blknum == 0:
if not self.write_cmd('cpnum %d ' % blkcnt):
print ('error!')
return False
self._port.write(str.encode('cpbin c%d %X %X %X' % (blknum, offset | MAX_FLASH_SIZE, size, 0x1FFF0000 + offset)))
read = self._port.read(12)
if read != b'by hex mode:':
print ('error!')
return False
data = stream.read(size)
self._port.write(data)
read = self._port.read(23); #'checksum is: 0x00001d1e'
#print ('%s' % read),
if read[0:15] != b'checksum is: 0x':
print ('error!')
return False
self._port.write(read[15:])
read = self._port.read(6)
if read != b'#OK>>:':
print ('error!')
return False
print ('ok')
return True
def WriteBlockFlash(self, stream, offset = 0, size = 0x8000):
offset &= 0x00ffffff
if self.autoerase:
if not self.EraseSectorsFlash(offset, size):
return False
sblk = PHY_WR_BLK_SIZE
blkcount = (size + sblk - 1) / sblk
blknum = 0
while(size > 0):
if size < sblk:
sblk = size
if not self.send_blk(stream, offset, sblk, blkcount, blknum):
return False
blknum+=1
offset+=sblk
size-=sblk
return True
def ReadBusToFile(self, ff, addr=0x11000000, size=0x80000):
flg = size > 128
if not flg:
print('\rRead 0x%08x...' % addr, end=' ') #, flush=True
while size > 0:
if flg and addr & 127 == 0:
print('\rRead 0x%08x...' % addr, end=' ') #, flush=True
rw = self.read_reg(addr)
if rw == None:
print('error!')
print('\rError read address 0x%08x!' % addr)
return False
dw = struct.pack('<I',rw)
ff.write(dw)
addr += 4
size -= 4
print('ok')
return True
def WriteHexf(self, sn, ph):
offset = ph[2]
offset &= 0x00ffffff
idx = 0
size = len(ph[1])
if self.autoerase:
if not self.EraseSectorsFlash(offset, size):
return False
sblk = PHY_WR_BLK_SIZE
blkcount = (size + sblk - 1) / sblk
blknum = 0
while(size > 0):
if size < sblk:
sblk = size
if not self.send_blk(stream, offset, sblk, blkcount, blknum):
return False
blknum+=1
offset+=sblk
size-=sblk
return True
def HexStartSend(self):
return self.write_cmd('spifs 0 1 3 0 ') and self.write_cmd('sfmod 2 2 ') and self.write_cmd('cpnum ffffffff ')
def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, raddr = DEF_START_WR_FLASH_ADDR):
if len(hp) > 1:
hexf = bytearray(b'\xff')*(0x100)
hexf[0:4] = int.to_bytes(len(hp)-1, 4, byteorder='little')
hexf[8:12] = int.to_bytes(start, 4, byteorder='little')
#sections = 0
faddr_min = MAX_FLASH_SIZE-1
faddr_max = 0
rsize = 0
for ihp in hp:
if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM
rsize += len(ihp[1])
elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash
offset = ihp[0] & (MAX_FLASH_SIZE-1)
if faddr_min > offset:
faddr_min = offset
send = offset + len(ihp[1])
if faddr_max <= send:
faddr_max = send
if (raddr + rsize) >= faddr_min:
raddr = (faddr_max + 3) & 0xfffffffc
#print('Test: Flash addr min: %08x, max: %08x, RAM addr: %08x' % (faddr_min, faddr_max, raddr))
print ('---- Segments Table -------------------------------------')
for ihp in hp:
if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM
faddr = raddr
raddr += (len(ihp[1])+3) & 0xfffffffc
elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash
faddr = ihp[0] & (MAX_FLASH_SIZE-1)
elif ihp[0] == 0:
continue
else:
print('Invalid Segment Address 0x%08x!' % ihp[0])
return None
ihp[2] = faddr
print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], faddr, len(ihp[1])))
hexf.extend(bytearray(struct.pack('<IIII', faddr, len(ihp[1]), ihp[0], 0xffffffff)))
return hexf
return None
class FatalError(RuntimeError):
def __init__(self, message):
RuntimeError.__init__(self, message)
@staticmethod
def WithResult(message, result):
message += " (result was %s)" % hexify(result)
return FatalError(message)
def arg_auto_int(x):
return int(x, 0)
def main():
parser = argparse.ArgumentParser(description='%s version %s' % (__progname__, __version__), prog = __filename__)
parser.add_argument('--port', '-p', help = 'Serial port device', default='COM1');
parser.add_argument('--baud', '-b', help = 'Set Port Baud (115200, 250000, 500000, 1000000)', type = arg_auto_int, default = DEF_RUN_BAUD);
parser.add_argument('--allerase', '-a', action='store_true', help = 'Pre-processing: All Chip Erase');
parser.add_argument('--erase', '-e', action='store_true', help = 'Pre-processing: Erase Flash work area');
parser.add_argument('--reset', '-r', action='store_true', help = 'Post-processing: Reset');
parser.add_argument('--start', '-s', help = 'Application start address for hex writer (default: 0x%08x)' % DEF_START_RUN_APP_ADDR, type = arg_auto_int, default = DEF_START_RUN_APP_ADDR);
parser.add_argument('--write', '-w', help = 'Flash starting address for hex writer (default: 0x%08x)' % DEF_START_WR_FLASH_ADDR, type = arg_auto_int, default = DEF_START_WR_FLASH_ADDR);
subparsers = parser.add_subparsers(
dest='operation',
help = 'Run '+__filename__+' {command} -h for additional help')
parser_hex_flash = subparsers.add_parser(
'wh',
help = 'Write hex file to Flash')
parser_hex_flash.add_argument('filename', help = 'Name of hex file')
parser_burn_flash = subparsers.add_parser(
'we',
help = 'Write bin file to Flash with sectors erases')
parser_burn_flash.add_argument('address', help = 'Start address', type = arg_auto_int)
parser_burn_flash.add_argument('filename', help = 'Name of binary file')
parser_write_flash = subparsers.add_parser(
'wf',
help = 'Write bin file to Flash without sectors erases')
parser_write_flash.add_argument('address', help = 'Start address', type = arg_auto_int)
parser_write_flash.add_argument('filename', help = 'Name of binary file')
parser_erase_sec_flash = subparsers.add_parser(
'er',
help = 'Erase Region (sectors) of Flash')
parser_erase_sec_flash.add_argument('address', help = 'Start address', type = arg_auto_int)
parser_erase_sec_flash.add_argument('size', help = 'Size of region', type = arg_auto_int)
parser_erase_work_flash = subparsers.add_parser(
'ew',
help = 'Erase Flash Work Area')
parser_erase_all_flash = subparsers.add_parser(
'ea',
help = 'Erase All Flash (MAC, ChipID/IV)')
parser_read_chip = subparsers.add_parser(
'rc',
help = 'Read chip bus address to binary file')
parser_read_chip.add_argument('address', help = 'Start address', type = arg_auto_int)
parser_read_chip.add_argument('size', help = 'Size of region', type = arg_auto_int)
parser_read_chip.add_argument('filename', help = 'Name of binary file')
parser_read_flash = subparsers.add_parser(
'i', help = 'Chip Information')
args = parser.parse_args()
print('=========================================================')
print('%s version %s' % (__progname__, __version__))
print('---------------------------------------------------------')
phy = phyflasher(args.port)
print ('Connecting...')
#--------------------------------
if not phy.Connect(args.baud):
if args.operation == 'ea':
if not phy.cmd_er512():
print ('Error: Erase All Flash!')
sys.exit(3)
exit(0)
else:
print ("Use the 'Erase All Flash' (ea) command to exit FCT mode!")
exit(2)
if args.operation == 'i':
rs = phy.flash_read_status()
if rs == None:
print ('Error Flash read Status!')
sys.exit(3)
print ('Flash Status: 0x%02x' % rs)
rb = phy.flash_read_unique_id()
if rb == None:
print ('Error Flash read Unique ID!')
sys.exit(3)
print ('Flash Serial Number:', rb.hex()) # Unique ID
if args.operation == 'rc':
#filename = "r%08x-%08x.bin" % (addr, length)
if args.size == 0:
print("Read Size = 0!" )
exit(1);
try:
ff = open(args.filename, "wb")
except:
print("Error file open '%s'" % filename)
exit(2)
if not phy.ReadBusToFile(ff, args.address, args.size):
ff.close()
exit(4)
#print
print ('\r---------------------------------------------------------')
byteSaved = (args.size + 3) & 0xfffffffc
if byteSaved > 1024:
print("%.3f KBytes saved to file '%s'" % (byteSaved/1024, args.filename))
else:
print("%i Bytes saved to file '%s'" % (byteSaved, args.filename))
ff.close()
#--------------------------------wr flash bin
if args.operation == 'we' or args.operation == 'wf':
offset = args.address & (MAX_FLASH_SIZE-1)
if offset >= MAX_FLASH_SIZE:
print ('Error Start Flash address!')
sys.exit(1)
stream = open(args.filename, 'rb')
size = os.path.getsize(args.filename)
if size < 1:
stream.close()
print ('Error: File size = 0!')
sys.exit(1)
offset = args.address & (MAX_FLASH_SIZE-1)
if size + offset > MAX_FLASH_SIZE:
size = MAX_FLASH_SIZE - offset
if size < 1:
stream.close()
print ('Error: Write File size = 0!')
sys.exit(1)
aerase = args.operation == 'we'
if args.erase == True or args.allerase == True:
aerase = False;
if args.allerase == True:
if not phy.cmd_erase_all_flash():
stream.close()
print ('Error: Erase All Flash!')
sys.exit(3)
else:
if args.erase == True:
if not phy.cmd_erase_work_flash():
stream.close
print ('Error: Erase Flash!')
sys.exit(3)
phy.SetAutoErase(aerase)
print ('Write Flash data 0x%08x to 0x%08x from file: %s ...' % (offset, offset + size, args.filename))
if not phy.ExpFlashSize():
exit(4)
if size > 0:
if not phy.WriteBlockFlash(stream, offset, size):
stream.close()
print ('Error: Write Flash!')
sys.exit(2)
stream.close()
print ('----------------------------------------------------------')
print ('Write Flash data 0x%08x to 0x%08x from file: %s - ok.' % (offset, offset + size, args.filename))
#--------------------------------wr flash hex
if args.operation == 'wh':
hp = ParseHexFile(args.filename)
if hp == None:
sys.exit(2)
hexf = phy.HexfHeader(hp, args.start, args.write)
if hexf == None:
sys.exit(2)
hp[0][1] = hexf
if not phy.HexStartSend():
sys.exit(2)
print ('----------------------------------------------------------')
aerase = True
if args.erase == True or args.allerase == True:
aerase = False;
if args.allerase == True:
if not phy.cmd_erase_all_flash():
stream.close()
print ('Error: Erase All Flash!')
sys.exit(3)
else:
if args.erase == True:
if not phy.cmd_erase_work_flash():
stream.close
print ('Error: Erase Flash!')
sys.exit(3)
phy.SetAutoErase(aerase)
if not phy.ExpFlashSize():
exit(4)
segment = 0
for ihp in hp:
if ihp[0] == 0:
print('Segment Table[%02d] <- Flash addr: %08x, Size: %08x' % (len(hp) - 1, ihp[2], len(ihp[1])))
else:
print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], ihp[2], len(ihp[1])))
stream = io.BytesIO(ihp[1])
if not phy.WriteBlockFlash(stream, ihp[2], len(ihp[1])):
stream.close()
sys.exit(2)
stream.close()
segment += 1
print ('----------------------------------------------------------')
print ('Write Flash from file: %s - ok.' % args.filename)
#--------------------------------erase flash region
if args.operation == 'er':
offset = args.address & (MAX_FLASH_SIZE-1)
if offset >= MAX_FLASH_SIZE:
print ('Error Flash Start address!')
sys.exit(1)
size = args.size & (MAX_FLASH_SIZE-1)
if size >= MAX_FLASH_SIZE:
print ('Error Flash Erase size!')
sys.exit(1)
if size + offset > MAX_FLASH_SIZE:
size = MAX_FLASH_SIZE - offset
if size < 1:
print ('Error Flash Erase size!')
sys.exit(1)
if not phy.ExpFlashSize():
exit(4)
if not phy.EraseSectorsFlash(offset, size):
sys.exit(2)
#--------------------------------erase flash all
if args.operation == 'ea':
if not phy.cmd_erase_all_flash():
print ('Error: Erase All Flash!')
sys.exit(3)
if args.operation == 'ew':
if not phy.cmd_erase_work_flash():
print ('Error: Erase Flash Work Area!')
sys.exit(3)
if args.reset:
phy.SendResetCmd()
print ("Send command 'reset' - ok")
sys.exit(0)
if __name__ == '__main__':
main()

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/**************************************************************************************************
Filename: bus_dev.h
Revised:
Revision:
Description: This file contains the SoC MCU relate definitions
SDK_LICENSE
**************************************************************************************************/
#ifndef __BUS_DEV_H__
#define __BUS_DEV_H__
#ifdef __cplusplus
extern "C" {
#endif
//#include "mcu.h"
enum
{
RSTC_COLD_UP = 0,
RSTC_WARM_UP = 1,
RSTC_OFF_MODE = 2,
RSTC_WAKE_IO = 3,
RSTC_WAKE_RTC = 4,
RSTC_WARM_NDWC = 5 //user mode, no dwc
};
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- PHY BUMBEE M0 Interrupt Numbers --------------------- */
BB_IRQn = 4, /* Base band Interrupt */
KSCAN_IRQn = 5, /* Key scan Interrupt */
RTC_IRQn = 6, /* RTC Timer Interrupt */
WDT_IRQn = 10, /* Watchdog Timer Interrupt */
UART0_IRQn = 11, /* UART0 Interrupt */
I2C0_IRQn = 12, /* I2C0 Interrupt */
I2C1_IRQn = 13, /* I2C1 Interrupt */
SPI0_IRQn = 14, /* SPI0 Interrupt */
SPI1_IRQn = 15, /* SPI1 Interrupt */
GPIO_IRQn = 16, /* GPIO Interrupt */
UART1_IRQn = 17, /* UART1 Interrupt */
SPIF_IRQn = 18, /* SPIF Interrupt */
DMAC_IRQn = 19, /* DMAC Interrupt */
TIM1_IRQn = 20, /* Timer1 Interrupt */
TIM2_IRQn = 21, /* Timer2 Interrupt */
TIM3_IRQn = 22, /* Timer3 Interrupt */
TIM4_IRQn = 23, /* Timer4 Interrupt */
TIM5_IRQn = 24, /* Timer5 Interrupt */
TIM6_IRQn = 25, /* Timer6 Interrupt */
AES_IRQn = 28, /* AES Interrupt */
ADCC_IRQn = 29, /* ADC Interrupt */
QDEC_IRQn = 30, /* QDEC Interrupt */
RNG_IRQn = 31 /* RNG Interrupt */
} IRQn_Type;
#include "core_bumbee_m0.h"
#include "mcu_phy_bumbee.h"
#endif

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#ifndef PHY_BUMBEE_M0_H
#define PHY_BUMBEE_M0_H
#ifdef __cplusplus
extern "C" {
#endif
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* ------- Start of section using anonymous unions and disabling warnings ------- */
#if defined (__CC_ARM)
#pragma push
#pragma anon_unions
#elif defined (__ICCARM__)
#pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wc11-extensions"
#pragma clang diagnostic ignored "-Wreserved-id-macro"
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning 586
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */
//#define __CM0_REV 0x0000U /* Core revision r0p0 */
//#define __MPU_PRESENT 0U /* MPU present or not */
//#define __VTOR_PRESENT 0U /* no VTOR present*/
#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */
//#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */
#include "core_cm0.h" /* Processor and core peripherals */
#if defined ( __CC_ARM )
#include "system_ARMCM0.h" /* System Header */
#endif /*__CC_ARM*/
#define NVIC_GetPendingIRQs() (NVIC->ISPR[0U])
#define NVIC_ClearPendingIRQs(icpr) (NVIC->ICPR[0U] = (unsigned int)icpr)
#define NVIC_SetPendingIRQs(ispr) (NVIC->ISPR[0U] = (unsigned int)ispr)
#define NVIC_GetEnableIRQs() (NVIC->ISER[0U])
#define NVIC_DisableIRQs(irqs) (NVIC->ICER[0U] = (unsigned int)irqs)
#define NVIC_EnableIRQs(iser) (NVIC->ISER[0U] = (unsigned int)iser)
#define NVIC_ClearWakeupIRQ(irqn)
#define NVIC_SetWakeupIRQ(irqn)
/* -------- End of section using anonymous unions and disabling warnings -------- */
#if defined (__CC_ARM)
#pragma pop
#elif defined (__ICCARM__)
/* leave anonymous unions enabled */
#elif (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#elif defined (__GNUC__)
/* anonymous unions are enabled by default */
#elif defined (__TMS470__)
/* anonymous unions are enabled by default */
#elif defined (__TASKING__)
#pragma warning restore
#elif defined (__CSMC__)
/* anonymous unions are enabled by default */
#else
#warning Not supported compiler type
#endif
#ifdef __cplusplus
}
#endif
#endif /* PHY_BUMBEE_M0 */

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/**
****************************************************************************************
@file global_config.h
@brief This file contains the definitions of index of global configuration which
will be configured in APP project.
$Rev: $
SDK_LICENSE
****************************************************************************************
*/
#ifndef _GLOBAL_CONFIG_H_
#define _GLOBAL_CONFIG_H_
#include "types.h"
/*******************************************************************************
software configuration parameters definition
*/
#define CONFIG_BASE_ADDR 0x1fff0400
#define SOFT_PARAMETER_NUM 256
// parameter index of configuration array
#define ADV_CHANNEL_INTERVAL 0 // interval between adv channel in the same adv event
#define SCAN_RSP_DELAY 1 // to adjust scan req -> scan rsp delay
#define CONN_REQ_TO_SLAVE_DELAY 2 // to calibrate the delay between conn req & 1st slave conn event
#define SLAVE_CONN_DELAY 3 // to adjust the delay between 2 slave connection events
#define SLAVE_CONN_DELAY_BEFORE_SYNC 4 // to adjust the delay between 2 slave connection events before 1st anchor is acquired
#define MAX_SLEEP_TIME 5 // maximum sleep time in us
#define MIN_SLEEP_TIME 6 // minimum sleep time in us
#define WAKEUP_ADVANCE 7 // wakeup advance time, to cover HW delay, crystal settle time, sw delay, ... etc.
#define WAKEUP_DELAY 8 // cycles of SW delay to wait crystal settle
#define HDC_DIRECT_ADV_INTERVAL 9
#define LDC_DIRECT_ADV_INTERVAL 10
#define LL_SWITCH 11 // Link Layer switch, 1 enable, 0 disable
#define NON_ADV_CHANNEL_INTERVAL 12 // interval between non-adv channel in the same adv event
#define CLOCK_SETTING 14 // HCLK
#define LL_HW_BB_DELAY 15
#define LL_HW_AFE_DELAY 16
#define LL_HW_PLL_DELAY 17
#define LL_HW_RTLP_LOOP_TIMEOUT 18
#define LL_HW_RTLP_1ST_TIMEOUT 19
#define MIN_TIME_TO_STABLE_32KHZ_XOSC 20
#define LL_TX_PKTS_PER_CONN_EVT 21
#define LL_RX_PKTS_PER_CONN_EVT 22
// ============= A1 ROM metal change add
#define DIR_ADV_DELAY 23
#define LL_TX_PWR_TO_REG_BIAS 24
#define LL_SMART_WINDOW_COEF_ALPHA 25
#define LL_SMART_WINDOW_TARGET 26
#define LL_SMART_WINDOW_INCREMENT 27
#define LL_SMART_WINDOW_LIMIT 28
#define LL_SMART_WINDOW_ACTIVE_THD 29
#define LL_SMART_WINDOW_ACTIVE_RANGE 30
#define LL_SMART_WINDOW_FIRST_WINDOW 31
#define LL_HW_Tx_TO_RX_INTV 32
#define LL_HW_Rx_TO_TX_INTV 33
#define INITIAL_STACK_PTR 34
#define ALLOW_TO_SLEEP_TICK_RC32K 35
#define LL_HW_BB_DELAY_ADV 36
#define LL_HW_AFE_DELAY_ADV 37
#define LL_HW_PLL_DELAY_ADV 38
// For scan & master, add 2018-6-15
#define LL_ADV_TO_SCAN_REQ_DELAY 39
#define LL_ADV_TO_CONN_REQ_DELAY 40
#define LL_MOVE_TO_MASTER_DELAY 41
#define LL_HW_TRLP_LOOP_TIMEOUT 42
#define LL_CONN_REQ_WIN_SIZE 43
#define LL_CONN_REQ_WIN_OFFSET 44
#define LL_MASTER_PROCESS_TARGET 45
#define LL_MASTER_TIRQ_DELAY 46
#define LL_HW_BB_DELAY_2MPHY 47
#define LL_HW_AFE_DELAY_2MPHY 48
#define LL_HW_PLL_DELAY_2MPHY 49
#define LL_HW_Tx_TO_RX_INTV_2MPHY 50
#define LL_HW_Rx_TO_TX_INTV_2MPHY 51
#define LL_HW_BB_DELAY_500KPHY 52
#define LL_HW_AFE_DELAY_500KPHY 53
#define LL_HW_PLL_DELAY_500KPHY 54
#define LL_HW_Tx_TO_RX_INTV_500KPHY 55
#define LL_HW_Rx_TO_TX_INTV_500KPHY 56
#define LL_HW_BB_DELAY_125KPHY 57
#define LL_HW_AFE_DELAY_125KPHY 58
#define LL_HW_PLL_DELAY_125KPHY 59
#define LL_HW_Tx_TO_RX_INTV_125KPHY 60
#define LL_HW_Rx_TO_TX_INTV_125KPHY 61
#define LL_HW_TRLP_TO_GAP 62
#define LL_HW_RTLP_TO_GAP 63
#define LL_TRX_NUM_ADAPTIVE_CONFIG 64
#define OSAL_SYS_TICK_WAKEUP_TRIM 65
// ==== A2 add, for secondary adv/scan
#define LL_NOCONN_ADV_EST_TIME 70
#define LL_NOCONN_ADV_MARGIN 71
#define LL_SEC_SCAN_MARGIN 72
#define LL_MIN_SCAN_TIME 73
// Bumblebee ROM code
#define LL_CONN_ADV_EST_TIME 74
#define LL_SCANABLE_ADV_EST_TIME 75
#define MAC_ADDRESS_LOC 80
// ==== For Extended Adv & Periodic adv
#define LL_EXT_ADV_INTER_PRI_CHN_INT 81
#define LL_EXT_ADV_INTER_AUX_CHN_INT 82
#define LL_EXT_ADV_RSC_POOL_PERIOD 83
#define LL_EXT_ADV_RSC_POOL_UNIT 84
#define LL_EXT_ADV_TASK_DURATION 86
#define LL_PRD_ADV_TASK_DURATION 87
#define LL_CONN_TASK_DURATION 88
#define TIMER_ISR_ENTRY_TIME 90 // time from HW timer expiry to ISR entry, unit: us
#define LL_MULTICONN_MASTER_PREEMP 91
#define LL_MULTICONN_SLAVE_PREEMP 92
#define LL_EXT_ADV_INTER_SEC_CHN_INT 93
#define LL_EXT_ADV_PRI_2_SEC_CHN_INT 94
#define LL_EXT_ADV_RSC_PERIOD 95
#define LL_EXT_ADV_RSC_SLOT_DURATION 96
#define LL_PRD_ADV_RSC_PERIOD 97
#define LL_PRD_ADV_RSC_SLOT_DURATION 98
#define LL_EXT_ADV_PROCESS_TARGET 99
#define LL_PRD_ADV_PROCESS_TARGET 100
#define EXT_ADV_AUXSCANRSP_DELAY_1MPHY 101
#define EXT_ADV_AUXCONNRSP_DELAY_1MPHY 102
#define EXT_ADV_AUXSCANRSP_DELAY_2MPHY 103
#define EXT_ADV_AUXCONNRSP_DELAY_2MPHY 104
#define EXT_ADV_AUXSCANRSP_DELAY_500KPHY 105
#define EXT_ADV_AUXCONNRSP_DELAY_500KPHY 106
#define EXT_ADV_AUXSCANRSP_DELAY_125KPHY 107
#define EXT_ADV_AUXCONNRSP_DELAY_125KPHY 108
#define EXT_ADV_AUXSCANREQ_DELAY_1MPHY 109
#define EXT_ADV_AUXCONNREQ_DELAY_1MPHY 110
#define EXT_ADV_AUXSCANREQ_DELAY_2MPHY 111
#define EXT_ADV_AUXCONNREQ_DELAY_2MPHY 112
#define EXT_ADV_AUXSCANREQ_DELAY_125KPHY 113
#define EXT_ADV_AUXCONNREQ_DELAY_125KPHY 114
#define LL_EXT_ADV_INTER_SEC_CHN_INT_2MPHY 115
//Open the RX window in advance if the connection interval is too large in sleep mode
#define LL_ENLARGE_ADVANCE_RX_WINDOW_VALUE 116 /// 200
#define GARBAGE_DATA_RESOURCE 117 /// 1000
#define MAXSCANRSPONSES 118 /// 64
// ==============
#define RC32_TRACKINK_ALLOW 0x00000001 // enable tracking RC 32KHz clock with 16MHz hclk
#define SLAVE_LATENCY_ALLOW 0x00000002 // slave latency allow switch
#define LL_DEBUG_ALLOW 0x00000004 // enable invoke RAM project debug output fucntion
#define LL_WHITELIST_ALLOW 0x00000008 // enable whitelist filter
#define LL_RC32K_SEL 0x00000010 // select RC32K RTC, otherwise select crystal 32K RTC
#define SIMUL_CONN_ADV_ALLOW 0x00000020 // allow send adv in connect state
#define SIMUL_CONN_SCAN_ALLOW 0x00000040 // allow scan in connect state
#define CONN_CSA2_ALLOW 0x00000080 // allow using CSA2 in connection state
#define GAP_DUP_RPT_FILTER_DISALLOW 0x00000100 // duplicate report filter in GAP layer, allow default
#define ENH_CONN_CMP_EVENT_ALLOW 0x00000200 // allow LL to send enhanced connection complete event.
// delete 2018-7-17, should use enum H_SYSCLK_SEL
//enum
//{
// CLOCK_16MHZ = 0,
// CLOCK_32MHZ = 1,
// CLOCK_48MHZ = 2,
// CLOCK_64MHZ = 3,
// CLOCK_96MHZ = 4,
// CLOCK_32MHZ_DBL=5
//};
//extern uint32 global_config[SOFT_PARAMETER_NUM];
extern uint32* pGlobal_config; // note: app project needn't this variable
#endif // _GLOBAL_CONFIG_H_

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/*************
mcu_phy_bumbee.h
SDK_LICENSE
***************/
#ifndef __MCU_BUMBEE_M0__
#define __MCU_BUMBEE_M0__
#ifdef __cplusplus
extern "C" {
#endif
#include "types.h"
typedef enum
{
MOD_NONE = 0, MOD_CK802_CPU = 0,
MOD_DMA = 3,
MOD_AES = 4,
MOD_IOMUX = 7,
MOD_UART0 = 8,
MOD_I2C0 = 9,
MOD_I2C1 = 10,
MOD_SPI0 = 11,
MOD_SPI1 = 12,
MOD_GPIO = 13,
MOD_QDEC = 15,
MOD_ADCC = 17,
MOD_PWM = 18,
MOD_SPIF = 19,
MOD_VOC = 20,
MOD_TIMER5 = 21,
MOD_TIMER6 = 22,
MOD_UART1 = 25,
MOD_CP_CPU = 0+32,
MOD_BB = MOD_CP_CPU+3,
MOD_TIMER = MOD_CP_CPU+4,
MOD_WDT = MOD_CP_CPU+5,
MOD_COM = MOD_CP_CPU+6,
MOD_KSCAN = MOD_CP_CPU+7,
MOD_BBREG = MOD_CP_CPU+9,
BBLL_RST = MOD_CP_CPU+10,//can reset,but not gate in here
BBTX_RST = MOD_CP_CPU+11,//can reset,but not gate in here
BBRX_RST = MOD_CP_CPU+12,//can reset,but not gate in here
BBMIX_RST = MOD_CP_CPU+13,//can reset,but not gate in here
MOD_TIMER1 = MOD_CP_CPU+21,
MOD_TIMER2 = MOD_CP_CPU+22,
MOD_TIMER3 = MOD_CP_CPU+23,
MOD_TIMER4 = MOD_CP_CPU+24,
MOD_PCLK_CACHE = 0+64,
MOD_HCLK_CACHE = MOD_PCLK_CACHE+1,
MOD_USR0 = 0+96,
MOD_USR1 = MOD_USR0+1,
MOD_USR2 = MOD_USR0+2,
MOD_USR3 = MOD_USR0+3,
MOD_USR4 = MOD_USR0+4,
MOD_USR5 = MOD_USR0+5,
MOD_USR6 = MOD_USR0+6,
MOD_USR7 = MOD_USR0+7,
MOD_USR8 = MOD_USR0+8,
MOD_SYSTEM = 0xFF,
} MODULE_e;
//SW_CLK -->0x4000f008
#define _CLK_NONE (BIT(0))
#define _CLK_CK802_CPU (BIT(0))
#define _CLK_DMA (BIT(3))
#define _CLK_AES (BIT(4))
#define _CLK_IOMUX (BIT(7))
#define _CLK_UART0 (BIT(8))
#define _CLK_I2C0 (BIT(9))
#define _CLK_I2C1 (BIT(10))
#define _CLK_SPI0 (BIT(11))
#define _CLK_SPI1 (BIT(12))
#define _CLK_GPIO (BIT(13))
#define _CLK_QDEC (BIT(15))
#define _CLK_ADCC (BIT(17))
#define _CLK_PWM (BIT(18))
#define _CLK_SPIF (BIT(19))
#define _CLK_VOC (BIT(20))
#define _CLK_TIMER5 (BIT(21))
#define _CLK_TIMER6 (BIT(22))
#define _CLK_UART1 (BIT(25))
//SW_CLK1 -->0x4000f014
#define _CLK_M0_CPU (BIT(0))
#define _CLK_BB (BIT(3))
#define _CLK_TIMER (BIT(4))
#define _CLK_WDT (BIT(5))
#define _CLK_COM (BIT(6))
#define _CLK_KSCAN (BIT(7))
#define _CLK_BBREG (BIT(9))
#define _CLK_TIMER1 (BIT(21))
#define _CLK_TIMER2 (BIT(22))
#define _CLK_TIMER3 (BIT(23))
#define _CLK_TIMER4 (BIT(24))
#define BB_IRQ_HANDLER V4_IRQ_HANDLER
#define KSCAN_IRQ_HANDLER V5_IRQ_HANDLER
#define RTC_IRQ_HANDLER V6_IRQ_HANDLER
#define CP_COM_IRQ_HANDLER V7_IRQ_HANDLER
#define AP_COM_IRQ_HANDLER V8_IRQ_HANDLER
#define WDT_IRQ_HANDLER V10_IRQ_HANDLER
#define UART0_IRQ_HANDLER V11_IRQ_HANDLER
#define I2C0_IRQ_HANDLER V12_IRQ_HANDLER
#define I2C1_IRQ_HANDLER V13_IRQ_HANDLER
#define SPI0_IRQ_HANDLER V14_IRQ_HANDLER
#define SPI1_IRQ_HANDLER V15_IRQ_HANDLER
#define GPIO_IRQ_HANDLER V16_IRQ_HANDLER
#define UART1_IRQ_HANDLER V17_IRQ_HANDLER
#define SPIF_IRQ_HANDLER V18_IRQ_HANDLER
#define DMAC_IRQ_HANDLER V19_IRQ_HANDLER
#define TIM1_IRQ_HANDLER V20_IRQ_HANDLER
#define TIM2_IRQ_HANDLER V21_IRQ_HANDLER
#define TIM3_IRQ_HANDLER V22_IRQ_HANDLER
#define TIM4_IRQ_HANDLER V23_IRQ_HANDLER
#define TIM5_IRQ_HANDLER V24_IRQ_HANDLER
#define TIM6_IRQ_HANDLER V25_IRQ_HANDLER
#define AES_IRQ_HANDLER V28_IRQ_HANDLER
#define ADCC_IRQ_HANDLER V29_IRQ_HANDLER
#define QDEC_IRQ_HANDLER V30_IRQ_HANDLER
/*******************************************************************************
TYPEDEFS
*/
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
typedef struct
{
__IO uint32_t CH0_AP_MBOX; //0x00
__IO uint32_t CH0_CP_MBOX; //0x04
__IO uint32_t CH1_AP_MBOX; //0x08
__IO uint32_t CH1_CP_MBOX; //0x0c
__IO uint32_t AP_STATUS; //0x10
__IO uint32_t CP_STATUS; //0x14
__IO uint32_t AP_INTEN; //0x18
__IO uint32_t CP_INTEN; //0x1c
__IO uint32_t remap; //0x20
__IO uint32_t RXEV_EN; //0x24
__IO uint32_t STCALIB; //0x28
__IO uint32_t PERI_MASTER_SELECT; //0x2c
} AP_COM_TypeDef;
typedef struct
{
__IO uint32_t CTRL0;//0x40
__IO uint32_t CTRL1;//0x44
uint32_t reserverd[13];
__IO uint32_t REMAP_TABLE;//0x7c
__IO uint32_t REMAP_CTRL[32];//0x80
} AP_CACHE_TypeDef;
typedef struct
{
__IO uint8_t CR; //0x0
uint8_t RESERVED0[3];
__IO uint32_t TORR; //0x4
__O uint32_t CCVR; //0x8
__IO uint32_t CRR; //0xc
uint8_t STAT; //0x10
uint8_t reserverd1[3];
__IO uint8_t EOI; //0x14
uint8_t reserverd2[3];
} AP_WDT_TypeDef;
typedef struct
{
__IO uint32_t SW_RESET0; //0x0
__IO uint32_t SW_RESET1; //0x4
__IO uint32_t SW_CLK; //0x8
__IO uint32_t SW_RESET2; //0xc
__IO uint32_t SW_RESET3; //0x10 bit 1: M0 cpu reset pulse, bit 0: M0 system reset pulse.
__IO uint32_t SW_CLK1; //0x14
__IO uint32_t APB_CLK; //0x18
__IO uint32_t APB_CLK_UPDATE; //0x1c
__IO uint32_t CACHE_CLOCK_GATE;//0x20
__IO uint32_t CACHE_RST;//0x24
__IO uint32_t CACHE_BYPASS;//0x28
} AP_PCR_TypeDef;
typedef struct
{
__IO uint32_t LoadCount; //0x0
__IO uint32_t CurrentCount; //0x4
__IO uint32_t ControlReg; //0x8
__IO uint32_t EOI; //0xc
__IO uint32_t status; //0x10
} AP_TIM_TypeDef;
typedef struct
{
__IO uint32_t IntStatus;
__IO uint32_t EOI;
__IO uint32_t unMaskIntStatus;
__IO uint32_t version;
} AP_TIM_SYS_TypeDef;
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/
typedef struct
{
union
{
__I uint8_t RBR;
__IO uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0; //0x0
};
union
{
__IO uint8_t DLM;
__IO uint32_t IER; //0x4
};
union
{
__I uint32_t IIR; //0x8
__IO uint8_t FCR;
};
__IO uint8_t LCR; //0xc
uint8_t RESERVED1[3];//Reserved
__IO uint32_t MCR; //0x10
__I uint8_t LSR; //0x14
uint8_t RESERVED2[3];//Reserved
__IO uint32_t MSR; //0x18
__IO uint8_t SCR; //0x1c
uint8_t RESERVED3[3];//Reserved
__IO uint32_t LPDLL; //0x20
__IO uint32_t LPDLH; //0x24
__IO uint32_t recerved[2];
union
{
__IO uint32_t SRBR[16]; // 0x30~60xc
__IO uint32_t STHR[16];
};
__IO uint32_t FAR; //0x70
__IO uint32_t TFR; //0x74
__IO uint32_t RFW; // 0x78
__IO uint32_t USR; // 0x7c
__IO uint32_t TFL;
__IO uint32_t RFL;
__IO uint32_t SRR;
__IO uint32_t SRTS;
__IO uint32_t SBCR;
__IO uint32_t SDMAM;
__IO uint32_t SFE;
__IO uint32_t SRT;
__IO uint32_t STET; //0xa0
__IO uint32_t HTX;
__IO uint32_t DMASA; //0xa8
__IO uint32_t reserved[18];
__IO uint32_t CPR; //0xf4
__IO uint32_t UCV;
__IO uint32_t CTR;
} AP_UART_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) setup by zjp-------------------------------*/
typedef struct
{
__IO uint32_t IC_CON;
__IO uint32_t IC_TAR;
__IO uint32_t IC_SAR;
__IO uint32_t IC_HS_MADDR;
__IO uint32_t IC_DATA_CMD; //0x10
__IO uint32_t IC_SS_SCL_HCNT;
__IO uint32_t IC_SS_SCL_LCNT;
__IO uint32_t IC_FS_SCL_HCNT;
__IO uint32_t IC_FS_SCL_LCNT; //0x20
__IO uint32_t IC_HS_SCL_HCNT;
__IO uint32_t IC_HS_SCL_LCNT;
__IO uint32_t IC_INTR_STAT;
__IO uint32_t IC_INTR_MASK; //0x30
__IO uint32_t IC_RAW_INTR_STAT;
__IO uint32_t IC_RX_TL;
__IO uint32_t IC_TX_TL;
__IO uint32_t IC_CLR_INTR; //0x40
__IO uint32_t IC_CLR_UNDER;
__IO uint32_t IC_CLR_RX_OVER;
__IO uint32_t IC_CLR_TX_OVER;
__IO uint32_t IC_CLR_RD_REG; //0x50
__IO uint32_t IC_CLR_TX_ABRT;
__IO uint32_t IC_CLR_RX_DONE;
__IO uint32_t IC_CLR_ACTIVITY;
__IO uint32_t IC_CLR_STOP_DET; //0x60
__IO uint32_t IC_CLR_START_DET;
__IO uint32_t IC_CLR_GEN_CALL;
__IO uint32_t IC_ENABLE;
__IO uint32_t IC_STATUS; //0x70
__IO uint32_t IC_TXFLR;
__IO uint32_t IC_RXFLR;
__IO uint32_t IC_SDA_HOLD;
__IO uint32_t IC_TX_ABRT_SOURCE; //0x80
__IO uint32_t IC_SLV_DATA_NACK_ONLY;
__IO uint32_t IC_DMA_CR;
__IO uint32_t IC_DMA_TDLR;
__IO uint32_t IC_DMA_RDLR; //0x90
__IO uint32_t IC_SDA_SETUP;
__IO uint32_t IC_ACK_GENERAL_CALL;
__IO uint32_t IC_ENABLE_STATUS;
__IO uint32_t IC_FS_SPKLEN; //0xa0
__IO uint32_t IC_HS_SPKLEN;
} AP_I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
typedef struct
{
__IO uint32_t IER;
__IO uint32_t IRER;
__IO uint32_t ITER;
__IO uint32_t CER;
__IO uint32_t CCR;
__IO uint32_t RXFFR;
__IO uint32_t TXFFR;
} AP_I2S_BLOCK_TypeDef;
typedef struct
{
union
{
__IO uint32_t LRBR; //0x20
__IO uint32_t LTHR; //0x20
};
union
{
__IO uint32_t RRBR; // 0x24
__IO uint32_t RTHR; //0x24
};
__IO uint32_t RER; //0x28
__IO uint32_t TER; //0x2c
__IO uint32_t RCR; //0x30
__IO uint32_t TCR; //0x34
__IO uint32_t ISR; //0x38
__IO uint32_t IMR; //0x3c
__IO uint32_t ROR; //0x40
__IO uint32_t TOR; //0x44
__IO uint32_t RFCR; //0x48
__IO uint32_t TFCR; //0x4c
__IO uint32_t RFF; //0x50
__IO uint32_t TFF; //0x54
} AP_I2S_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
__IO uint32_t swporta_dr; //0x00
__IO uint32_t swporta_ddr; //0x04
__IO uint32_t swporta_ctl; //0x08
uint32_t reserved8[9]; //0x18-0x2c portC&D
__IO uint32_t inten; //0x30
__IO uint32_t intmask; //0x34
__IO uint32_t inttype_level; //0x38
__IO uint32_t int_polarity; //0x3c
__I uint32_t int_status; //0x40
__IO uint32_t raw_instatus; //0x44
__IO uint32_t debounce; //0x48
__O uint32_t porta_eoi; //0x4c
__I uint32_t ext_porta; //0x50
uint32_t reserved9[3]; //0x58 0x5c
__IO uint32_t ls_sync; //0x60
__I uint32_t id_code; //0x64
uint32_t reserved10[1]; //0x68
__I uint32_t ver_id_code; //0x6c
__I uint32_t config_reg2; //0x70
__I uint32_t config_reg1; //0x74
} AP_GPIO_TypeDef;
/*-------------------- (SPI) --------------------------------*/
typedef struct
{
__IO uint16_t CR0; //0x0 /*!< Offset: 0x000 Control Register 0 (R/W) */
uint16_t reserved1;
__IO uint16_t CR1; //0x04 /*!< Offset: 0x004 Control Register 1 (R/W) */
uint16_t reserved2;
__IO uint8_t SSIEN; //0x08
uint8_t reserved3[3];
__IO uint8_t MWCR; // 0x0c
uint8_t reserved4[3];
__IO uint8_t SER; //0x10
uint8_t reserved5[3];
__IO uint32_t BAUDR; //0x14
__IO uint32_t TXFTLR; //0x18
__IO uint32_t RXFTLR; //0x1c
__O uint32_t TXFLR; //0x20
__O uint32_t RXFLR; //0x24
__IO uint8_t SR; //0x28
uint8_t reserved7[3];
__IO uint32_t IMR; //0x2c
__IO uint32_t ISR; //0x30
__IO uint32_t RISR; //0x34
__IO uint32_t TXOICR; //0x38
__IO uint32_t RXOICR; //0x3c
__IO uint32_t RXUICR; //0x40
__IO uint32_t MSTICR; //0x44
__IO uint32_t ICR; //0x48
__IO uint32_t DMACR; //0x4c
__IO uint32_t DMATDLR; //0x50
__IO uint32_t DMARDLR; //0x54
__IO uint32_t IDR; //0x5c
__IO uint32_t SSI_COM_VER; //0x5c
__IO uint32_t DataReg;
} AP_SSI_TypeDef;
typedef struct
{
__IO uint32_t Analog_IO_en;//0x00
__IO uint32_t SPI_debug_en;//0x04
__IO uint32_t debug_mux_en;//0x08
__IO uint32_t full_mux0_en;//0x0c
__IO uint32_t full_mux1_en;//0x10 reserved in some soc
__IO uint32_t gpio_pad_en; //0x14
__IO uint32_t gpio_sel[9]; //0x18
__IO uint32_t pad_pe0;//0x3c
__IO uint32_t pad_pe1;//0x40
__IO uint32_t pad_ps0;//0x44
__IO uint32_t pad_ps1;//0x48
__IO uint32_t keyscan_in_en;//0x4c
__IO uint32_t keyscan_out_en;//0x50
} IOMUX_TypeDef;
// 0x4000f05C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
// 0x4000f064 - RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
// uint32_t counter_tracking // 24bit tracking counter, read from 0x4000f064
// counter_tracking = g_counter_traking_avg = STD_RC32_16_CYCLE_16MHZ_CYCLE; hal_rc32k_clk_tracking_init()
// 0x4000f0C0 - SLEEP_R[0] flags =2 RSTC_OFF_MODE, =4 RSTC_WARM_NDWC
// 0x4000f0C4 - SLEEP_R[1] bit7 - first wakeupinit, tracking flags
// 0x4000f0C8 - SLEEP_R[2] использую для сохранения UTC счета времени при перезагрузке
// 0x4000f0CС - SLEEP_R[3] использую для сохранения UTC счета времени при перезагрузке
typedef struct
{
__IO uint32_t PWROFF; //0x00 = 0x5a5aa5a5 enter system off mode
__IO uint32_t PWRSLP; //0x04 = 0xa5a55a5a system sleep mode
__IO uint32_t IOCTL[3]; //0x08 0x0c 0x10
__IO uint32_t PMCTL0; //0x14
__IO uint32_t PMCTL1; //0x18
__IO uint32_t PMCTL2_0; //0x1c bit6 enable software control 32k_clk
__IO uint32_t PMCTL2_1; //0x20
__IO uint32_t RTCCTL; //0x24 bit20 - enable comparator0 envent, bit18 counter overflow interrupt, bit15 enable comparator0 inerrupt,
__IO uint32_t RTCCNT; //0x28 current RTC counter
__IO uint32_t RTCCC0; //0x2c
__IO uint32_t RTCCC1; //0x30
__IO uint32_t RTCCC2; //0x34
__IO uint32_t RTCFLAG; //0x38
__IO uint32_t RTCCLK0; //0x3C bit3:0 = sysclk_t: 1 dll 32m, 2 xtal 16m, 3 dll 48m, 4 dll 64m, 5 dll 96m
__IO uint32_t RTCCLK1; //0x40 bit18 - xtal output to digital enable
__IO uint32_t RTCCFG1; //0x44 - [bit16] enable digclk 96M, [bit7] enable DLL, 25:24 g_rxAdcClkSel 26:25 sel_rxadc_dbl_clk_32M_polarity, 23:22 g_rfPhyClkSel, 6:5 trim dll/dbl ldo vout
__IO uint32_t reserved0[5]; //0x48 4c 50 54 58
__IO uint32_t RTCCFG2; //0x5C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
__IO uint32_t reserved1; //0x60
__IO uint32_t RTCTRCCNT; //0x64 RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle, counter_tracking_wakeup
__IO uint32_t RTCTRCNT; //0x68
__IO uint32_t reserved2[13]; //0x6c 70 74 78 7c 80 84 88 8c 90 94 98 9c
__IO uint32_t REG_S9; //0xa0
__IO uint32_t REG_S10; //0xa4
__IO uint32_t REG_S11; //0xa8 bit0 sleep_flag
__IO uint32_t IDLE_REG; //0xac
__IO uint32_t GPIO_WAKEUP_SRC[2]; //0xb0 b4
__IO uint32_t PCLK_CLK_GATE; //0xb8 bit0 pclk_clk_gate_en
__IO uint32_t XTAL_16M_CTRL; //0xbc
__IO uint32_t SLEEP_R[4]; //0xc0 c4 c8 cc
} AP_AON_TypeDef;
typedef struct
{
__IO uint32_t RTCCTL; //0x24
__IO uint32_t RTCCNT; //0x28
__IO uint32_t RTCCC0; //0x2c
__IO uint32_t RTCCC1; //0x30
__IO uint32_t RTCCC2; //0x34
__IO uint32_t RTCFLAG; //0x38
} AP_RTC_TypeDef;
typedef struct
{
__IO uint32_t io_wu_mask_31_0; //0xa0
__IO uint32_t io_wu_mask_34_32; //0xa4
} AP_Wakeup_TypeDef;
typedef struct
{
__IO uint32_t CLKSEL; //0x3c
__IO uint32_t CLKHF_CTL0; //0x40
__IO uint32_t CLKHF_CTL1; //0x44
__IO uint32_t ANA_CTL; //0x48
__IO uint32_t mem_0_1_dvs; //0x4c
__IO uint32_t mem_2_3_4_dvs; //0x50
__IO uint32_t efuse_cfg; //0x54
__IO uint32_t chip_state; //0x58
__IO uint32_t cal_rw; //0x5c
__IO uint32_t cal_ro0; //0x60
__IO uint32_t cal_ro1; //0x64
__IO uint32_t cal_ro2; //0x68
__IO uint32_t ADC_CTL0; //0x6c
__IO uint32_t ADC_CTL1; //0x70
__IO uint32_t ADC_CTL2; //0x74
__IO uint32_t ADC_CTL3; //0x78
__IO uint32_t ADC_CTL4; //0x7c
uint32_t reserved1[48];
__IO uint32_t EFUSE_PROG[2];//0x140
uint32_t reserved2[6];
__IO uint32_t EFUSE0[2];//0x160
__IO uint32_t EFUSE1[2];//0x168
__IO uint32_t EFUSE2[2];//0x170
__IO uint32_t EFUSE3[2];//0x178
__IO uint32_t SECURTY_STATE;//0x180
} AP_PCRM_TypeDef;
typedef struct
{
__IO uint32_t enable; //0x00
__IO uint32_t reserve0[2]; //0x04~0x08
__IO uint32_t control_1; //0x0c
__IO uint32_t control_2; //0x10
__IO uint32_t control_3; //0x14
__IO uint32_t control_4; //0x18
__IO uint32_t compare_reset; //0x1c
__IO uint32_t int_pointer_ch0_ch3; //0x20
__IO uint32_t int_pointer_ch4_ch7; //0x24
//__IO uint32_t int_pointer[2]; //0x20~0x24
__IO uint32_t reserve1[3]; //0x28~0x30
__IO uint32_t intr_mask; //0x34
__IO uint32_t intr_clear; //0x38
__IO uint32_t intr_status; //0x3c
__IO uint32_t compare_cfg[8]; //0x40~0x5c
} AP_ADCC_TypeDef;
typedef struct
{
__IO uint32_t config; //0x0,QSPI Configuration Register,R/W
__IO uint32_t read_instr; //0x4,Device Read Instruction Register,R/W
__IO uint32_t write_instr; //0x8,Device Write Instruction Register,R/W
__IO uint32_t delay; //0xC,QSPI Device Delay Register,R/W
__IO uint32_t rddata_capture; //0x10,Read Data Capture Register,R/W
__IO uint32_t dev_size; //0x14,Device Size Register,R/W
__IO uint32_t sram_part; //0x18,SRAM Partition Register,R/W
__IO uint32_t indirect_ahb_addr_trig; //0x1C,Indirect AHB Address Trigger Register,R/W
__IO uint32_t dma_peripheral; //0x20,DMA Peripheral Register,R/W
__IO uint32_t remap; //0x24,Remap Address Register,R/W
__IO uint32_t mode_bit; //0x28,Mode Bit Register,R/W
__IO uint32_t sram_fill_level; //0x2C,SRAM Fill Level Register,RO
__IO uint32_t tx_threshold; //0x30,TX Threshold Register,R/W
__IO uint32_t rx_threshold; //0x34,RX Threshold Register,R/W
__IO uint32_t wr_completion_ctrl; //0x38,Write Completion Control Register,R/W
__IO uint32_t poll_expire; //0x3C,Polling Expiration Register,R/W
__IO uint32_t int_status; //0x40,Interrupt Status Register,R/W
__IO uint32_t int_mask; //0x44,Interrupt Mask,R/W
__I uint32_t n1[2]; //0x48~0x4c,Empty
__IO uint32_t low_wr_protection; //0x50,Lower Write Protection Register,R/W
__IO uint32_t up_wr_protection; //0x54,Upper Write Protection Register,R/W
__IO uint32_t wr_protection; //0x58,Write Protection Register,R/W
__I uint32_t n2; //0x5c,Empty
__IO uint32_t indirect_rd; //0x60,Indirect Read Transfer Register,R/W
__IO uint32_t indirect_rd_watermark; //0x64,Indirect Read Transfer Watermark Register,R/W
__IO uint32_t indirect_rd_start_addr; //0x68,Indirect Read Transfer Start Address Register,R/W
__IO uint32_t indirect_rd_num; //0x6C,Indirect Read Transfer Number Bytes Register,R/W
__IO uint32_t indirect_wr; //0x70,Indirect Write Transfer Register,R/W
__IO uint32_t indirect_wr_watermark; //0x74,Indirect Write Transfer Watermark Register,R/W
__IO uint32_t indirect_wr_start_addr; //0x78,Indirect Write Transfer Start Address Register,R/W
__IO uint32_t indirect_wr_cnt; //0x7C,Indirect Write Transfer Count Register,R/W
__IO uint32_t indirect_ahb_trig_addr_range; //0x80,Indirect AHB Trigger Address Range Register,R/W
__I uint32_t n3[3]; //0x84~0x8c,Empty
__IO uint32_t fcmd; //0x90,Flash Command Register,R/W
__IO uint32_t fcmd_addr; //0x94,Flash Command Address Registers,R/W
__I uint32_t n4[2]; //0x98~0x9c,Empty
__IO uint32_t fcmd_rddata[2]; //0xA0,Flash Command Read Data Register (low-a0, up-a4),RO
__IO uint32_t fcmd_wrdata[2]; //0xA8,Flash Command Write Data Register (low-a8, up-ac),R/W
__IO uint32_t poll_fstatus; //0xB0,Polling Flash Status Register,RO
//__IO uint32_t ; //0xFC,Module ID Register,RO
} AP_SPIF_TypeDef;
typedef struct
{
__IO uint32_t ctrl0; //0xc0
__IO uint32_t ctrl1; //0xc4
__IO uint32_t mk_in_en; //0xc8
__IO uint32_t mkc[6]; //0xcc~0xe0
} AP_KSCAN_TypeDef;
typedef struct
{
__IO uint32_t pwmen;
} AP_PWM_TypeDef;
typedef struct
{
__IO uint32_t ctrl0;
__IO uint32_t ctrl1;
} AP_PWMCTRL_TypeDef;
typedef struct
{
__IO uint32_t SAR;
__IO uint32_t SAR_H;
__IO uint32_t DAR;
__IO uint32_t DAR_H;
__IO uint32_t LLP;
__IO uint32_t LLP_H;
__IO uint32_t CTL;
__IO uint32_t CTL_H;
__IO uint32_t SSTAT;
__IO uint32_t SSTAT_H;
__IO uint32_t DSTAT;
__IO uint32_t DSTAT_L;
__IO uint32_t SSTATAR;
__IO uint32_t SSTATAR_H;
__IO uint32_t DSTATAR;
__IO uint32_t DSTATAR_H;
__IO uint32_t CFG;
__IO uint32_t CFG_H;
__IO uint32_t rsv[4];
} AP_DMA_CH_TypeDef;
typedef struct
{
__IO uint32_t RawTfr; //0x2c0
__IO uint32_t RawTfr_H; //0x2c4
__IO uint32_t RawBlock; //0x2c8
__IO uint32_t RawBlock_H; //0x2cc
__IO uint32_t RawSrcTran; //0x2d0
__IO uint32_t RawSrcTran_H; //0x2d4
__IO uint32_t RawDstTran; //0x2d8
__IO uint32_t RawDstTran_H; //0x2dc
__IO uint32_t RawErr; //0x2e0
__IO uint32_t RawErr_H; //0x2e4
__IO uint32_t StatusTfr; //0x2e8
__IO uint32_t StatusTfr_H; //0x2ec
__IO uint32_t StatusBlock; //0x2f0
__IO uint32_t StatusBlock_H; //0x2f4
__IO uint32_t StatusSrcTran; //0x2f8
__IO uint32_t StatusSrcTran_H; //0x2fc
__IO uint32_t StatusDstTran; //0x300
__IO uint32_t StatusDstTran_H; //0x304
__IO uint32_t StatusErr; //0x308
__IO uint32_t StatusErr_H; //0x30c
__IO uint32_t MaskTfr; //0x310
__IO uint32_t MaskTfr_H; //0x314
__IO uint32_t MaskBlock; //0x318
__IO uint32_t MaskBlock_H; //0x31c
__IO uint32_t MaskSrcTran; //0x320
__IO uint32_t MaskSrcTran_H; //0x324
__IO uint32_t MaskDstTran; //0x328
__IO uint32_t MaskDstTran_H; //0x32c
__IO uint32_t MaskErr; //0x330
__IO uint32_t MaskErr_H; //0x334
__IO uint32_t ClearTfr; //0x338
__IO uint32_t ClearTfr_H; //0x33c
__IO uint32_t ClearBlock; //0x340
__IO uint32_t ClearBlock_H; //0x344
__IO uint32_t ClearSrcTran; //0x348
__IO uint32_t ClearSrcTran_H; //0x34c
__IO uint32_t ClearDstTran; //0x350
__IO uint32_t ClearDstTran_H; //0x354
__IO uint32_t ClearErr; //0x358
__IO uint32_t ClearErr_H; //0x35c
__IO uint32_t StatusInt; //0x360
__IO uint32_t StatusInt_H; //0x364
} AP_DMA_INT_TypeDef;
typedef struct
{
__IO uint32_t ReqSrcReg; //0x368
__IO uint32_t ReqSrcReg_H; //0x36c
__IO uint32_t ReqDstReg; //0x370
__IO uint32_t ReqDstReg_H; //0x374
__IO uint32_t SglReqSrcReg; //0x378
__IO uint32_t SglReqSrcReg_H; //0x37c
__IO uint32_t SglReqDstReg; //0x380
__IO uint32_t SglReqDstReg_H; //0x384
__IO uint32_t LstSrcReg; //0x388
__IO uint32_t LstSrcReg_H; //0x38c
__IO uint32_t LstDstReg; //0x390
__IO uint32_t LstDstReg_H; //0x394
} AP_DMA_SW_HANDSHAKE_TypeDef;
typedef struct
{
__IO uint32_t DmaCfgReg; //0x398
__IO uint32_t DmaCfgReg_H; //0x39c
__IO uint32_t ChEnReg; //0x3a0
__IO uint32_t ChEnReg_H; //0x3a4
__IO uint32_t DmaIdReg; //0x3a8
__IO uint32_t DmaIdReg_H; //0x3ac
__IO uint32_t DmaTestReg; //0x3b0
__IO uint32_t DmaTestReg_H; //0x3b4
__IO uint32_t rsv1[4];
__IO uint32_t DMA_COMP_PARAMS_6; //0x3c8
__IO uint32_t DMA_COMP_PARAMS_6_H; //0x3cc
__IO uint32_t DMA_COMP_PARAMS_5; //0x3d0
__IO uint32_t DMA_COMP_PARAMS_5_H; //0x3d4
__IO uint32_t DMA_COMP_PARAMS_4; //0x3d8
__IO uint32_t DMA_COMP_PARAMS_4_H; //0x3dc
__IO uint32_t DMA_COMP_PARAMS_3; //0x3e0
__IO uint32_t DMA_COMP_PARAMS_3_H; //0x3e4
__IO uint32_t DMA_COMP_PARAMS_2; //0x3e8
__IO uint32_t DMA_COMP_PARAMS_2_H; //0x3ec
__IO uint32_t DMA_COMP_PARAMS_1; //0x3f0
__IO uint32_t DMA_COMP_PARAMS_1_H; //0x3f4
__IO uint32_t DMA_ID; //0x3f8
__IO uint32_t DMA_ID_H; //0x3fc
} AP_DMA_MISC_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map(AP) */
/******************************************************************************/
/* Base addresses */
#define AP_APB0_BASE (0x40000000UL)
#define SPIF_BASE_ADDR (0x11000000) /*spif*/
#define AP_PCR_BASE (AP_APB0_BASE + 0x0000)/*pcr*//* APB0 peripherals */
#define AP_TIM1_BASE (AP_APB0_BASE + 0x1000)
#define AP_TIM2_BASE (AP_APB0_BASE + 0x1014)
#define AP_TIM3_BASE (AP_APB0_BASE + 0x1028)
#define AP_TIM4_BASE (AP_APB0_BASE + 0x103c)
#define AP_TIM5_BASE (AP_APB0_BASE + 0x1050)
#define AP_TIM6_BASE (AP_APB0_BASE + 0x1064)
#define AP_TIM_SYS_BASE (AP_APB0_BASE + 0x10a0)
#define AP_WDT_BASE (AP_APB0_BASE + 0x2000)
#define AP_COM_BASE (AP_APB0_BASE + 0x3000)/*com*/
#define AP_IOMUX_BASE (AP_APB0_BASE + 0x3800)/*iomux*/
#define AP_UART0_BASE (AP_APB0_BASE + 0x4000)/*uart0*/
#define AP_I2C0_BASE (AP_APB0_BASE + 0x5000)/*i2c0*/
#define AP_I2C1_BASE (AP_APB0_BASE + 0x5800)/*i2c1*/
#define AP_SPI0_BASE (AP_APB0_BASE + 0x6000)/*spi0*/
#define AP_SPI1_BASE (AP_APB0_BASE + 0x7000)/*spi1*/
#define AP_GPIOA_BASE (AP_APB0_BASE + 0x8000)/*gpio*/
#define AP_UART1_BASE (AP_APB0_BASE + 0x9000)/*uart1*/
#define AP_DMIC_BASE (AP_APB0_BASE + 0xA000)
#define AP_QDEC_BASE (AP_APB0_BASE + 0xB000)/*qdec*/
#define AP_CACHE_BASE (AP_APB0_BASE + 0xC000)
#define AP_SPIF_BASE (AP_APB0_BASE + 0xC800)/*spif*/
#define AP_KSCAN_BASE (AP_APB0_BASE + 0xD0C0)/*kscan*/
#define AP_PWM_BASE (AP_APB0_BASE + 0xE000)/*pwm*/
#define AP_AON_BASE (AP_APB0_BASE + 0xF000)/*aon*/
#define AP_RTC_BASE (AP_APB0_BASE + 0xF024)/*rtc*/
#define AP_PCRM_BASE (AP_APB0_BASE + 0xF03c)/*pcrm*/
#define AP_WAKEUP_BASE (AP_APB0_BASE + 0xF0a0)/*wakeup*/
#define AP_DMAC_BASE (AP_APB0_BASE + 0x10000)/*dmac*/
#define ADCC_BASE_ADDR (AP_APB0_BASE + 0x50000)/*adcc*/
/*bb_top*/
/*linklayer*/
#define SRAM0_BASE_ADDRESS 0x1FFF0000
#define SRAM1_BASE_ADDRESS 0x1FFF4000
#define SRAM2_BASE_ADDRESS 0x1FFF8000
/////////////////////////////////////////////////////////////
#define AP_PCR ((AP_PCR_TypeDef *) AP_PCR_BASE)
#define AP_TIM1 ((AP_TIM_TypeDef *) AP_TIM1_BASE)
#define AP_TIM2 ((AP_TIM_TypeDef *) AP_TIM2_BASE)
#define AP_TIM3 ((AP_TIM_TypeDef *) AP_TIM3_BASE)
#define AP_TIM4 ((AP_TIM_TypeDef *) AP_TIM4_BASE)
#define AP_TIM5 ((AP_TIM_TypeDef *) AP_TIM5_BASE)
#define AP_TIM6 ((AP_TIM_TypeDef *) AP_TIM6_BASE)
#define AP_TIMS ((AP_TIM_SYS_TypeDef *) AP_TIM_SYS_BASE)
#define AP_WDT ((AP_WDT_TypeDef *) AP_WDT_BASE)
#define AP_COM ((AP_COM_TypeDef *) AP_COM_BASE)
#define AP_IOMUX ((IOMUX_TypeDef *) AP_IOMUX_BASE)
#define AP_UART0 ((AP_UART_TypeDef *) AP_UART0_BASE)
#define AP_I2C0 ((AP_I2C_TypeDef *) AP_I2C0_BASE)
#define AP_I2C1 ((AP_I2C_TypeDef *) AP_I2C1_BASE)
#define AP_SPI0 ((AP_SSI_TypeDef *) AP_SPI0_BASE)
#define AP_SPI1 ((AP_SSI_TypeDef *) AP_SPI1_BASE)
#define AP_GPIO ((AP_GPIO_TypeDef *) AP_GPIOA_BASE)
#define AP_UART1 ((AP_UART_TypeDef *) AP_UART1_BASE)
#define AP_CACHE ((AP_CACHE_TypeDef *) AP_CACHE_BASE)
#define AP_SPIF ((AP_SPIF_TypeDef *) AP_SPIF_BASE)
#define AP_KSCAN ((AP_KSCAN_TypeDef *) AP_KSCAN_BASE)
#define AP_PWM ((AP_PWM_TypeDef *) AP_PWM_BASE)
#define AP_PWM_CTRL(n) ((AP_PWMCTRL_TypeDef *) (AP_PWM_BASE + 4 + n*12))
#define AP_AON ((AP_AON_TypeDef *) AP_AON_BASE)
#define AP_RTC ((AP_RTC_TypeDef *) AP_RTC_BASE)
#define AP_PCRM ((AP_PCRM_TypeDef *) AP_PCRM_BASE)
#define AP_WAKEUP ((AP_Wakeup_TypeDef*) AP_WAKEUP_BASE)
#define AP_ADCC ((AP_ADCC_TypeDef *) ADCC_BASE_ADDR)
#define AP_DMA_CH_CFG(n) ((AP_DMA_CH_TypeDef *) (AP_DMAC_BASE+0x58*n))
#define AP_DMA_INT ((AP_DMA_INT_TypeDef *) (AP_DMAC_BASE+0x2c0))
#define AP_DMA_SW_HANDSHAKE ((AP_DMA_SW_HANDSHAKE_TypeDef *) (AP_DMAC_BASE+0x368))
#define AP_DMA_MISC ((AP_DMA_MISC_TypeDef *) (AP_DMAC_BASE+0x398))
/*
watchdog enable state,enable or not.
*/
#define AP_WDT_ENABLE_STATE ((AP_WDT->CR & 0x01))//1:enable 0:disable
#define AP_WDT_FEED do{AP_WDT->CRR = 0x76;}while(0)
/******************************************************************************/
/* Peripheral memory map(CP) */
/******************************************************************************/
/* Base addresses */
#define IRQ_PRIO_REALTIME 0
#define IRQ_PRIO_HIGH 1
#define IRQ_PRIO_HAL 2
#define IRQ_PRIO_THREAD 3
#define IRQ_PRIO_APP 3
#endif

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#ifndef _TYPES_H_
#define _TYPES_H_
#include <stdint.h>
#include <stdbool.h>
typedef signed char int8; //!< Signed 8 bit integer
typedef unsigned char uint8; //!< Unsigned 8 bit integer
typedef signed short int16; //!< Signed 16 bit integer
typedef unsigned short uint16; //!< Unsigned 16 bit integer
typedef signed long int32; //!< Signed 32 bit integer
typedef unsigned long uint32; //!< Unsigned 32 bit integer
typedef uint8 halDataAlign_t; //!< Used for byte alignment
#ifdef __GCC
#define ALIGN4_U8 _Alignas(4) uint8
#define ALIGN4_U16 _Alignas(4) uint16
#define ALIGN4_INT8 _Alignas(4) int8
#define ALIGN4_INT16 _Alignas(4) int16
#else
#define ALIGN4_U8 __align(4) uint8
#define ALIGN4_U16 __align(4) uint16
#define ALIGN4_INT8 __align(4) int8
#define ALIGN4_INT16 __align(4) int16
#endif
#define BIT(n) (1ul << (n))
#define write_reg(addr,data) (*(volatile unsigned int *)(addr)=(unsigned int)(data))
#define read_reg(addr) (*(volatile unsigned int *)(addr))
//bit operations
#define BM_SET(addr,bit) ( *(addr) |= (bit) ) //bit set
#define BM_CLR(addr,bit) ( *(addr) &= ~(bit) ) //bit clear
#define BM_IS_SET(addr,bit) ( *(addr) & (bit) ) //judge bit is set
#ifndef BV
#define BV(n) (1 << (n))
#endif
#ifndef BF
#define BF(x,b,s) (((x) & (b)) >> (s))
#endif
#ifndef MIN
#define MIN(n,m) (((n) < (m)) ? (n) : (m))
#endif
#ifndef MAX
#define MAX(n,m) (((n) < (m)) ? (m) : (n))
#endif
#ifndef ABS
#define ABS(n) (((n) < 0) ? -(n) : (n))
#endif
/* takes a byte out of a uint32 : var - uint32, ByteNum - byte to take out (0 - 3) */
#define BREAK_UINT32( var, ByteNum ) \
(uint8)((uint32)(((var) >>((ByteNum) * 8)) & 0x00FF))
#define BUILD_UINT32(Byte0, Byte1, Byte2, Byte3) \
((uint32)((uint32)((Byte0) & 0x00FF) \
+ ((uint32)((Byte1) & 0x00FF) << 8) \
+ ((uint32)((Byte2) & 0x00FF) << 16) \
+ ((uint32)((Byte3) & 0x00FF) << 24)))
#define BUILD_UINT16(loByte, hiByte) \
((uint16)(((loByte) & 0x00FF) + (((hiByte) & 0x00FF) << 8)))
#define HI_UINT16(a) (((a) >> 8) & 0xFF)
#define LO_UINT16(a) ((a) & 0xFF)
#define BUILD_UINT8(hiByte, loByte) \
((uint8)(((loByte) & 0x0F) + (((hiByte) & 0x0F) << 4)))
// Write the 32bit value of 'val' in little endian format to the buffer pointed
// to by pBuf, and increment pBuf by 4
#define UINT32_TO_BUF_LITTLE_ENDIAN(pBuf,val) \
do { \
*(pBuf)++ = (((val) >> 0) & 0xFF); \
*(pBuf)++ = (((val) >> 8) & 0xFF); \
*(pBuf)++ = (((val) >> 16) & 0xFF); \
*(pBuf)++ = (((val) >> 24) & 0xFF); \
} while (0)
// Return the 32bit little-endian formatted value pointed to by pBuf, and increment pBuf by 4
#define BUF_TO_UINT32_LITTLE_ENDIAN(pBuf) (((pBuf) += 4), BUILD_UINT32((pBuf)[-4], (pBuf)[-3], (pBuf)[-2], (pBuf)[-1]))
#ifndef GET_BIT
#define GET_BIT(DISCS, IDX) (((DISCS)[((IDX) / 8)] & BV((IDX) % 8)) ? TRUE : FALSE)
#endif
#ifndef SET_BIT
#define SET_BIT(DISCS, IDX) (((DISCS)[((IDX) / 8)] |= BV((IDX) % 8)))
#endif
#ifndef CLR_BIT
#define CLR_BIT(DISCS, IDX) (((DISCS)[((IDX) / 8)] &= (BV((IDX) % 8) ^ 0xFF)))
#endif
/* ------------------------------------------------------------------------------------------------
Standard Defines
------------------------------------------------------------------------------------------------
*/
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#ifndef NULL
#define NULL 0
#endif
#define HAL_WAIT_CONDITION(condition) {while(!(condition)){}}
#define HAL_WAIT_CONDITION_TIMEOUT(condition, timeout) {\
volatile int val = 0;\
while(!(condition)){\
if(val ++ > timeout)\
return PPlus_ERR_TIMEOUT;\
}\
}
#define HAL_WAIT_CONDITION_TIMEOUT_WO_RETURN(condition, timeout) {\
volatile int val = 0;\
while(!(condition)){\
if(val ++ > timeout)\
break;\
}\
}
typedef struct _comm_evt_t
{
unsigned int type;
unsigned char* data;
unsigned int len;
} comm_evt_t;
typedef void (*comm_cb_t)(comm_evt_t* pev);
#define __ATTR_SECTION_SRAM__ __attribute__((section("_section_sram_code_")))
#define __ATTR_SECTION_XIP__ __attribute__((section("_section_xip_code_")))
#endif

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/*
main.c
*/
#include <string.h>
#include "global_config.h"
#include "rom_sym_def.h"
#include "ota_boot.h"
#include "bus_dev.h"
/*******************************************************************************/
extern int m_in_critical_region;
extern const uint32_t _sbss;
extern const uint32_t _ebss;
/****************************************************************************
Name: c_start
Description:
This is the reset entry point.
****************************************************************************/
#define WR_BLK_SIZE 256
/* Заголовок OTA */
typedef struct _app_info_t {
uint32_t flag; // id = START_UP_FLAG
uint32_t seg_count; // кол-во сегментов
uint32_t start_addr; // стартовый/run адрес (if = -1 -> берестя из первого значения != -1 у сегмента)
uint32_t app_size; // размер OTA без 4-х байт CRC32
} app_info_t;
app_info_t info_app;
/* Описание сегментов OTA */
typedef struct _app_info_seg_t {
uint32_t faddr; // адрес записи в Flash
uint32_t size; // размер сегмента
uint32_t waddr; // рабочий адрес
uint32_t chk; // не используется
} app_info_seg_t;
app_info_seg_t seg_info;
uint8_t sector_buf[WR_BLK_SIZE];
__attribute__ ((naked))
void copy_app_code(void) {
uint32_t blksize = WR_BLK_SIZE;
uint32_t rfaddr = FADDR_APP_SEC + 0xfc;
uint32_t dfaddr = 0;
uint32_t wfaddr = FADDR_BOOT_ROM_INFO;
uint32_t count;
__disable_irq();
spif_read(rfaddr, (uint8_t*)&rfaddr, 4);
spif_read(rfaddr, (uint8_t*)&info_app, sizeof(info_app));
if(info_app.flag == START_UP_FLAG
&& info_app.seg_count
&& info_app.seg_count < 16
&& info_app.app_size < FADDR_APP_SEC - FADDR_OTA_SEC
){
dfaddr = rfaddr + 0x100;
count = info_app.seg_count;
spif_erase_sector(wfaddr);
spif_write(wfaddr, (uint8_t*)&info_app.seg_count, 4);
spif_write(wfaddr + 8, (uint8_t*)&info_app.start_addr, 4);
wfaddr += 0x100;
while(count--) {
rfaddr += 16;
spif_read(rfaddr, (uint8_t*)&seg_info, 12);
spif_write(wfaddr, (uint8_t*)&seg_info, 12);
wfaddr += 16;
}
wfaddr = FADDR_OTA_SEC;
count = info_app.app_size;
while(count) {
if(count < WR_BLK_SIZE)
blksize = count;
if((wfaddr & (FLASH_SECTOR_SIZE - 1)) == 0)
spif_erase_sector(wfaddr);
spif_read(dfaddr, sector_buf, blksize);
spif_write(wfaddr, sector_buf, blksize);
dfaddr += blksize;
wfaddr += blksize;
count -= blksize;
}
spif_erase_sector(FADDR_APP_SEC);
}
//__disable_irq();
m_in_critical_region++;
/**
config reset casue as RSTC_WARM_NDWC
reset path walkaround dwc
*/
AP_AON->RTCCC2 = BOOT_FLG_OTA; // [0x4000f034] == 0x55 -> OTA
AP_AON->SLEEP_R[0] = 4;
AP_AON->SLEEP_R[1] = 0;
AP_PCR->SW_RESET1 = 0;
while(1);
}
/////////////////////////////////////////////////////////////////////////////////////////////////////////
//xip flash read instrcution
#define XFRD_FCMD_READ 0x0000003
#define XFRD_FCMD_READ_DUAL 0x801003B
#define XFRD_FCMD_READ_QUAD 0x801006B
int main(void) {
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
certain that there are no issues with the state of global variables.
*/
uint8_t* dest = (uint8_t*)&_sbss;
uint8_t* edest = (uint8_t*)&_ebss;
memset(dest, 0, edest - dest);
g_system_clk = SYS_CLK_XTAL_16M; // SYS_CLK_XTAL_16M, SYS_CLK_DBL_32M, SYS_CLK_DLL_64M
spif_config(SYS_CLK_DLL_64M, 1, XFRD_FCMD_READ_DUAL, 0, 0);
copy_app_code();
return 0;
}

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#ifndef __PHY62XX_H
#define __PHY62XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup Configuration_section_for_CMSIS
@{
*/
/**
@brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define __CM0_REV 0 /*!< Core Revision r0p0 */
#define __MPU_PRESENT 0 /*!< M0 provides an MPU */
#define __VTOR_PRESENT 0 /*!< Vector Table Register supported */
#define __NVIC_PRIO_BITS 2 /*!< M0 uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
/**
@}
*/
/** @addtogroup Peripheral_interrupt_number_definition
@{
*/
/**
@brief STM32L0xx Interrupt Number Definition, according to the selected device
in @ref Library_configuration_section
*/
/*!< Interrupt Number Definition */
typedef enum
{
/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
/****** STM32L-0 specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
FLASH_IRQn = 3, /*!< FLASH Interrupt */
RCC_IRQn = 4, /*!< RCC Interrupt */
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
TIM2_IRQn = 15, /*!< TIM2 Interrupt */
TIM6_IRQn = 17, /*!< TIM6 Interrupt */
TIM21_IRQn = 20, /*!< TIM21 Interrupt */
TIM22_IRQn = 22, /*!< TIM22 Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
I2C2_IRQn = 24, /*!< I2C2 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
USART2_IRQn = 28, /*!< USART2 Interrupt */
LPUART1_IRQn = 29, /*!< LPUART1 Interrupts */
} IRQn_Type;
/**
@}
*/
#include "core_cm0.h"
//#include "system_m0.h"
#include <stdint.h>
/**
@}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32L0xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32L0 Family */
/******************************************************************************/
/* Aliases for __IRQn */
/**
@}
*/
/**
@}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __PHY62XX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Public Symbols
****************************************************************************/
.file "phy6222_start.s"
/* *.ld: g_top_irqstack = ORIGIN(sram) + LENGTH(sram) */
.global g_stack
.text
.align 2
.code 16
.globl __start
.thumb_func
.type __start, %function
__start:
ldr r1, = g_irqstack_top
msr msp, r1 /* r2>>sp */
bl main /* R0=IRQ, R1=register save area on stack */
.size __start, .-__start
#if 0 // Implemented in phy6222_vectors.c
.section .isr_vector
.align 4
.globl __Vectors
.type __Vectors, %object
__Vectors:
.long 0
.long __start
.size __Vectors, . - __Vectors
#endif
.section .irq_stack
.align 4
.global g_irqstack_base
.global g_irqstack_top
g_irqstack_base:
.space 0x400
g_irqstack_top:
.end

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#define locate_data(n) __attribute__ ((section(n)))
extern unsigned int g_irqstack_top;
extern void __start(void);
const unsigned _vectors[] locate_data(".isr_vector") =
{
/* Initial stack */
(unsigned)(&g_irqstack_top),
/* Reset exception handler */
(unsigned)(&__start),
};

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/* ----------------------------------------------------------------------
Copyright (C) 2010-2013 ARM Limited. All rights reserved.
$Date: 17. January 2013
$Revision: V1.4.1
Project: CMSIS DSP Library
Title: arm_common_tables.h
Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
Target Processor: Cortex-M4/Cortex-M3
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
- Neither the name of ARM LIMITED nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
#include "arm_math.h"
extern const uint16_t armBitRevTable[1024];
extern const q15_t armRecipTableQ15[64];
extern const q31_t armRecipTableQ31[64];
extern const q31_t realCoefAQ31[1024];
extern const q31_t realCoefBQ31[1024];
extern const float32_t twiddleCoef_16[32];
extern const float32_t twiddleCoef_32[64];
extern const float32_t twiddleCoef_64[128];
extern const float32_t twiddleCoef_128[256];
extern const float32_t twiddleCoef_256[512];
extern const float32_t twiddleCoef_512[1024];
extern const float32_t twiddleCoef_1024[2048];
extern const float32_t twiddleCoef_2048[4096];
extern const float32_t twiddleCoef_4096[8192];
#define twiddleCoef twiddleCoef_4096
extern const q31_t twiddleCoefQ31[6144];
extern const q15_t twiddleCoefQ15[6144];
extern const float32_t twiddleCoef_rfft_32[32];
extern const float32_t twiddleCoef_rfft_64[64];
extern const float32_t twiddleCoef_rfft_128[128];
extern const float32_t twiddleCoef_rfft_256[256];
extern const float32_t twiddleCoef_rfft_512[512];
extern const float32_t twiddleCoef_rfft_1024[1024];
extern const float32_t twiddleCoef_rfft_2048[2048];
extern const float32_t twiddleCoef_rfft_4096[4096];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
#endif /* ARM_COMMON_TABLES_H */

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/* ----------------------------------------------------------------------
Copyright (C) 2010-2013 ARM Limited. All rights reserved.
$Date: 17. January 2013
$Revision: V1.4.1
Project: CMSIS DSP Library
Title: arm_const_structs.h
Description: This file has constant structs that are initialized for
user convenience. For example, some can be given as
arguments to the arm_cfft_f32() function.
Target Processor: Cortex-M4/Cortex-M3
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
- Neither the name of ARM LIMITED nor the names of its contributors
may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------- */
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
#include "arm_math.h"
#include "arm_common_tables.h"
const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 =
{
16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 =
{
32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 =
{
64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 =
{
128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 =
{
256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 =
{
512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 =
{
1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 =
{
2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
};
const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 =
{
4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
};
#endif

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/**************************************************************************//**
@file core_cm0.h
@brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
@version V3.20
@date 25. February 2013
@note
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
CMSIS definitions
******************************************************************************/
/** \ingroup Cortex_M0
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for Cortex-M0 system interrupts */
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

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@ -0,0 +1,801 @@
/**************************************************************************//**
@file core_cm0plus.h
@brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
@version V3.20
@date 25. February 2013
@note
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0PLUS_H_GENERIC
#define __CORE_CM0PLUS_H_GENERIC
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
CMSIS definitions
******************************************************************************/
/** \ingroup Cortex-M0+
@{
*/
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex-M Core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __STATIC_INLINE static __inline
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#define __STATIC_INLINE static inline
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __STATIC_INLINE static inline
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#define __STATIC_INLINE static inline
#endif
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
*/
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include <stdint.h> /* standard types definitions */
#include <core_cmInstr.h> /* Core Instruction Access */
#include <core_cmFunc.h> /* Core Function Access */
#endif /* __CORE_CM0PLUS_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0PLUS_H_DEPENDANT
#define __CORE_CM0PLUS_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0PLUS_REV
#define __CM0PLUS_REV 0x0000
#warning "__CM0PLUS_REV not defined in device header file; using default!"
#endif
#ifndef __MPU_PRESENT
#define __MPU_PRESENT 0
#warning "__MPU_PRESENT not defined in device header file; using default!"
#endif
#ifndef __VTOR_PRESENT
#define __VTOR_PRESENT 0
#warning "__VTOR_PRESENT not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/*@} end of group Cortex-M0+ */
/*******************************************************************************
Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core MPU Register
******************************************************************************/
/** \defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
#if (__VTOR_PRESENT == 1)
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
#else
uint32_t RESERVED0;
#endif
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
\brief Type definitions for the Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
are only accessible over DAP and not via processor. Therefore
they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Cortex-M0+ Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
The function enables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
The function disables a device-specific interrupt in the NVIC interrupt controller.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
The function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
*/
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
The function sets the pending bit of an external interrupt.
\param [in] IRQn Interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
The function clears the pending bit of an external interrupt.
\param [in] IRQn External interrupt number. Value cannot be negative.
*/
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
The function sets the priority of an interrupt.
\note The priority cannot be set for every core interrupt.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
*/
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0)
{
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
else
{
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn));
}
}
/** \brief Get Interrupt Priority
The function reads the priority of an interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
\param [in] IRQn Interrupt number.
\return Interrupt Priority. Value is aligned automatically to the implemented
priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0)
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for Cortex-M0 system interrupts */
else
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS)));
} /* get priority for device specific interrupts */
}
/** \brief System Reset
The function initiates a system reset request to reset the MCU.
*/
__STATIC_INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = ticks - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0PLUS_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

638
ota_boot/source/misc/CMSIS/include/core_cmFunc.h Normal file
View file

@ -0,0 +1,638 @@
/**************************************************************************//**
@file core_cmFunc.h
@brief CMSIS Cortex-M Core Function Access Header File
@version V3.20
@date 25. February 2013
@note
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
// https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Clobbers-and-Scratch-Registers
// The clobber list should not contain the stack pointer register.
// This is because the compiler requires the value of the stack pointer
// to be the same after an asm statement as it was on entry to the statement.
// However, previous versions of GCC did not enforce this rule and allowed the
// stack pointer to appear in the list, with unclear semantics.
// This behavior is deprecated and listing the stack pointer may become an error
// in future versions of GCC.
#if __GNUC__ >= 9
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack));
#else
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
#endif
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
The CMSIS functions have been implemented as intrinsics in the compiler.
Please use "carm -?i" to get an up to date list of all instrinsics,
Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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ota_boot/source/misc/CMSIS/include/core_cmInstr.h Normal file
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@ -0,0 +1,677 @@
/**************************************************************************//**
@file core_cmInstr.h
@brief CMSIS Cortex-M Core Instruction Access Header File
@version V3.20
@date 05. March 2013
@note
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
For thumb1, use low register (r0-r7), specified by constrant "l"
Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
The CMSIS functions have been implemented as intrinsics in the compiler.
Please use "carm -?i" to get an up to date list of all intrinsics,
Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

1023
ota_boot/source/misc/bb_rom_sym_m0.gcc Normal file
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ota_boot/source/misc/ota_upboot.ld Normal file
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/* SRAM + XIP linker script */
/* https://docs.oracle.com/cd/E19120-01/open.solaris/819-0690/6n33n7fds/index.html */
PHDRS
{
romdata PT_LOAD FLAGS(6);
text PT_LOAD FLAGS(5);
data PT_LOAD FLAGS(6);
xip PT_LOAD FLAGS(5);
rodata PT_LOAD FLAGS(4);
}
MEMORY
{
jumptbl (rw) : ORIGIN = 0x1fff0000, LENGTH = 0x00400
gcfgtbl (rw) : ORIGIN = 0x1fff0400, LENGTH = 0x00400
sram (rwx) : ORIGIN = 0x1fff1838, LENGTH = 0x0E7C8
flash (rx) : ORIGIN = 0x11010100, LENGTH = 0x1ff00
sram2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000
sram3 (rwx) : ORIGIN = 0x20010000, LENGTH = 0x02000
sram4 (rwx) : ORIGIN = 0x20012000, LENGTH = 0x00800
}
OUTPUT_ARCH(arm)
EXTERN(_vectors)
ENTRY(__start)
SECTIONS
{
.jumptbl : {
*(jump_table_mem_area)
} > jumptbl : romdata
.gcfgtbl (NOLOAD) : {
*(global_config_area)
} > gcfgtbl
.textentry : {
*(*.isr_vector)
} > sram : text
_sdata = ABSOLUTE(.);
.text : {
_stextram = ABSOLUTE(.);
*phy6222_start.o(.text)
*phy6222_cstart.o(.text)
*main.o(.text.*)
*.o(_section_standby_code_)
*.o(_section_sram_code_)
_etextram = ABSOLUTE(.);
} > sram : text
.data : {
*(.data .data.*)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
} > sram : data
. = ALIGN(4);
_edata = ABSOLUTE(.);
.bss : {
_sbss = ABSOLUTE(.);
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = ABSOLUTE(.);
} > sram
.irq_stack : {
*(g_irqstack_base)
} > sram
g_stack = ORIGIN(sram) + LENGTH(sram);
.xip : {
_stext = ABSOLUTE(.);
*.o(_func_xip_code_)
*.o(_section_xip_code_)
*(.text .text.*)
_etext = ABSOLUTE(.);
} > flash : xip
.rodata : {
*(.rodata .rodata.*)
*(.fixup)
*(.gnu.warning)
*(.rodata .rodata.*)
*(.gnu.linkonce.t.*)
*(.glue_7)
*(.glue_7t)
*(.got)
*(.gcc_except_table)
*(.gnu.linkonce.r.*)
} > flash : rodata
.init_section : {
_sinit = ABSOLUTE(.);
*(.init_array .init_array.*)
_einit = ABSOLUTE(.);
} > flash : rodata
.ARM.extab : {
*(.ARM.extab*)
} > flash : rodata
.ARM.exidx : {
__exidx_start = ABSOLUTE(.);
*(.ARM.exidx*)
__exidx_end = ABSOLUTE(.);
} > flash : rodata
._sjtblsstore : {
_sjtblss = ABSOLUTE(.);
} > flash : rodata
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

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ota_boot/source/misc/rom_sym_def.h Normal file
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/*************
rom_sym_def.h
SDK_LICENSE
***************/
#ifndef __ROM_SYM_H__
#define __ROM_SYM_H__
#ifdef USE_ROMSYM_ALIAS
#define m_in_critical_region _symrom_m_in_critical_region
#define _spif_read_status_reg _symrom__spif_read_status_reg
#define _spif_wait_nobusy _symrom__spif_wait_nobusy
#define adv_param _symrom_adv_param
#define app_sleep_process _symrom_app_sleep_process
#define app_wakeup_process _symrom_app_wakeup_process
#define ate_fun_test _symrom_ate_fun_test
#define ate_sleep_process _symrom_ate_sleep_process
#define ate_wakeup_process _symrom_ate_wakeup_process
#define baseTaskID _symrom_baseTaskID
#define bit_to_byte _symrom_bit_to_byte
#define ble_crc24_gen _symrom_ble_crc24_gen
#define bleEvtMask _symrom_bleEvtMask
#define boot_init _symrom_boot_init
#define boot_init0 _symrom_boot_init0
#define boot_m0 _symrom_boot_m0
#define bx_to_application _symrom_bx_to_application
#define byte_to_bit _symrom_byte_to_bit
#define cachedTRNGdata _symrom_cachedTRNGdata
#define calculate_whiten_seed _symrom_calculate_whiten_seed
#define cbTimers _symrom_cbTimers
#define chanMapUpdate _symrom_chanMapUpdate
#define clear_timer _symrom_clear_timer
#define clear_timer_int _symrom_clear_timer_int
#define clk_get_pclk _symrom_clk_get_pclk
#define clk_init _symrom_clk_init
#define clk_set_pclk_div _symrom_clk_set_pclk_div
#define clk_spif_ref_clk _symrom_clk_spif_ref_clk
#define config_RTC _symrom_config_RTC
#define conn_param _symrom_conn_param
#define connUpdateTimer _symrom_connUpdateTimer
#define counter_tracking _symrom_counter_tracking
#define rom_crc16 _symrom_crc16
#define ctrlToHostEnable _symrom_ctrlToHostEnable
#define dataPkt _symrom_dataPkt
#define debug_print _symrom_debug_print
#define deviceFeatureSet _symrom_deviceFeatureSet
#define disableSleep _symrom_disableSleep
#define drv_disable_irq _symrom_drv_disable_irq
#define drv_enable_irq _symrom_drv_enable_irq
#define drv_irq_init _symrom_drv_irq_init
#define dwc_connect _symrom_dwc_connect
#define dwc_data_process _symrom_dwc_data_process
#define dwc_loop _symrom_dwc_loop
#define efuse_read _symrom_efuse_read
#define enableSleep _symrom_enableSleep
#define enter_sleep_off_mode _symrom_enter_sleep_off_mode
#define enterSleepProcess _symrom_enterSleepProcess
#define ext_adv_hdr _symrom_ext_adv_hdr
#define extInitInfo _symrom_extInitInfo
#define extScanInfo _symrom_extScanInfo
#define fastTxRespTime _symrom_fastTxRespTime
#define forever_write _symrom_forever_write
#define g_adv_taskEvent _symrom_g_adv_taskEvent
#define g_adv_taskID _symrom_g_adv_taskID
#define g_advPerSlotTick _symrom_g_advPerSlotTick
#define g_advSetMaximumLen _symrom_g_advSetMaximumLen
#define g_advSlotPeriodic _symrom_g_advSlotPeriodic
#define g_blePktVersion _symrom_g_blePktVersion
#define g_conn_taskEvent _symrom_g_conn_taskEvent
#define g_conn_taskID _symrom_g_conn_taskID
#define g_counter_traking_avg _symrom_g_counter_traking_avg
#define g_counter_traking_cnt _symrom_g_counter_traking_cnt
#define g_currentAdvTimer _symrom_g_currentAdvTimer
#define g_currentExtAdv _symrom_g_currentExtAdv
#define g_currentExtAdv_periodic _symrom_g_currentExtAdv_periodic
#define g_currentTimerTask _symrom_g_currentTimerTask
#define g_dle_taskEvent _symrom_g_dle_taskEvent
#define g_dle_taskID _symrom_g_dle_taskID
//#define g_dtmAccessCode _symrom_g_dtmAccessCode
//#define g_dtmCarrSens _symrom_g_dtmCarrSens
//#define g_dtmCmd _symrom_g_dtmCmd
//#define g_dtmCtrl _symrom_g_dtmCtrl
//#define g_dtmEvt _symrom_g_dtmEvt
//#define g_dtmExtLen _symrom_g_dtmExtLen
//#define g_dtmFoff _symrom_g_dtmFoff
//#define g_dtmFreq _symrom_g_dtmFreq
//#define g_dtmLength _symrom_g_dtmLength
//#define g_dtmModeType _symrom_g_dtmModeType
//#define g_dtmPara _symrom_g_dtmPara
//#define g_dtmPerAutoIntv _symrom_g_dtmPerAutoIntv
//#define g_dtmPKT _symrom_g_dtmPKT
//#define g_dtmPktCount _symrom_g_dtmPktCount
//#define g_dtmPktIntv _symrom_g_dtmPktIntv
//#define g_dtmRsp _symrom_g_dtmRsp
//#define g_dtmRssi _symrom_g_dtmRssi
//#define g_dtmRxCrcNum _symrom_g_dtmRxCrcNum
//#define g_dtmRxTONum _symrom_g_dtmRxTONum
//#define g_dtmStatus _symrom_g_dtmStatus
//#define g_dtmTick _symrom_g_dtmTick
//#define g_dtmTpCalEnable _symrom_g_dtmTpCalEnable
//#define g_dtmTxPower _symrom_g_dtmTxPower
#define g_extAdvNumber _symrom_g_extAdvNumber
#define g_getPn23_cnt _symrom_g_getPn23_cnt
#define g_getPn23_seed _symrom_g_getPn23_seed
#define g_hclk _symrom_g_hclk
#define g_interAuxPduDuration _symrom_g_interAuxPduDuration
#define g_ll_conn_ctx _symrom_g_ll_conn_ctx
#define g_llHdcDirAdvTime _symrom_g_llHdcDirAdvTime
#define g_llPduLen _symrom_g_llPduLen
#define g_llPeriodAdvSyncInfo _symrom_g_llPeriodAdvSyncInfo
#define g_llResolvinglist _symrom_g_llResolvinglist
#define g_llRlDeviceNum _symrom_g_llRlDeviceNum
#define g_llRlEnable _symrom_g_llRlEnable
#define g_llRlTimeout _symrom_g_llRlTimeout
#define g_llSleepContext _symrom_g_llSleepContext
#define g_llWhitelist _symrom_g_llWhitelist
#define g_llWlDeviceNum _symrom_g_llWlDeviceNum
#define g_maxConnNum _symrom_g_maxConnNum
#define g_maxPktPerEventRx _symrom_g_maxPktPerEventRx
#define g_maxPktPerEventTx _symrom_g_maxPktPerEventTx
#define g_new_master_delta _symrom_g_new_master_delta
#define g_osal_tick_trim _symrom_g_osal_tick_trim
#define g_osalTickTrim_mod _symrom_g_osalTickTrim_mod
#define g_pAdvSchInfo _symrom_g_pAdvSchInfo
#define g_pAdvSchInfo_periodic _symrom_g_pAdvSchInfo_periodic
#define g_perioAdvNumber _symrom_g_perioAdvNumber
#define g_pExtendedAdvInfo _symrom_g_pExtendedAdvInfo
#define g_phyChg_taskEvent _symrom_g_phyChg_taskEvent
#define g_phyChg_taskID _symrom_g_phyChg_taskID
#define g_pLLcteISample _symrom_g_pLLcteISample
#define g_pLLcteQSample _symrom_g_pLLcteQSample
#define g_pmCounters _symrom_g_pmCounters
#define g_pPeriodicAdvInfo _symrom_g_pPeriodicAdvInfo
//#define g_rfPhyClkSel _symrom_g_rfPhyClkSel
//#define g_rfPhyDtmCmd _symrom_g_rfPhyDtmCmd
//#define g_rfPhyDtmEvt _symrom_g_rfPhyDtmEvt
//#define g_rfPhyFreqOffSet _symrom_g_rfPhyFreqOffSet
//#define g_rfPhyPktFmt _symrom_g_rfPhyPktFmt
//#define g_rfPhyRxDcIQ _symrom_g_rfPhyRxDcIQ
//#define g_rfPhyTpCal0 _symrom_g_rfPhyTpCal0
//#define g_rfPhyTpCal0_2Mbps _symrom_g_rfPhyTpCal0_2Mbps
//#define g_rfPhyTpCal1 _symrom_g_rfPhyTpCal1
//#define g_rfPhyTpCal1_2Mbps _symrom_g_rfPhyTpCal1_2Mbps
//#define g_rfPhyTxPower _symrom_g_rfPhyTxPower
#define g_rx_adv_buf _symrom_g_rx_adv_buf
//#define g_rxAdcClkSel _symrom_g_rxAdcClkSel
#define g_same_rf_channel_flag _symrom_g_same_rf_channel_flag
#define g_schExtAdvNum _symrom_g_schExtAdvNum
#define g_schExtAdvNum_periodic _symrom_g_schExtAdvNum_periodic
#define g_smartWindowActive _symrom_g_smartWindowActive
#define g_smartWindowActiveCnt _symrom_g_smartWindowActiveCnt
#define g_smartWindowLater _symrom_g_smartWindowLater
#define g_smartWindowPreAnchPoint _symrom_g_smartWindowPreAnchPoint
#define g_smartWindowRTOCnt _symrom_g_smartWindowRTOCnt
#define g_smartWindowSize _symrom_g_smartWindowSize
#define g_smartWindowSizeNew _symrom_g_smartWindowSizeNew
#define g_system_clk _symrom_g_system_clk
#define g_TIM2_IRQ_PendingTick _symrom_g_TIM2_IRQ_PendingTick
#define g_TIM2_IRQ_TIM3_CurrCount _symrom_g_TIM2_IRQ_TIM3_CurrCount
#define g_TIM2_IRQ_to_Sleep_DeltTick _symrom_g_TIM2_IRQ_to_Sleep_DeltTick
#define g_TIM2_wakeup_delay _symrom_g_TIM2_wakeup_delay
#define g_timerExpiryTick _symrom_g_timerExpiryTick
#define g_tx_adv_buf _symrom_g_tx_adv_buf
#define g_tx_ext_adv_buf _symrom_g_tx_ext_adv_buf
#define g_wakeup_rtc_tick _symrom_g_wakeup_rtc_tick
#define get_rx_read_ptr _symrom_get_rx_read_ptr
#define get_rx_write_ptr _symrom_get_rx_write_ptr
#define get_sleep_flag _symrom_get_sleep_flag
#define get_timer_count _symrom_get_timer_count
#define get_timer_int _symrom_get_timer_int
#define get_tx_read_ptr _symrom_get_tx_read_ptr
#define get_tx_write_ptr _symrom_get_tx_write_ptr
#define getMcuPrecisionCount _symrom_getMcuPrecisionCount
#define getPN23RandNumber _symrom_getPN23RandNumber
#define getRxBufferFree _symrom_getRxBufferFree
#define getRxBufferSize _symrom_getRxBufferSize
#define getSleepMode _symrom_getSleepMode
#define getTxBufferFree _symrom_getTxBufferFree
#define getTxBufferSize _symrom_getTxBufferSize
#define gpio_cfg_analog_io _symrom_gpio_cfg_analog_io
#define gpio_dir _symrom_gpio_dir
#define gpio_fmux_control _symrom_gpio_fmux_control
#define gpio_fmux_set _symrom_gpio_fmux_set
#define gpio_in_trigger _symrom_gpio_in_trigger
#define gpio_init _symrom_gpio_init
#define gpio_interrupt_set _symrom_gpio_interrupt_set
#define GPIO_IRQHandler _symrom_GPIO_IRQHandler
#define gpio_pull_set _symrom_gpio_pull_set
#define gpio_read _symrom_gpio_read
#define gpio_wakeup_set _symrom_gpio_wakeup_set
#define gpio_write _symrom_gpio_write
#define HardFault_Handler _symrom_HardFault_Handler
#define HardFault_IRQHandler _symrom_HardFault_IRQHandler
#define HCI_bm_alloc _symrom_HCI_bm_alloc
#define HCI_CommandCompleteEvent _symrom_HCI_CommandCompleteEvent
#define HCI_CommandStatusEvent _symrom_HCI_CommandStatusEvent
#define HCI_DataBufferOverflowEvent _symrom_HCI_DataBufferOverflowEvent
#define HCI_DisconnectCmd _symrom_HCI_DisconnectCmd
#define HCI_ExtTaskRegister _symrom_HCI_ExtTaskRegister
#define HCI_GAPTaskRegister _symrom_HCI_GAPTaskRegister
#define HCI_HardwareErrorEvent _symrom_HCI_HardwareErrorEvent
#define HCI_HostBufferSizeCmd _symrom_HCI_HostBufferSizeCmd
#define HCI_HostNumCompletedPktCmd _symrom_HCI_HostNumCompletedPktCmd
#define HCI_Init _symrom_HCI_Init
#define HCI_L2CAPTaskRegister _symrom_HCI_L2CAPTaskRegister
#define HCI_LE_AddDevToResolvingListCmd _symrom_HCI_LE_AddDevToResolvingListCmd
#define HCI_LE_AddWhiteListCmd _symrom_HCI_LE_AddWhiteListCmd
#define HCI_LE_ClearAdvSetsCmd _symrom_HCI_LE_ClearAdvSetsCmd
#define HCI_LE_ClearResolvingListCmd _symrom_HCI_LE_ClearResolvingListCmd
#define HCI_LE_ClearWhiteListCmd _symrom_HCI_LE_ClearWhiteListCmd
#define HCI_LE_Connection_CTE_Request_EnableCmd _symrom_HCI_LE_Connection_CTE_Request_EnableCmd
#define HCI_LE_Connection_CTE_Response_EnableCmd _symrom_HCI_LE_Connection_CTE_Response_EnableCmd
#define HCI_LE_ConnectionlessCTE_TransmitEnableCmd _symrom_HCI_LE_ConnectionlessCTE_TransmitEnableCmd
#define HCI_LE_ConnectionlessCTE_TransmitParamCmd _symrom_HCI_LE_ConnectionlessCTE_TransmitParamCmd
#define HCI_LE_ConnectionlessIQ_SampleEnableCmd _symrom_HCI_LE_ConnectionlessIQ_SampleEnableCmd
#define HCI_LE_ConnUpdateCmd _symrom_HCI_LE_ConnUpdateCmd
#define HCI_LE_CreateConnCancelCmd _symrom_HCI_LE_CreateConnCancelCmd
#define HCI_LE_CreateConnCmd _symrom_HCI_LE_CreateConnCmd
#define HCI_LE_EncryptCmd _symrom_HCI_LE_EncryptCmd
#define HCI_LE_ExtendedCreateConnectionCmd _symrom_HCI_LE_ExtendedCreateConnectionCmd
#define HCI_LE_LtkReqNegReplyCmd _symrom_HCI_LE_LtkReqNegReplyCmd
#define HCI_LE_LtkReqReplyCmd _symrom_HCI_LE_LtkReqReplyCmd
#define HCI_LE_PeriodicAdvertisingCreateSyncCancelCmd _symrom_HCI_LE_PeriodicAdvertisingCreateSyncCancelCmd
#define HCI_LE_PeriodicAdvertisingCreateSyncCmd _symrom_HCI_LE_PeriodicAdvertisingCreateSyncCmd
#define HCI_LE_PeriodicAdvertisingTerminateSyncCmd _symrom_HCI_LE_PeriodicAdvertisingTerminateSyncCmd
#define HCI_LE_RandCmd _symrom_HCI_LE_RandCmd
#define HCI_LE_READ_Anatenna_InfoCmd _symrom_HCI_LE_READ_Anatenna_InfoCmd
#define HCI_LE_ReadAdvChanTxPowerCmd _symrom_HCI_LE_ReadAdvChanTxPowerCmd
#define HCI_LE_ReadBufSizeCmd _symrom_HCI_LE_ReadBufSizeCmd
#define HCI_LE_ReadChannelMapCmd _symrom_HCI_LE_ReadChannelMapCmd
#define HCI_LE_ReadLocalSupportedFeaturesCmd _symrom_HCI_LE_ReadLocalSupportedFeaturesCmd
#define HCI_LE_ReadMaxDataLengthCmd _symrom_HCI_LE_ReadMaxDataLengthCmd
#define HCI_LE_ReadMaximumAdvDataLengthCmd _symrom_HCI_LE_ReadMaximumAdvDataLengthCmd
#define HCI_LE_ReadNumberOfSupportAdvSetCmd _symrom_HCI_LE_ReadNumberOfSupportAdvSetCmd
#define HCI_LE_ReadPhyMode _symrom_HCI_LE_ReadPhyMode
#define HCI_LE_ReadRemoteUsedFeaturesCmd _symrom_HCI_LE_ReadRemoteUsedFeaturesCmd
#define HCI_LE_ReadResolvingListSizeCmd _symrom_HCI_LE_ReadResolvingListSizeCmd
#define HCI_LE_ReadSuggestedDefaultDataLengthCmd _symrom_HCI_LE_ReadSuggestedDefaultDataLengthCmd
#define HCI_LE_ReadSupportedStatesCmd _symrom_HCI_LE_ReadSupportedStatesCmd
#define HCI_LE_ReadWhiteListSizeCmd _symrom_HCI_LE_ReadWhiteListSizeCmd
#define HCI_LE_ReceiverTestCmd _symrom_HCI_LE_ReceiverTestCmd
#define HCI_LE_RemoveAdvSetCmd _symrom_HCI_LE_RemoveAdvSetCmd
#define HCI_LE_RemoveResolvingListCmd _symrom_HCI_LE_RemoveResolvingListCmd
#define HCI_LE_RemoveWhiteListCmd _symrom_HCI_LE_RemoveWhiteListCmd
#define HCI_LE_Set_ConnectionCTE_ReceiveParamCmd _symrom_HCI_LE_Set_ConnectionCTE_ReceiveParamCmd
#define HCI_LE_Set_ConnectionCTE_TransmitParamCmd _symrom_HCI_LE_Set_ConnectionCTE_TransmitParamCmd
#define HCI_LE_SetAddressResolutionEnableCmd _symrom_HCI_LE_SetAddressResolutionEnableCmd
#define HCI_LE_SetAdvDataCmd _symrom_HCI_LE_SetAdvDataCmd
#define HCI_LE_SetAdvEnableCmd _symrom_HCI_LE_SetAdvEnableCmd
#define HCI_LE_SetAdvParamCmd _symrom_HCI_LE_SetAdvParamCmd
#define HCI_LE_SetDataLengthCmd _symrom_HCI_LE_SetDataLengthCmd
#define HCI_LE_SetDefaultPhyMode _symrom_HCI_LE_SetDefaultPhyMode
#define HCI_LE_SetEventMaskCmd _symrom_HCI_LE_SetEventMaskCmd
#define HCI_LE_SetExtAdvDataCmd _symrom_HCI_LE_SetExtAdvDataCmd
#define HCI_LE_SetExtAdvEnableCmd _symrom_HCI_LE_SetExtAdvEnableCmd
#define HCI_LE_SetExtAdvParamCmd _symrom_HCI_LE_SetExtAdvParamCmd
#define HCI_LE_SetExtAdvSetRandomAddressCmd _symrom_HCI_LE_SetExtAdvSetRandomAddressCmd
#define HCI_LE_SetExtendedScanEnableCmd _symrom_HCI_LE_SetExtendedScanEnableCmd
#define HCI_LE_SetExtendedScanParametersCmd _symrom_HCI_LE_SetExtendedScanParametersCmd
#define HCI_LE_SetExtScanRspDataCmd _symrom_HCI_LE_SetExtScanRspDataCmd
#define HCI_LE_SetHostChanClassificationCmd _symrom_HCI_LE_SetHostChanClassificationCmd
#define HCI_LE_SetPeriodicAdvDataCmd _symrom_HCI_LE_SetPeriodicAdvDataCmd
#define HCI_LE_SetPeriodicAdvEnableCmd _symrom_HCI_LE_SetPeriodicAdvEnableCmd
#define HCI_LE_SetPeriodicAdvParameterCmd _symrom_HCI_LE_SetPeriodicAdvParameterCmd
#define HCI_LE_SetPhyMode _symrom_HCI_LE_SetPhyMode
#define HCI_LE_SetRandomAddressCmd _symrom_HCI_LE_SetRandomAddressCmd
#define HCI_LE_SetResolvablePrivateAddressTimeoutCmd _symrom_HCI_LE_SetResolvablePrivateAddressTimeoutCmd
#define HCI_LE_SetScanEnableCmd _symrom_HCI_LE_SetScanEnableCmd
#define HCI_LE_SetScanParamCmd _symrom_HCI_LE_SetScanParamCmd
#define HCI_LE_SetScanRspDataCmd _symrom_HCI_LE_SetScanRspDataCmd
#define HCI_LE_StartEncyptCmd _symrom_HCI_LE_StartEncyptCmd
#define HCI_LE_TestEndCmd _symrom_HCI_LE_TestEndCmd
#define HCI_LE_TransmitterTestCmd _symrom_HCI_LE_TransmitterTestCmd
#define HCI_LE_WriteSuggestedDefaultDataLengthCmd _symrom_HCI_LE_WriteSuggestedDefaultDataLengthCmd
#define HCI_NumOfCompletedPacketsEvent _symrom_HCI_NumOfCompletedPacketsEvent
#define HCI_ProcessEvent _symrom_HCI_ProcessEvent
#define HCI_ReadBDADDRCmd _symrom_HCI_ReadBDADDRCmd
#define HCI_ReadLocalSupportedCommandsCmd _symrom_HCI_ReadLocalSupportedCommandsCmd
#define HCI_ReadLocalSupportedFeaturesCmd _symrom_HCI_ReadLocalSupportedFeaturesCmd
#define HCI_ReadLocalVersionInfoCmd _symrom_HCI_ReadLocalVersionInfoCmd
#define HCI_ReadRemoteVersionInfoCmd _symrom_HCI_ReadRemoteVersionInfoCmd
#define HCI_ReadRssiCmd _symrom_HCI_ReadRssiCmd
#define HCI_ReadTransmitPowerLevelCmd _symrom_HCI_ReadTransmitPowerLevelCmd
#define HCI_ResetCmd _symrom_HCI_ResetCmd
#define HCI_ReverseBytes _symrom_HCI_ReverseBytes
#define HCI_SendCommandCompleteEvent _symrom_HCI_SendCommandCompleteEvent
#define HCI_SendCommandStatusEvent _symrom_HCI_SendCommandStatusEvent
#define HCI_SendControllerToHostEvent _symrom_HCI_SendControllerToHostEvent
#define HCI_SendDataPkt _symrom_HCI_SendDataPkt
#define HCI_SetControllerToHostFlowCtrlCmd _symrom_HCI_SetControllerToHostFlowCtrlCmd
#define HCI_SetEventMaskCmd _symrom_HCI_SetEventMaskCmd
#define HCI_SMPTaskRegister _symrom_HCI_SMPTaskRegister
#define HCI_TestAppTaskRegister _symrom_HCI_TestAppTaskRegister
#define HCI_ValidConnTimeParams _symrom_HCI_ValidConnTimeParams
#define HCI_VendorSpecifcCommandCompleteEvent _symrom_HCI_VendorSpecifcCommandCompleteEvent
#define hciCmdTable _symrom_hciCmdTable
#define hciCtrlCmdToken _symrom_hciCtrlCmdToken
#define hciExtTaskID _symrom_hciExtTaskID
#define hciGapTaskID _symrom_hciGapTaskID
#define hciInitEventMasks _symrom_hciInitEventMasks
#define hciL2capTaskID _symrom_hciL2capTaskID
#define hciPTMenabled _symrom_hciPTMenabled
#define hciSmpTaskID _symrom_hciSmpTaskID
#define hciTaskID _symrom_hciTaskID
#define hciTestTaskID _symrom_hciTestTaskID
#define hclk_per_us _symrom_hclk_per_us
#define hclk_per_us_shift _symrom_hclk_per_us_shift
#define initInfo _symrom_initInfo
#define ISR_entry_time _symrom_ISR_entry_time
#define isSleepAllow _symrom_isSleepAllow
#define isTimer1Running _symrom_isTimer1Running
#define isTimer4Running _symrom_isTimer4Running
#define jump_area_init _symrom_jump_area_init
#define ll_add_adv_task _symrom_ll_add_adv_task
#define ll_add_adv_task_periodic _symrom_ll_add_adv_task_periodic
#define LL_AddResolvingListLDevice _symrom_LL_AddResolvingListLDevice
#define ll_addTask _symrom_ll_addTask
#define LL_AddWhiteListDevice _symrom_LL_AddWhiteListDevice
#define ll_adptive_adj_next_time _symrom_ll_adptive_adj_next_time
#define ll_adptive_smart_window _symrom_ll_adptive_smart_window
#define ll_adv_scheduler _symrom_ll_adv_scheduler
#define ll_adv_scheduler_periodic _symrom_ll_adv_scheduler_periodic
#define LL_AdvReportCback _symrom_LL_AdvReportCback
#define ll_allocAuxAdvTimeSlot _symrom_ll_allocAuxAdvTimeSlot
#define ll_allocAuxAdvTimeSlot_prd _symrom_ll_allocAuxAdvTimeSlot_prd
#define ll_CalcRandomAddr _symrom_ll_CalcRandomAddr
#define LL_ChanMapUpdate _symrom_LL_ChanMapUpdate
#define LL_ClearAdvSets _symrom_LL_ClearAdvSets
#define LL_ClearResolvingList _symrom_LL_ClearResolvingList
#define LL_ClearWhiteList _symrom_LL_ClearWhiteList
#define LL_ConnActive _symrom_LL_ConnActive
#define LL_Connection_CTE_Request_Enable _symrom_LL_Connection_CTE_Request_Enable
#define LL_Connection_CTE_Response_Enable _symrom_LL_Connection_CTE_Response_Enable
#define LL_ConnectionCompleteCback _symrom_LL_ConnectionCompleteCback
#define LL_ConnectionIQReportCback _symrom_LL_ConnectionIQReportCback
#define LL_ConnectionlessCTE_TransmitEnable _symrom_LL_ConnectionlessCTE_TransmitEnable
#define LL_ConnectionlessCTE_TransmitParam _symrom_LL_ConnectionlessCTE_TransmitParam
#define LL_ConnectionlessIQ_SampleEnable _symrom_LL_ConnectionlessIQ_SampleEnable
#define LL_ConnectionlessIQReportCback _symrom_LL_ConnectionlessIQReportCback
#define LL_ConnParamUpdateCback _symrom_LL_ConnParamUpdateCback
#define LL_ConnUpdate _symrom_LL_ConnUpdate
#define LL_CreateConn _symrom_LL_CreateConn
#define LL_CreateConnCancel _symrom_LL_CreateConnCancel
#define LL_CTE_Report_FailedCback _symrom_LL_CTE_Report_FailedCback
#define LL_CtrlToHostFlowControl _symrom_LL_CtrlToHostFlowControl
#define LL_DataLengthChangeCback _symrom_LL_DataLengthChangeCback
#define ll_debug_output _symrom_ll_debug_output
#define ll_delete_adv_task _symrom_ll_delete_adv_task
#define ll_delete_adv_task_periodic _symrom_ll_delete_adv_task_periodic
#define ll_deleteTask _symrom_ll_deleteTask
#define LL_DirectTestEnd _symrom_LL_DirectTestEnd
#define LL_DirectTestTxTest _symrom_LL_DirectTestTxTest
#define LL_Disconnect _symrom_LL_Disconnect
#define LL_DisconnectCback _symrom_LL_DisconnectCback
#define LL_ENC_AES128_Encrypt _symrom_LL_ENC_AES128_Encrypt
#define LL_ENC_Decrypt _symrom_LL_ENC_Decrypt
#define LL_ENC_Encrypt _symrom_LL_ENC_Encrypt
#define LL_ENC_GenDeviceIV _symrom_LL_ENC_GenDeviceIV
#define LL_ENC_GenDeviceSKD _symrom_LL_ENC_GenDeviceSKD
#define LL_ENC_GenerateNonce _symrom_LL_ENC_GenerateNonce
#define LL_ENC_GeneratePseudoRandNum _symrom_LL_ENC_GeneratePseudoRandNum
#define LL_ENC_GenerateTrueRandNum _symrom_LL_ENC_GenerateTrueRandNum
#define LL_ENC_LoadKey _symrom_LL_ENC_LoadKey
#define LL_ENC_ReverseBytes _symrom_LL_ENC_ReverseBytes
#define LL_ENC_sm_ah _symrom_LL_ENC_sm_ah
#define LL_EncChangeCback _symrom_LL_EncChangeCback
#define LL_EncKeyRefreshCback _symrom_LL_EncKeyRefreshCback
#define LL_EncLtkNegReply _symrom_LL_EncLtkNegReply
#define LL_EncLtkReply _symrom_LL_EncLtkReply
#define LL_EncLtkReqCback _symrom_LL_EncLtkReqCback
#define LL_Encrypt _symrom_LL_Encrypt
#define LL_evt_schedule _symrom_LL_evt_schedule
#define ll_ext_adv_schedule_next_event _symrom_ll_ext_adv_schedule_next_event
#define LL_EXT_AdvEventNotice _symrom_LL_EXT_AdvEventNotice
#define LL_EXT_BuildRevision _symrom_LL_EXT_BuildRevision
#define LL_EXT_ClkDivOnHalt _symrom_LL_EXT_ClkDivOnHalt
#define LL_EXT_ConnEventNotice _symrom_LL_EXT_ConnEventNotice
#define LL_EXT_DeclareNvUsage _symrom_LL_EXT_DeclareNvUsage
#define LL_EXT_Decrypt _symrom_LL_EXT_Decrypt
#define LL_EXT_DelaySleep _symrom_LL_EXT_DelaySleep
#define LL_EXT_DisconnectImmed _symrom_LL_EXT_DisconnectImmed
#define LL_EXT_EndModemTest _symrom_LL_EXT_EndModemTest
#define LL_EXT_HaltDuringRf _symrom_LL_EXT_HaltDuringRf
#define LL_EXT_Init_IQ_pBuff _symrom_LL_EXT_Init_IQ_pBuff
#define ll_ext_init_schedule_next_event _symrom_ll_ext_init_schedule_next_event
#define LL_EXT_MapPmIoPort _symrom_LL_EXT_MapPmIoPort
#define LL_EXT_ModemHopTestTx _symrom_LL_EXT_ModemHopTestTx
#define LL_EXT_ModemTestRx _symrom_LL_EXT_ModemTestRx
#define LL_EXT_ModemTestTx _symrom_LL_EXT_ModemTestTx
#define LL_EXT_NumComplPktsLimit _symrom_LL_EXT_NumComplPktsLimit
#define LL_EXT_OnePacketPerEvent _symrom_LL_EXT_OnePacketPerEvent
#define LL_EXT_OverlappedProcessing _symrom_LL_EXT_OverlappedProcessing
#define LL_EXT_PacketErrorRate _symrom_LL_EXT_PacketErrorRate
#define LL_EXT_PERbyChan _symrom_LL_EXT_PERbyChan
#define LL_EXT_ResetSystem _symrom_LL_EXT_ResetSystem
#define LL_EXT_SaveFreqTune _symrom_LL_EXT_SaveFreqTune
#define ll_ext_scan_schedule_next_event _symrom_ll_ext_scan_schedule_next_event
#define LL_EXT_SetBDADDR _symrom_LL_EXT_SetBDADDR
#define LL_EXT_SetFastTxResponseTime _symrom_LL_EXT_SetFastTxResponseTime
#define LL_EXT_SetFreqTune _symrom_LL_EXT_SetFreqTune
#define LL_EXT_SetLocalSupportedFeatures _symrom_LL_EXT_SetLocalSupportedFeatures
#define LL_EXT_SetMaxDtmTxPower _symrom_LL_EXT_SetMaxDtmTxPower
#define LL_EXT_SetRxGain _symrom_LL_EXT_SetRxGain
#define LL_EXT_SetSCA _symrom_LL_EXT_SetSCA
#define LL_EXT_SetSlaveLatencyOverride _symrom_LL_EXT_SetSlaveLatencyOverride
#define LL_EXT_SetTxPower _symrom_LL_EXT_SetTxPower
#define LL_ExtAdvReportCback _symrom_LL_ExtAdvReportCback
#define LL_extAdvTimerExpProcess _symrom_LL_extAdvTimerExpProcess
#define LL_ExtendedCreateConnection _symrom_LL_ExtendedCreateConnection
#define LL_extInitTimerExpProcess _symrom_LL_extInitTimerExpProcess
#define LL_extScanTimerExpProcess _symrom_LL_extScanTimerExpProcess
#define ll_generateExtAdvDid _symrom_ll_generateExtAdvDid
#define ll_generateTxBuffer _symrom_ll_generateTxBuffer
#define ll_get_next_active_conn _symrom_ll_get_next_active_conn
#define ll_get_next_timer _symrom_ll_get_next_timer
#define ll_getFirstAdvChn _symrom_ll_getFirstAdvChn
#define ll_getRPAListEntry _symrom_ll_getRPAListEntry
#define ll_hw_clr_irq _symrom_ll_hw_clr_irq
#define ll_hw_config _symrom_ll_hw_config
#define ll_hw_get_anchor _symrom_ll_hw_get_anchor
#define ll_hw_get_fsm_status _symrom_ll_hw_get_fsm_status
#define ll_hw_get_iq_RawSample _symrom_ll_hw_get_iq_RawSample
#define ll_hw_get_irq_status _symrom_ll_hw_get_irq_status
#define ll_hw_get_last_ack _symrom_ll_hw_get_last_ack
#define ll_hw_get_loop_cycle _symrom_ll_hw_get_loop_cycle
#define ll_hw_get_loop_time _symrom_ll_hw_get_loop_time
#define ll_hw_get_nAck _symrom_ll_hw_get_nAck
#define ll_hw_get_rfifo_depth _symrom_ll_hw_get_rfifo_depth
#define ll_hw_get_rfifo_info _symrom_ll_hw_get_rfifo_info
#define ll_hw_get_rxPkt_CrcErr_num _symrom_ll_hw_get_rxPkt_CrcErr_num
#define ll_hw_get_rxPkt_CrcOk_num _symrom_ll_hw_get_rxPkt_CrcOk_num
#define ll_hw_get_rxPkt_num _symrom_ll_hw_get_rxPkt_num
#define ll_hw_get_rxPkt_stats _symrom_ll_hw_get_rxPkt_stats
#define ll_hw_get_rxPkt_Total_num _symrom_ll_hw_get_rxPkt_Total_num
#define ll_hw_get_snNesn _symrom_ll_hw_get_snNesn
#define ll_hw_get_tfifo_info _symrom_ll_hw_get_tfifo_info
#define ll_hw_get_tfifo_wrptr _symrom_ll_hw_get_tfifo_wrptr
#define ll_hw_get_tr_mode _symrom_ll_hw_get_tr_mode
#define ll_hw_get_txAck _symrom_ll_hw_get_txAck
#define ll_hw_go _symrom_ll_hw_go
#define ll_hw_ign_rfifo _symrom_ll_hw_ign_rfifo
#define ll_hw_process_RTO _symrom_ll_hw_process_RTO
#define ll_hw_read_rfifo _symrom_ll_hw_read_rfifo
#define ll_hw_read_rfifo_pplus _symrom_ll_hw_read_rfifo_pplus
#define ll_hw_read_rfifo_zb _symrom_ll_hw_read_rfifo_zb
#define ll_hw_read_tfifo_packet _symrom_ll_hw_read_tfifo_packet
#define ll_hw_read_tfifo_rtlp _symrom_ll_hw_read_tfifo_rtlp
#define ll_hw_rst_rfifo _symrom_ll_hw_rst_rfifo
#define ll_hw_rst_tfifo _symrom_ll_hw_rst_tfifo
#define ll_hw_set_ant_pattern _symrom_ll_hw_set_ant_pattern
#define ll_hw_set_ant_switch_mode _symrom_ll_hw_set_ant_switch_mode
#define ll_hw_set_ant_switch_timing _symrom_ll_hw_set_ant_switch_timing
#define ll_hw_set_crc_fmt _symrom_ll_hw_set_crc_fmt
#define ll_hw_set_cte_rxSupp _symrom_ll_hw_set_cte_rxSupp
#define ll_hw_set_cte_txSupp _symrom_ll_hw_set_cte_txSupp
#define ll_hw_set_empty_head _symrom_ll_hw_set_empty_head
#define ll_hw_set_irq _symrom_ll_hw_set_irq
#define ll_hw_set_loop_nack_num _symrom_ll_hw_set_loop_nack_num
#define ll_hw_set_loop_timeout _symrom_ll_hw_set_loop_timeout
#define ll_hw_set_pplus_pktfmt _symrom_ll_hw_set_pplus_pktfmt
#define ll_hw_set_rtlp _symrom_ll_hw_set_rtlp
#define ll_hw_set_rtlp_1st _symrom_ll_hw_set_rtlp_1st
#define ll_hw_set_rtx _symrom_ll_hw_set_rtx
#define ll_hw_set_rx_timeout _symrom_ll_hw_set_rx_timeout
#define ll_hw_set_rx_timeout_1st _symrom_ll_hw_set_rx_timeout_1st
#define ll_hw_set_rx_tx_interval _symrom_ll_hw_set_rx_tx_interval
#define ll_hw_set_srx _symrom_ll_hw_set_srx
#define ll_hw_set_stx _symrom_ll_hw_set_stx
#define ll_hw_set_tfifo_space _symrom_ll_hw_set_tfifo_space
#define ll_hw_set_timing _symrom_ll_hw_set_timing
#define ll_hw_set_trlp _symrom_ll_hw_set_trlp
#define ll_hw_set_trx _symrom_ll_hw_set_trx
#define ll_hw_set_trx_settle _symrom_ll_hw_set_trx_settle
#define ll_hw_set_tx_rx_interval _symrom_ll_hw_set_tx_rx_interval
#define ll_hw_set_tx_rx_release _symrom_ll_hw_set_tx_rx_release
#define ll_hw_trigger _symrom_ll_hw_trigger
#define ll_hw_trx_settle_config _symrom_ll_hw_trx_settle_config
#define ll_hw_tx2rx_timing_config _symrom_ll_hw_tx2rx_timing_config
#define ll_hw_update _symrom_ll_hw_update
#define ll_hw_update_rtlp_mode _symrom_ll_hw_update_rtlp_mode
#define ll_hw_update_trlp_mode _symrom_ll_hw_update_trlp_mode
#define ll_hw_write_tfifo _symrom_ll_hw_write_tfifo
#define LL_Init _symrom_LL_Init
#define LL_InitConnectContext _symrom_LL_InitConnectContext
#define LL_InitExtendedAdv _symrom_LL_InitExtendedAdv
#define LL_InitExtendedScan _symrom_LL_InitExtendedScan
#define LL_InitPeriodicAdv _symrom_LL_InitPeriodicAdv
#define LL_IRQHandler _symrom_LL_IRQHandler
#define ll_isAddrInWhiteList _symrom_ll_isAddrInWhiteList
#define ll_isFirstAdvChn _symrom_ll_isFirstAdvChn
#define LL_master_conn_event _symrom_LL_master_conn_event
#define LL_NumEmptyWlEntries _symrom_LL_NumEmptyWlEntries
#define ll_parseExtHeader _symrom_ll_parseExtHeader
#define LL_PeriodicAdvertisingCreateSync _symrom_LL_PeriodicAdvertisingCreateSync
#define LL_PeriodicAdvertisingCreateSyncCancel _symrom_LL_PeriodicAdvertisingCreateSyncCancel
#define LL_PeriodicAdvertisingTerminateSync _symrom_LL_PeriodicAdvertisingTerminateSync
#define LL_PhyUpdate _symrom_LL_PhyUpdate
#define LL_PhyUpdateCompleteCback _symrom_LL_PhyUpdateCompleteCback
#define LL_PLUS_AdvDataFilterCBack _symrom_LL_PLUS_AdvDataFilterCBack
#define LL_PLUS_DisableSlaveLatency _symrom_LL_PLUS_DisableSlaveLatency
#define LL_PLUS_EnableSlaveLatency _symrom_LL_PLUS_EnableSlaveLatency
#define LL_PLUS_GetAdvDataExtendData _symrom_LL_PLUS_GetAdvDataExtendData
#define LL_PLUS_GetScanerAddr _symrom_LL_PLUS_GetScanerAddr
#define LL_PLUS_GetScanRequestExtendData _symrom_LL_PLUS_GetScanRequestExtendData
#define LL_PLUS_PerStasReadByChn _symrom_LL_PLUS_PerStasReadByChn
#define LL_PLUS_PerStats_Init _symrom_LL_PLUS_PerStats_Init
#define LL_PLUS_PerStatsReset _symrom_LL_PLUS_PerStatsReset
#define LL_PLUS_ScanRequestFilterCBack _symrom_LL_PLUS_ScanRequestFilterCBack
#define LL_PLUS_SetAdvDataFilterCB _symrom_LL_PLUS_SetAdvDataFilterCB
#define LL_PLUS_SetScanRequestData _symrom_LL_PLUS_SetScanRequestData
#define LL_PLUS_SetScanRequestFilterCB _symrom_LL_PLUS_SetScanRequestFilterCB
#define LL_PLUS_SetScanRsqData _symrom_LL_PLUS_SetScanRsqData
#define LL_PLUS_SetScanRsqDataByIndex _symrom_LL_PLUS_SetScanRsqDataByIndex
#define ll_prd_adv_schedule_next_event _symrom_ll_prd_adv_schedule_next_event
#define ll_prd_scan_schedule_next_event _symrom_ll_prd_scan_schedule_next_event
#define LL_PrdAdvReportCback _symrom_LL_PrdAdvReportCback
#define LL_PrdAdvSyncEstablishedCback _symrom_LL_PrdAdvSyncEstablishedCback
#define LL_PrdAdvSyncLostCback _symrom_LL_PrdAdvSyncLostCback
#define LL_prdAdvTimerExpProcess _symrom_LL_prdAdvTimerExpProcess
#define LL_prdScanTimerExpProcess _symrom_LL_prdScanTimerExpProcess
#define ll_processBasicIRQ _symrom_ll_processBasicIRQ
#define LL_ProcessEvent _symrom_LL_ProcessEvent
#define ll_processExtAdvIRQ _symrom_ll_processExtAdvIRQ
#define ll_processExtInitIRQ _symrom_ll_processExtInitIRQ
#define ll_processExtScanIRQ _symrom_ll_processExtScanIRQ
#define ll_processMissMasterEvt _symrom_ll_processMissMasterEvt
#define ll_processMissSlaveEvt _symrom_ll_processMissSlaveEvt
#define ll_processPrdAdvIRQ _symrom_ll_processPrdAdvIRQ
#define ll_processPrdScanIRQ _symrom_ll_processPrdScanIRQ
#define LL_PseudoRand _symrom_LL_PseudoRand
#define LL_Rand _symrom_LL_Rand
#define LL_RandCback _symrom_LL_RandCback
#define LL_READ_Anatenna_Info _symrom_LL_READ_Anatenna_Info
#define ll_read_rxfifo _symrom_ll_read_rxfifo
#define LL_ReadAdvChanTxPower _symrom_LL_ReadAdvChanTxPower
#define LL_ReadBDADDR _symrom_LL_ReadBDADDR
#define LL_ReadCarrSens _symrom_LL_ReadCarrSens
#define LL_ReadChanMap _symrom_LL_ReadChanMap
#define LL_ReadFoff _symrom_LL_ReadFoff
#define ll_readLocalIRK _symrom_ll_readLocalIRK
#define LL_ReadLocalSupportedFeatures _symrom_LL_ReadLocalSupportedFeatures
#define LL_ReadLocalVersionInfo _symrom_LL_ReadLocalVersionInfo
#define LL_ReadMaximumAdvDataLength _symrom_LL_ReadMaximumAdvDataLength
#define LL_ReadNumberOfSupportAdvSet _symrom_LL_ReadNumberOfSupportAdvSet
#define LL_ReadRemoteUsedFeatures _symrom_LL_ReadRemoteUsedFeatures
#define LL_ReadRemoteUsedFeaturesCompleteCback _symrom_LL_ReadRemoteUsedFeaturesCompleteCback
#define LL_ReadRemoteVersionInfo _symrom_LL_ReadRemoteVersionInfo
#define LL_ReadRemoteVersionInfoCback _symrom_LL_ReadRemoteVersionInfoCback
#define LL_ReadResolvingListSize _symrom_LL_ReadResolvingListSize
#define LL_ReadRssi _symrom_LL_ReadRssi
#define LL_ReadSupportedStates _symrom_LL_ReadSupportedStates
#define LL_ReadTxPowerLevel _symrom_LL_ReadTxPowerLevel
#define LL_ReadWlSize _symrom_LL_ReadWlSize
#define ll_remain_time _symrom_ll_remain_time
#define LL_RemoveAdvSet _symrom_LL_RemoveAdvSet
#define LL_RemoveResolvingListDevice _symrom_LL_RemoveResolvingListDevice
#define LL_RemoveWhiteListDevice _symrom_LL_RemoveWhiteListDevice
#define LL_Reset _symrom_LL_Reset
#define ll_ResolveRandomAddrs _symrom_ll_ResolveRandomAddrs
#define LL_RX_bm_alloc _symrom_LL_RX_bm_alloc
#define LL_RxDataCompleteCback _symrom_LL_RxDataCompleteCback
#define ll_schedule_next_event _symrom_ll_schedule_next_event
#define ll_scheduler _symrom_ll_scheduler
#define LL_Set_ConnectionCTE_ReceiveParam _symrom_LL_Set_ConnectionCTE_ReceiveParam
#define LL_Set_ConnectionCTE_TransmitParam _symrom_LL_Set_ConnectionCTE_TransmitParam
#define LL_set_default_conn_params _symrom_LL_set_default_conn_params
#define LL_SetAddressResolutionEnable _symrom_LL_SetAddressResolutionEnable
#define LL_SetAdvControl _symrom_LL_SetAdvControl
#define LL_SetAdvData _symrom_LL_SetAdvData
#define LL_SetAdvParam _symrom_LL_SetAdvParam
#define LL_SetDataLengh _symrom_LL_SetDataLengh
#define LL_SetDefaultPhyMode _symrom_LL_SetDefaultPhyMode
#define LL_SetExtAdvData _symrom_LL_SetExtAdvData
#define LL_SetExtAdvEnable _symrom_LL_SetExtAdvEnable
#define LL_SetExtAdvParam _symrom_LL_SetExtAdvParam
#define LL_SetExtAdvSetRandomAddress _symrom_LL_SetExtAdvSetRandomAddress
#define LL_SetExtendedScanEnable _symrom_LL_SetExtendedScanEnable
#define LL_SetExtendedScanParameters _symrom_LL_SetExtendedScanParameters
#define LL_SetExtScanRspData _symrom_LL_SetExtScanRspData
#define LL_SetPeriodicAdvData _symrom_LL_SetPeriodicAdvData
#define LL_SetPeriodicAdvEnable _symrom_LL_SetPeriodicAdvEnable
#define LL_SetPeriodicAdvParameter _symrom_LL_SetPeriodicAdvParameter
#define LL_SetPhyMode _symrom_LL_SetPhyMode
#define LL_SetRandomAddress _symrom_LL_SetRandomAddress
#define LL_SetResolvablePrivateAddressTimeout _symrom_LL_SetResolvablePrivateAddressTimeout
#define LL_SetScanControl _symrom_LL_SetScanControl
#define LL_SetScanParam _symrom_LL_SetScanParam
#define LL_SetScanRspData _symrom_LL_SetScanRspData
#define LL_SetTxPowerLevel _symrom_LL_SetTxPowerLevel
#define LL_slave_conn_event _symrom_LL_slave_conn_event
#define LL_StartEncrypt _symrom_LL_StartEncrypt
#define LL_TaskID _symrom_LL_TaskID
#define LL_TX_bm_alloc _symrom_LL_TX_bm_alloc
#define LL_TxData _symrom_LL_TxData
#define ll_updateAuxAdvTimeSlot _symrom_ll_updateAuxAdvTimeSlot
#define ll_updateExtAdvRemainderTime _symrom_ll_updateExtAdvRemainderTime
#define LL_WriteSuggestedDefaultDataLength _symrom_LL_WriteSuggestedDefaultDataLength
#define ll24BitTimeCompare _symrom_ll24BitTimeCompare
#define llAdjSlaveLatencyValue _symrom_llAdjSlaveLatencyValue
#define llAllocateSyncHandle _symrom_llAllocateSyncHandle
#define llAllocConnId _symrom_llAllocConnId
#define llAtLeastTwoChans _symrom_llAtLeastTwoChans
#define llCalcMaxScanTime _symrom_llCalcMaxScanTime
#define llCalcScaFactor _symrom_llCalcScaFactor
#define llCalcTimerDrift _symrom_llCalcTimerDrift
#define llCheckForLstoDuringSL _symrom_llCheckForLstoDuringSL
#define llCheckWhiteListUsage _symrom_llCheckWhiteListUsage
#define llConnCleanup _symrom_llConnCleanup
#define llConnTerminate _symrom_llConnTerminate
#define llConvertCtrlProcTimeoutToEvent _symrom_llConvertCtrlProcTimeoutToEvent
#define llConvertLstoToEvent _symrom_llConvertLstoToEvent
#define llCurrentScanChn _symrom_llCurrentScanChn
#define llDeleteSyncHandle _symrom_llDeleteSyncHandle
#define llDequeueCtrlPkt _symrom_llDequeueCtrlPkt
#define llDequeueDataQ _symrom_llDequeueDataQ
#define llEnqueueCtrlPkt _symrom_llEnqueueCtrlPkt
#define llEnqueueDataQ _symrom_llEnqueueDataQ
#define llEqAlreadyValidAddr _symrom_llEqAlreadyValidAddr
#define llEqSynchWord _symrom_llEqSynchWord
#define llEqualBytes _symrom_llEqualBytes
#define llEventDelta _symrom_llEventDelta
#define llEventInRange _symrom_llEventInRange
#define llGenerateCRC _symrom_llGenerateCRC
#define llGenerateValidAccessAddr _symrom_llGenerateValidAccessAddr
#define llGetNextAdvChn _symrom_llGetNextAdvChn
#define llGetNextAuxAdvChn _symrom_llGetNextAuxAdvChn
#define llGetNextDataChan _symrom_llGetNextDataChan
#define llGetNextDataChanCSA2 _symrom_llGetNextDataChanCSA2
#define llGtSixConsecZerosOrOnes _symrom_llGtSixConsecZerosOrOnes
#define llGtTwentyFourTransitions _symrom_llGtTwentyFourTransitions
#define llInitFeatureSet _symrom_llInitFeatureSet
#define llInitFeatureSet2MPHY _symrom_llInitFeatureSet2MPHY
#define llInitFeatureSetCodedPHY _symrom_llInitFeatureSetCodedPHY
#define llInitFeatureSetDLE _symrom_llInitFeatureSetDLE
#define llLtTwoChangesInLastSixBits _symrom_llLtTwoChangesInLastSixBits
#define llMasterEvt_TaskEndOk _symrom_llMasterEvt_TaskEndOk
#define llMemCopyDst _symrom_llMemCopyDst
#define llMemCopySrc _symrom_llMemCopySrc
#define llOneBitSynchWordDiffer _symrom_llOneBitSynchWordDiffer
#define llPduLengthManagmentReset _symrom_llPduLengthManagmentReset
#define llPduLengthUpdate _symrom_llPduLengthUpdate
#define llPendingUpdateParam _symrom_llPendingUpdateParam
#define llPhyModeCtrlReset _symrom_llPhyModeCtrlReset
#define llPhyModeCtrlUpdateNotify _symrom_llPhyModeCtrlUpdateNotify
#define llProcessChanMap _symrom_llProcessChanMap
#define llProcessMasterControlPacket _symrom_llProcessMasterControlPacket
#define llProcessMasterControlProcedures _symrom_llProcessMasterControlProcedures
#define llProcessRxData _symrom_llProcessRxData
#define llProcessSlaveControlPacket _symrom_llProcessSlaveControlPacket
#define llProcessSlaveControlProcedures _symrom_llProcessSlaveControlProcedures
#define llProcessTxData _symrom_llProcessTxData
#define llReleaseAllConnId _symrom_llReleaseAllConnId
#define llReleaseConnId _symrom_llReleaseConnId
#define llReplaceCtrlPkt _symrom_llReplaceCtrlPkt
#define llResetConnId _symrom_llResetConnId
#define llResetRfCounters _symrom_llResetRfCounters
#define llScanT1 _symrom_llScanT1
#define llScanTime _symrom_llScanTime
#define llSecAdvAllow _symrom_llSecAdvAllow
#define llSecondaryState _symrom_llSecondaryState
#define llSetNextDataChan _symrom_llSetNextDataChan
#define llSetNextPhyMode _symrom_llSetNextPhyMode
#define llSetupAdv _symrom_llSetupAdv
#define llSetupAdvExtIndPDU _symrom_llSetupAdvExtIndPDU
#define llSetupAuxAdvIndPDU _symrom_llSetupAuxAdvIndPDU
#define llSetupAuxChainIndPDU _symrom_llSetupAuxChainIndPDU
#define llSetupAuxConnectReqPDU _symrom_llSetupAuxConnectReqPDU
#define llSetupAuxConnectRspPDU _symrom_llSetupAuxConnectRspPDU
#define llSetupAuxScanRspPDU _symrom_llSetupAuxScanRspPDU
#define llSetupAuxSyncIndPDU _symrom_llSetupAuxSyncIndPDU
#define llSetupConn _symrom_llSetupConn
#define llSetupCTEReq _symrom_llSetupCTEReq
#define llSetupCTERsp _symrom_llSetupCTERsp
#define llSetupDataLenghtReq _symrom_llSetupDataLenghtReq
#define llSetupDataLenghtRsp _symrom_llSetupDataLenghtRsp
#define llSetupDirectedAdvEvt _symrom_llSetupDirectedAdvEvt
#define llSetupEncReq _symrom_llSetupEncReq
#define llSetupEncRsp _symrom_llSetupEncRsp
#define llSetupExtAdvEvent _symrom_llSetupExtAdvEvent
#define llSetupExtInit _symrom_llSetupExtInit
#define llSetupExtScan _symrom_llSetupExtScan
#define llSetupFeatureSetReq _symrom_llSetupFeatureSetReq
#define llSetupFeatureSetRsp _symrom_llSetupFeatureSetRsp
#define llSetupInit _symrom_llSetupInit
#define llSetupNextMasterEvent _symrom_llSetupNextMasterEvent
#define llSetupNextSlaveEvent _symrom_llSetupNextSlaveEvent
#define llSetupNonConnectableAdvEvt _symrom_llSetupNonConnectableAdvEvt
#define llSetupPauseEncReq _symrom_llSetupPauseEncReq
#define llSetupPauseEncRsp _symrom_llSetupPauseEncRsp
#define llSetupPhyReq _symrom_llSetupPhyReq
#define llSetupPhyRsp _symrom_llSetupPhyRsp
#define llSetupPhyUpdateInd _symrom_llSetupPhyUpdateInd
#define llSetupPrdAdvEvent _symrom_llSetupPrdAdvEvent
#define llSetupPrdScan _symrom_llSetupPrdScan
#define llSetupRejectExtInd _symrom_llSetupRejectExtInd
#define llSetupRejectInd _symrom_llSetupRejectInd
#define llSetupScan _symrom_llSetupScan
#define llSetupScanInit _symrom_llSetupScanInit
#define llSetupScannableAdvEvt _symrom_llSetupScannableAdvEvt
#define llSetupSecAdvEvt _symrom_llSetupSecAdvEvt
#define llSetupSecConnectableAdvEvt _symrom_llSetupSecConnectableAdvEvt
#define llSetupSecInit _symrom_llSetupSecInit
#define llSetupSecNonConnectableAdvEvt _symrom_llSetupSecNonConnectableAdvEvt
#define llSetupSecScan _symrom_llSetupSecScan
#define llSetupSecScannableAdvEvt _symrom_llSetupSecScannableAdvEvt
#define llSetupStartEncReq _symrom_llSetupStartEncReq
#define llSetupStartEncRsp _symrom_llSetupStartEncRsp
#define llSetupSyncInfo _symrom_llSetupSyncInfo
#define llSetupTermInd _symrom_llSetupTermInd
#define llSetupUndirectedAdvEvt _symrom_llSetupUndirectedAdvEvt
#define llSetupUnknownRsp _symrom_llSetupUnknownRsp
#define llSetupUpdateChanReq _symrom_llSetupUpdateChanReq
#define llSetupUpdateParamReq _symrom_llSetupUpdateParamReq
#define llSetupVersionIndReq _symrom_llSetupVersionIndReq
#define llSlaveEvt_TaskAbort _symrom_llSlaveEvt_TaskAbort
#define llSlaveEvt_TaskEndOk _symrom_llSlaveEvt_TaskEndOk
#define llState _symrom_llState
#define llTaskState _symrom_llTaskState
#define llTrxNumAdaptiveConfig _symrom_llTrxNumAdaptiveConfig
#define llValidAccessAddr _symrom_llValidAccessAddr
#define llWaitingIrq _symrom_llWaitingIrq
#define llWaitUs _symrom_llWaitUs
#define llWriteTxData _symrom_llWriteTxData
#define log_clr_putc _symrom_log_clr_putc
#define log_debug_level _symrom_log_debug_level
#define log_get_debug_level _symrom_log_get_debug_level
#define log_printf _symrom_log_printf
#define log_set_putc _symrom_log_set_putc
#define log_vsprintf _symrom_log_vsprintf
#define move_to_master_function _symrom_move_to_master_function
#define move_to_slave_function _symrom_move_to_slave_function
#define NMI_Handler _symrom_NMI_Handler
#define numComplPkts _symrom_numComplPkts
#define numComplPktsLimit _symrom_numComplPktsLimit
#define numHostBufs _symrom_numHostBufs
#define osal_bm_adjust_header _symrom_osal_bm_adjust_header
#define osal_bm_adjust_tail _symrom_osal_bm_adjust_tail
#define osal_bm_alloc _symrom_osal_bm_alloc
#define osal_bm_free _symrom_osal_bm_free
#define osal_buffer_uint24 _symrom_osal_buffer_uint24
#define osal_buffer_uint32 _symrom_osal_buffer_uint32
#define osal_build_uint16 _symrom_osal_build_uint16
#define osal_build_uint32 _symrom_osal_build_uint32
#define osal_CbTimerInit _symrom_osal_CbTimerInit
#define osal_CbTimerProcessEvent _symrom_osal_CbTimerProcessEvent
#define osal_CbTimerStart _symrom_osal_CbTimerStart
#define osal_CbTimerStop _symrom_osal_CbTimerStop
#define osal_CbTimerUpdate _symrom_osal_CbTimerUpdate
#define osal_clear_event _symrom_osal_clear_event
#define osal_ConvertUTCSecs _symrom_osal_ConvertUTCSecs
#define osal_ConvertUTCTime _symrom_osal_ConvertUTCTime
#define osal_get_timeoutEx _symrom_osal_get_timeoutEx
#define osal_getClock _symrom_osal_getClock
#define osal_GetSystemClock _symrom_osal_GetSystemClock
#define osal_init_system _symrom_osal_init_system
#define osal_isbufset _symrom_osal_isbufset
#define osal_mem_alloc _symrom_osal_mem_alloc
#define osal_mem_free _symrom_osal_mem_free
#define osal_mem_init _symrom_osal_mem_init
#define osal_mem_kick _symrom_osal_mem_kick
#define osal_mem_set_heap _symrom_osal_mem_set_heap
#define osal_memcmp _symrom_osal_memcmp
#define osal_memcpy _symrom_osal_memcpy
#define osal_memdup _symrom_osal_memdup
#define osal_memset _symrom_osal_memset
#define osal_msg_allocate _symrom_osal_msg_allocate
#define osal_msg_deallocate _symrom_osal_msg_deallocate
#define osal_msg_dequeue _symrom_osal_msg_dequeue
#define osal_msg_enqueue _symrom_osal_msg_enqueue
#define osal_msg_enqueue_max _symrom_osal_msg_enqueue_max
#define osal_msg_extract _symrom_osal_msg_extract
#define osal_msg_find _symrom_osal_msg_find
#define osal_msg_push _symrom_osal_msg_push
#define osal_msg_push_front _symrom_osal_msg_push_front
#define osal_msg_receive _symrom_osal_msg_receive
#define osal_msg_send _symrom_osal_msg_send
#define osal_next_timeout _symrom_osal_next_timeout
#define osal_pwrmgr_device _symrom_osal_pwrmgr_device
#define osal_pwrmgr_init _symrom_osal_pwrmgr_init
#define osal_pwrmgr_powerconserve _symrom_osal_pwrmgr_powerconserve
#define osal_pwrmgr_task_state _symrom_osal_pwrmgr_task_state
#define osal_qHead _symrom_osal_qHead
#define osal_rand _symrom_osal_rand
#define osal_revmemcpy _symrom_osal_revmemcpy
#define osal_run_system _symrom_osal_run_system
#define osal_self _symrom_osal_self
#define osal_set_event _symrom_osal_set_event
#define osal_setClock _symrom_osal_setClock
#define osal_start_reload_timer _symrom_osal_start_reload_timer
#define osal_start_system _symrom_osal_start_system
#define osal_start_timerEx _symrom_osal_start_timerEx
#define osal_stop_timerEx _symrom_osal_stop_timerEx
#define osal_strlen _symrom_osal_strlen
#define osal_sys_tick _symrom_osal_sys_tick
#define osal_timer_num_active _symrom_osal_timer_num_active
#define OSAL_timeSeconds _symrom_OSAL_timeSeconds
#define osalAddTimer _symrom_osalAddTimer
#define osalDeleteTimer _symrom_osalDeleteTimer
#define osalFindTimer _symrom_osalFindTimer
#define osalTimerInit _symrom_osalTimerInit
#define osalTimerUpdate _symrom_osalTimerUpdate
#define osalTimeUpdate _symrom_osalTimeUpdate
#define osalTimeUpdate1 _symrom_osalTimeUpdate1
#define ownPublicAddr _symrom_ownPublicAddr
#define p_perStatsByChan _symrom_p_perStatsByChan
#define peerInfo _symrom_peerInfo
#define PendSV_Handler _symrom_PendSV_Handler
#define pHciEvtMask _symrom_pHciEvtMask
#define phy_sec_app_key _symrom_phy_sec_app_key
#define phy_sec_decrypt _symrom_phy_sec_decrypt
#define phy_sec_efuse_lock _symrom_phy_sec_efuse_lock
#define phy_sec_encrypt _symrom_phy_sec_encrypt
#define phy_sec_init _symrom_phy_sec_init
#define phy_sec_key_valid _symrom_phy_sec_key_valid
#define prog_process_data _symrom_prog_process_data
#define prog_uart_command _symrom_prog_uart_command
#define prog_uart_fct_command _symrom_prog_uart_fct_command
#define prog_uart_handle _symrom_prog_uart_handle
#define pwrmgr_attribute _symrom_pwrmgr_attribute
#define read_current_fine_time _symrom_read_current_fine_time
#define read_ll_adv_remainder_time _symrom_read_ll_adv_remainder_time
#define read_LL_remainder_time _symrom_read_LL_remainder_time
#define receive_timeout_flag _symrom_receive_timeout_flag
#define reset_conn_buf _symrom_reset_conn_buf
//#define rf_calibrate _symrom_rf_calibrate
//#define rf_init _symrom_rf_init
//#define rf_phy_ana_cfg _symrom_rf_phy_ana_cfg
//#define rf_phy_bb_cfg _symrom_rf_phy_bb_cfg
//#define rf_phy_change_cfg _symrom_rf_phy_change_cfg
//#define rf_phy_direct_test_ate _symrom_rf_phy_direct_test_ate
//#define rf_phy_get_pktFoot _symrom_rf_phy_get_pktFoot
//#define rf_phy_ini _symrom_rf_phy_ini
//#define rf_phy_set_txPower _symrom_rf_phy_set_txPower
//#define rf_rxDcoc_cfg _symrom_rf_rxDcoc_cfg
//#define rf_tp_cal _symrom_rf_tp_cal
//#define rf_tpCal_cfg _symrom_rf_tpCal_cfg
//#define rf_tpCal_cfg_avg _symrom_rf_tpCal_cfg_avg
//#define rf_tpCal_gen_cap_arrary _symrom_rf_tpCal_gen_cap_arrary
#define rfCounters _symrom_rfCounters
#define rom_board_init _symrom_rom_board_init
#define rtc_clear _symrom_rtc_clear
#define rtc_config_prescale _symrom_rtc_config_prescale
#define rtc_get_counter _symrom_rtc_get_counter
#define rtc_mod_value _symrom_rtc_mod_value
#define rtc_start _symrom_rtc_start
#define rtc_stop _symrom_rtc_stop
#define rxFifoFlowCtrl _symrom_rxFifoFlowCtrl
#define s_prog_time_save _symrom_s_prog_time_save
#define s_prog_timeout _symrom_s_prog_timeout
#define s_rom_debug_level _symrom_s_rom_debug_level
#define s_spif_ctx _symrom_s_spif_ctx
#define SCA _symrom_SCA
#define scanInfo _symrom_scanInfo
#define scanSyncInfo _symrom_scanSyncInfo
#define set_access_address _symrom_set_access_address
#define set_channel _symrom_set_channel
#define set_crc_seed _symrom_set_crc_seed
#define set_gpio_pull_down_ate _symrom_set_gpio_pull_down_ate
#define set_gpio_pull_up_ate _symrom_set_gpio_pull_up_ate
#define set_int _symrom_set_int
#define set_max_length _symrom_set_max_length
#define set_sleep_flag _symrom_set_sleep_flag
#define set_timer _symrom_set_timer
#define set_whiten_seed _symrom_set_whiten_seed
#define setSleepMode _symrom_setSleepMode
#define slave_conn_event_recv_delay _symrom_slave_conn_event_recv_delay
#define sleep_flag _symrom_sleep_flag
#define spif_cmd _symrom_spif_cmd
#define spif_erase_all _symrom_spif_erase_all
#define spif_erase_block64 _symrom_spif_erase_block64
#define spif_erase_chip _symrom_spif_erase_chip
#define spif_erase_sector _symrom_spif_erase_sector
#define spif_flash_size _symrom_spif_flash_size
#define spif_flash_status_reg_0 _symrom_spif_flash_status_reg_0
#define spif_flash_status_reg_1 _symrom_spif_flash_status_reg_1
#define spif_init _symrom_spif_init
#define spif_rddata _symrom_spif_rddata
#define spif_read _symrom_spif_read
#define spif_release_deep_sleep _symrom_spif_release_deep_sleep
#define spif_set_deep_sleep _symrom_spif_set_deep_sleep
#define spif_wrdata _symrom_spif_wrdata
#define spif_write _symrom_spif_write
#define spif_write_protect _symrom_spif_write_protect
#define sram_ret_patch _symrom_sram_ret_patch
#define supportedCmdsTable _symrom_supportedCmdsTable
#define syncInfo _symrom_syncInfo
#define timerHead _symrom_timerHead
#define tx_scanRsp_desc _symrom_tx_scanRsp_desc
#define update_rx_read_ptr _symrom_update_rx_read_ptr
#define update_rx_write_ptr _symrom_update_rx_write_ptr
#define update_tx_read_ptr _symrom_update_tx_read_ptr
#define update_tx_write_ptr _symrom_update_tx_write_ptr
#define verInfo _symrom_verInfo
#define WaitRTCCount _symrom_WaitRTCCount
#define wakeup_init _symrom_wakeup_init
#define wakeup_init0 _symrom_wakeup_init0
#define wakeupProcess _symrom_wakeupProcess
#define whiten_seed _symrom_whiten_seed
#define zigbee_crc16_gen _symrom_zigbee_crc16_gen
#define WaitUs _symrom_WaitUs
#endif
#endif

59
ota_boot/source/ota_boot.h Normal file
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@ -0,0 +1,59 @@
/******************************************************************************
* @file ota_boot.h
*
******************************************************************************/
#ifndef OTA_BOOT_H_
#define OTA_BOOT_H_
/* FLASH */
#ifndef FLASH_SIZE
#define FLASH_SIZE 0x80000 // 512k (512*1024)
#endif
#define FLASH_MAX_SIZE 0x200000 // 2M (2048*1024)
#ifndef FLASH_SECTOR_SIZE
#define FLASH_SECTOR_SIZE 0x01000 // 4k (4*1024)
#endif
#define FADDR_START_ADDR (0x11000000)
#define FADDR_BOOT_ROM_INFO (FADDR_START_ADDR + 0x02000) // 4k
#define FADDR_OTA_SEC (FADDR_START_ADDR + 0x03000) // 52k
#define FADDR_APP_SEC (FADDR_START_ADDR + 0x10000) // 176k (for 256k Flash)
#define START_UP_FLAG 0x36594850 // "PHY6"
#define OTA_MODE_SELECT_REG 0x4000f034
//#define OTA_MODE_SELECT_REG (AP_AON->RTCCC2) // [0x4000f034] == 0x55 -> OTA
#define BOOT_FLG_OTA 0x55 // перезагрузка в FW Boot для OTA (ожидание соединения 80 сек)
#define BOOT_FLG_FW0 0x33 // перезагрузка в FW Boot
typedef enum _SYSCLK_SEL
{
SYS_CLK_RC_32M = 0,
SYS_CLK_DBL_32M = 1,
SYS_CLK_XTAL_16M = 2,
SYS_CLK_DLL_48M = 3,
SYS_CLK_DLL_64M = 4,
SYS_CLK_DLL_96M = 5,
SYS_CLK_8M = 6,
SYS_CLK_4M = 7,
SYS_CLK_NUM = 8,
} sysclk_t;
extern sysclk_t g_system_clk;
int _spif_wait_nobusy(uint8_t flg, uint32_t tout_ns);
int spif_write(uint32_t addr, uint8_t* data, uint32_t size);
int spif_write_dma(uint32_t addr, uint8_t* data, uint32_t size);
int spif_read(uint32_t addr, uint8_t* data, uint32_t size);
int spif_read_dma(uint32_t addr, uint8_t* data, uint32_t size);
int spif_erase_sector(unsigned int addr);
int spif_erase_block64(unsigned int addr);
int spif_erase_all(void);
uint8_t spif_flash_status_reg_0(void);
int spif_write_protect(bool en);
void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy);
void spif_rddata(uint8_t* data, uint8_t len);
int spif_config(sysclk_t ref_clk, uint8_t div, uint32_t rd_instr, uint8_t mode_bit, uint8_t QE);
#endif /* OTA_BOOT_H_ */

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rdwr_phy62x2.py
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@ -459,7 +459,7 @@ class phyflasher:
def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, raddr = DEF_START_WR_FLASH_ADDR):
if len(hp) > 1:
hexf = bytearray(b'\xff')*(0x100)
hexf[0:4] = int.to_bytes(len(hp), 4, byteorder='little')
hexf[0:4] = int.to_bytes(len(hp)-1, 4, byteorder='little')
hexf[8:12] = int.to_bytes(start, 4, byteorder='little')
#sections = 0
faddr_min = MAX_FLASH_SIZE-1
@ -592,8 +592,6 @@ def main():
print ('Error Flash read Unique ID!')
sys.exit(3)
print ('Flash Serial Number:', rb.hex()) # Unique ID
exit(0)
if args.operation == 'rc':
#filename = "r%08x-%08x.bin" % (addr, length)
if args.size == 0:

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