diff --git a/README.md b/README.md index 98e3a8c..d6bab26 100644 --- a/README.md +++ b/README.md @@ -21,6 +21,10 @@ Custom firmware for Tuya devices on the PHY622x2 chipset | [TH05_V1.3](https://pvvx.github.io/TH05-v1.3) | BOOT_TH05D_v14.hex | TH05D_v14.bin | RSH-TH05-V1.3 с чипом BL55072 | | [TH05F](https://pvvx.github.io/TH05F) | BOOT_TH05F_v14.hex | TH05F_v14.bin | TH05Y_V1.1, TH05Y_V1.2 с чипом QD01 2332 NT | +Основные файлы прошивок, BOOT_xxx_vxx.hex для программирования через USB-COM адаптер и xxx_vxx.bin для OTA, находятся в директории [bin](https://github.com/pvvx/THB2/tree/master/bin). + +Файлы для обновления Boot по OTA находятся в директории [update_boot](https://github.com/pvvx/THB2/tree/master/update_boot). Если boot работает нормально, то обновлять на новую версию не требуется. О необходимости замены будет объявлено дополнительно. Актуальная версия boot - v1.4. + ## Основные характеристики ! _При настройках по умолчанию_ ! @@ -44,11 +48,11 @@ Custom firmware for Tuya devices on the PHY622x2 chipset | 1.1 | Добавлен триггер - вывод TX2 срабатывающий по установленным значениям температуры и/или влажности с гистерезисами. Передача состояния вывода RX2 при connect. Для термометров с экраном добавлен показ смайлика с "комфортом". Дополнены: изменение имени и MAC устройства. | | 1.2 | Обработка и передача событий open/close со счетчиком с вывода маркированного "RX2" (для THB2 - "RX1"). | | 1.3 | Добавлен THB1 и TH05V1.3. Следующий этап уменьшения потребления для версий с LCD дисплеем и опция отключения дисплея. | -| 1.4 | Стабилизация соединения для всех вариантов устройств. Добавлен [TH05F](https://pvvx.github.io/TH05F). Коррекция хода RTC. Изменено BLE имя для TH05_V1.3 на "TH05D" | +| 1.4 | Стабилизация соединения для всех вариантов устройств. Добавлен [TH05F](https://pvvx.github.io/TH05F). Коррекция хода RTC. Изменено BLE имя для TH05_V1.3 на "TH05D". Добавлены файлы для обновления Boot по OTA. | ## Прошивка -Прошить устройство програмой Boot-OTA возможно через USB-COM адаптер с выходами на 3.3В: +Прошить устройство програмой Boot возможно через USB-COM адаптер с выходами на 3.3В: 1. Соединить GND, TX, RX, RTS–RESET, VCC (+3.3B). @@ -60,7 +64,7 @@ Custom firmware for Tuya devices on the PHY622x2 chipset | RX | TX1 | | RTS | RESET | -Если на адаптере отсутствует RST пин, во время запуска скрипта следует подключить RESET пин до GND (вомзожно потребуется несколько попыток) +Если на адаптере отсутствует RST пин, тогда следует замкнуть вывод RESET с GND(-Vbat) и быстро разомкнуть при старте скрипта (вомзожно потребуется несколько попыток) Название контактов на устройстве смотреть в описании по ссылкам: [THB1](https://pvvx.github.io/THB1), [THB2](https://pvvx.github.io/THB2), [BTH01](https://pvvx.github.io/BTH01/), [TH05_V1.3](https://pvvx.github.io/TH05-v1.3), [TH05_V1.4](https://pvvx.github.io/TH-05) @@ -70,21 +74,23 @@ Custom firmware for Tuya devices on the PHY622x2 chipset pip3 install -r requirements.txt ``` -3. Запустить: +3. Скачать необходимый для конкретного устройства файл BOOT_xxx_vxx.hex из директории bin. + +4. Запустить: ```txt python3 rdwr_phy62x2.py -p COM11 -e -r wh BOOT_xxx_vxx.hex ``` -4. Прошивка Boot-OTA завершена. Устройство работает. Адаптер можно отсоединить. +5. Прошивка Boot завершена. Устройство работает. Адаптер можно отсоединить. -5. Загружаем полную версию прошивки по OTA. Для этого: +6. Загружаем полную версию прошивки по OTA. Для этого: 1. Подаем питание на датчик (устройство). 2. Переходим на [PHY62x2BTHome.html](https://pvvx.github.io/THB2/web/PHY62x2BTHome.html). - 3. Жмем кнопку `Cоединение`, ищем устройство, подключаемся. + 3. Жмем кнопку `Соединение`, ищем устройство, подключаемся. 4. После подключение переходим на вкладку `OTA`, выбираем необходимую прошивку и жмем `Старт`. -6. Устройство должно перезагрузиться и быть готово для использования. +7. Устройство должно перезагрузиться и быть готово для использования. Дополнительно: @@ -92,6 +98,11 @@ python3 rdwr_phy62x2.py -p COM11 -e -r wh BOOT_xxx_vxx.hex * Для предварительного стирания рабочей области Flash используйте опцию `-e`. +* С помощью USB-COM адаптера возможно сразу дописать основную прошивку (APP) +``` +python3 rdwr_phy62x2.py -p COM11 -r we 0x10000 xxx_vxx.bin +``` + ## Сохранение оригинальной прошивки 1. Соединить GND, TX, RX, RTS–RESET, VCC (+3.3B). diff --git a/bin/BTH01_v14.bin b/bin/BTH01_v14.bin index f81ecaa..19b6cdd 100644 Binary files a/bin/BTH01_v14.bin and b/bin/BTH01_v14.bin differ diff --git a/bin/TH05D_v14.bin b/bin/TH05D_v14.bin index 8c55569..50dcdf5 100644 Binary files a/bin/TH05D_v14.bin and b/bin/TH05D_v14.bin differ diff --git a/bin/TH05F_v14.bin b/bin/TH05F_v14.bin index 894469c..5545ce2 100644 Binary files a/bin/TH05F_v14.bin and b/bin/TH05F_v14.bin differ diff --git a/bin/TH05_v14.bin b/bin/TH05_v14.bin index 5f61923..b7f96ee 100644 Binary files a/bin/TH05_v14.bin and b/bin/TH05_v14.bin differ diff --git a/bin/THB1_v14.bin b/bin/THB1_v14.bin index 26ad6c7..5626ede 100644 Binary files a/bin/THB1_v14.bin and b/bin/THB1_v14.bin differ diff --git a/bin/THB2_v14.bin b/bin/THB2_v14.bin index 915d7a2..943a0b7 100644 Binary files a/bin/THB2_v14.bin and b/bin/THB2_v14.bin differ diff --git a/bthome_phy6222/.gitignore b/bthome_phy6222/.gitignore index 2ad3804..2c69bbe 100644 --- a/bthome_phy6222/.gitignore +++ b/bthome_phy6222/.gitignore @@ -1,3 +1,5 @@ +bin +boot Listings Objects TestTHB2.asm diff --git a/bthome_phy6222/Makefile b/bthome_phy6222/Makefile index e315da9..6d0023d 100644 --- a/bthome_phy6222/Makefile +++ b/bthome_phy6222/Makefile @@ -117,11 +117,13 @@ CFLAGS += -Wl,--gc-sections ifdef BOOT_OTA LDSCRIPT ?= $(SDK_PATH)/misc/boot_ota_phy62x2.ld DEFINES += -DOTA_TYPE=OTA_TYPE_BOOT -BIN_OTA = +BIN_OTA = $(OBJ_DIR)/$(PROJECT_NAME).bin +ADD_OPT = -w 0x2F00 -f ota_upboot.add else LDSCRIPT ?= $(SDK_PATH)/misc/phy6222.ld DEFINES += -DOTA_TYPE=OTA_TYPE_NONE BIN_OTA = $(OBJ_DIR)/$(PROJECT_NAME).bin +ADD_OPT = endif LDFLAGS := $(ARCH_FLAGS) @@ -279,7 +281,7 @@ all: directory $(SRC_O) $(OBJ_DIR)/$(PROJECT_NAME).elf $(OBJ_DIR)/$(PROJECT_NAME %.bin: %.hex @echo Make: $@ - @$(PYTHON) ./phy62x2_ota.py $(OBJ_DIR)/$(PROJECT_NAME).hex + @$(PYTHON) ./phy62x2_ota.py $(ADD_OPT) $(OBJ_DIR)/$(PROJECT_NAME).hex %.asm: %.elf @echo OBJDUMP: $@ @@ -301,7 +303,7 @@ flash: @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex flash_ota: - @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r we 0x10000 $(OBJ_DIR)/$(PROJECT_NAME).bin + @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r we 0x10000 $(BIN_OTA) erase_and_flash: @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -e -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex diff --git a/bthome_phy6222/SDK/components/driver/flash/flash.c b/bthome_phy6222/SDK/components/driver/flash/flash.c index b3564cb..da80889 100644 --- a/bthome_phy6222/SDK/components/driver/flash/flash.c +++ b/bthome_phy6222/SDK/components/driver/flash/flash.c @@ -49,6 +49,29 @@ static xflash_Ctx_t s_xflashCtx = { .spif_ref_clk = SYS_CLK_DLL_64M, .rd_instr = XFRD_FCMD_READ_DUAL }; +/* +void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy) +{ + uint32_t temp = op << 0x18; + if (addrlen != 0) { + temp = temp | 0x80000 | addrlen * 0x10000 - 0x10000; + } + if (rdlen != 0) { + temp = temp | 0x800000 | rdlen * 0x100000 - 0x100000; + } + if (wrlen != 0) { + temp = temp | 0x8000 | wrlen * 0x1000 - 0x1000; + } + if (mbit != 0) { + temp = temp | 0x40000; + } + if (dummy != 0) { + temp = temp | dummy << 7; + } + AP_SPIF->fcmd = temp | 1; + ... +} +*/ __ATTR_SECTION_SRAM__ static inline uint32_t spif_lock() { HAL_ENTER_CRITICAL_SECTION(); diff --git a/bthome_phy6222/SDK/misc/ota_app_phy62x2.ld b/bthome_phy6222/SDK/misc/ota_app_phy62x2.ld index f5bde2c..d64a7ec 100644 --- a/bthome_phy6222/SDK/misc/ota_app_phy62x2.ld +++ b/bthome_phy6222/SDK/misc/ota_app_phy62x2.ld @@ -46,18 +46,7 @@ SECTIONS *.o(_section_standby_code_) *.o(_section_sram_code_) - *patch.o(.text.*) - *patch_ext_adv.o(.text.*) - - *rf_phy_driver.o(.text.*) - *pwrmgr.o(.text .text.*) - *timer.o(.text .text.*) - - *flash.o(.text .text.*) - *clock.o(.text.*) - - *phy_sec_ext.o(.text .text.*) - + *main.o(.text.*) *libgcc.a:*.o(.text .text.*) _etextram = ABSOLUTE(.); diff --git a/bthome_phy6222/bin/BTH01_v14.bin b/bthome_phy6222/bin/BTH01_v14.bin index f81ecaa..19b6cdd 100644 Binary files a/bthome_phy6222/bin/BTH01_v14.bin and b/bthome_phy6222/bin/BTH01_v14.bin differ diff --git a/bthome_phy6222/bin/TH05D_v14.bin b/bthome_phy6222/bin/TH05D_v14.bin index 8c55569..50dcdf5 100644 Binary files a/bthome_phy6222/bin/TH05D_v14.bin and b/bthome_phy6222/bin/TH05D_v14.bin differ diff --git a/bthome_phy6222/bin/TH05F_v14.bin b/bthome_phy6222/bin/TH05F_v14.bin index 894469c..5545ce2 100644 Binary files a/bthome_phy6222/bin/TH05F_v14.bin and b/bthome_phy6222/bin/TH05F_v14.bin differ diff --git a/bthome_phy6222/bin/TH05_v14.bin b/bthome_phy6222/bin/TH05_v14.bin index 5f61923..b7f96ee 100644 Binary files a/bthome_phy6222/bin/TH05_v14.bin and b/bthome_phy6222/bin/TH05_v14.bin differ diff --git a/bthome_phy6222/bin/THB1_v14.bin b/bthome_phy6222/bin/THB1_v14.bin index 26ad6c7..5626ede 100644 Binary files a/bthome_phy6222/bin/THB1_v14.bin and b/bthome_phy6222/bin/THB1_v14.bin differ diff --git a/bthome_phy6222/bin/THB2_v14.bin b/bthome_phy6222/bin/THB2_v14.bin index 915d7a2..943a0b7 100644 Binary files a/bthome_phy6222/bin/THB2_v14.bin and b/bthome_phy6222/bin/THB2_v14.bin differ diff --git a/bthome_phy6222/mk_windows.cmd b/bthome_phy6222/mk_windows.cmd index e4c68a7..926ac78 100644 --- a/bthome_phy6222/mk_windows.cmd +++ b/bthome_phy6222/mk_windows.cmd @@ -3,6 +3,7 @@ @del /Q "build\THB2%SWVER%.hex" @del /Q "build\THB2%SWVER%.bin" @mkdir .\bin +@mkdir .\boot @make -s clean @make -s -j PROJECT_NAME=THB2%SWVER% POJECT_DEF="-DDEVICE=DEVICE_THB2" @if not exist "build\THB2%SWVER%.hex" goto :error @@ -48,36 +49,42 @@ @make -s -j PROJECT_NAME=BOOT_THB2%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_THB2" @if not exist "build\BOOT_THB2%SWVER%.hex" goto :error @copy "build\BOOT_THB2%SWVER%.hex" .\bin +@copy "build\BOOT_THB2%SWVER%.bin" .\boot @ @del /Q "build\BOOT_BTH01%SWVER%.hex" @make -s clean @make -s -j PROJECT_NAME=BOOT_BTH01%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_BTH01" @if not exist "build\BOOT_BTH01%SWVER%.hex" goto :error @copy "build\BOOT_BTH01%SWVER%.hex" .\bin +@copy "build\BOOT_BTH01%SWVER%.bin" .\boot @ @del /Q "build\BOOT_TH05%SWVER%.hex" @make -s clean @make -s -j PROJECT_NAME=BOOT_TH05%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_TH05" @if not exist "build\BOOT_TH05%SWVER%.hex" goto :error @copy "build\BOOT_TH05%SWVER%.hex" .\bin +@copy "build\BOOT_TH05%SWVER%.bin" .\boot @ @del /Q "build\BOOT_TH05D%SWVER%.hex" @make -s clean @make -s -j PROJECT_NAME=BOOT_TH05D%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_TH05D" @if not exist "build\BOOT_TH05D%SWVER%.hex" goto :error @copy "build\BOOT_TH05D%SWVER%.hex" .\bin +@copy "build\BOOT_TH05D%SWVER%.bin" .\boot @ @del /Q "build\BOOT_TH05F%SWVER%.hex" @make -s clean @make -s -j PROJECT_NAME=BOOT_TH05F%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_TH05F" @if not exist "build\BOOT_TH05F%SWVER%.hex" goto :error @copy "build\BOOT_TH05F%SWVER%.hex" .\bin +@copy "build\BOOT_TH05F%SWVER%.bin" .\boot @ @del /Q "build\BOOT_THB1%SWVER%.hex" @make -s clean @make -s -j PROJECT_NAME=BOOT_THB1%SWVER% BOOT_OTA=1 POJECT_DEF="-DDEVICE=DEVICE_THB1" @if not exist "build\BOOT_THB1%SWVER%.hex" goto :error @copy "build\BOOT_THB1%SWVER%.hex" .\bin +@copy "build\BOOT_THB1%SWVER%.bin" .\boot @exit :error @echo "Error!" \ No newline at end of file diff --git a/bthome_phy6222/ota_upboot.add b/bthome_phy6222/ota_upboot.add new file mode 100644 index 0000000..ce77bf4 Binary files /dev/null and b/bthome_phy6222/ota_upboot.add differ diff --git a/bthome_phy6222/phy62x2_ota.py b/bthome_phy6222/phy62x2_ota.py index d40f6f8..baf4c4c 100644 --- a/bthome_phy6222/phy62x2_ota.py +++ b/bthome_phy6222/phy62x2_ota.py @@ -23,7 +23,7 @@ PHY_WR_BLK_SIZE = 0x2000 __progname__ = 'PHY62x2 OTA Utility' __filename__ = 'phy62x2_ota.py' -__version__ = "23.01.24" +__version__ = "25.02.24" def do_crc(s, c): return zlib.crc32(s, c) & 0xffffffff @@ -84,10 +84,11 @@ class phy_ota: size = 0x100 sections = 15 wfaddr = (wrfaddr & (MAX_FLASH_SIZE-1)) + size + wrfaddr = wfaddr; faddr_min = MAX_FLASH_SIZE-1 # xip addr min faddr_max = 0 # xip addr max rsize = 0 # size ram data - hexf = bytearray(struct.pack(' 4096) or (fbuplen <= 256): + print('Error: Boot update file %s format!' % args.fbup) + exit(2) + datafbup = bytearray(datafbup[0:-4]) + phy = phy_ota() hp = phy.ParseHexFile(args.filename, args.wraddr) if hp == None: - sys.exit(2) + sys.exit(3) hexf = phy.HexfHeader(hp, args.runaddr, args.wraddr, args.idota) if hexf == None: - sys.exit(2) + sys.exit(4) hp[0][1] = hexf print ('---- File Structure -------------------------------------') @@ -182,15 +205,19 @@ def main(): fout = open(outfile, 'wb') except: print('No file opened', outfile) - sys.exit(3) + sys.exit(5) fsize = 0 for ihp in hp: fsize += len(ihp[1]) - fillsize = 16 - fsize % 16 - fsize += fillsize segment = 0 crc = 0 try: + if args.fbup != None: + #print('size: %08x , %08x' % (fsize, fbuplen)) + datafbup[12:16] = int.to_bytes(fsize + fbuplen, 4, byteorder='little') + datafbup[0xfc:0x100] = int.to_bytes((fbuplen + DEF_START_WR_FLASH_ADDR) | 0x11000000, 4, byteorder='little') + crc = do_crc(datafbup, crc) + fout.write(datafbup) for ihp in hp: if ihp[0] == 0: print('Segment Table[%02d] <- Flash addr: %08x, Size: %08x' % (len(hp) - 1, ihp[2], len(ihp[1]))) @@ -204,9 +231,9 @@ def main(): fout.write(bytearray(struct.pack(' 1: hexf = bytearray(b'\xff')*(0x100) - hexf[0:4] = int.to_bytes(len(hp), 4, byteorder='little') + hexf[0:4] = int.to_bytes(len(hp)-1, 4, byteorder='little') hexf[8:12] = int.to_bytes(start, 4, byteorder='little') #sections = 0 faddr_min = MAX_FLASH_SIZE-1 @@ -592,8 +592,6 @@ def main(): print ('Error Flash read Unique ID!') sys.exit(3) print ('Flash Serial Number:', rb.hex()) # Unique ID - - exit(0) if args.operation == 'rc': #filename = "r%08x-%08x.bin" % (addr, length) if args.size == 0: diff --git a/ota_boot/.autotools b/ota_boot/.autotools new file mode 100644 index 0000000..e73513b --- /dev/null +++ b/ota_boot/.autotools @@ -0,0 +1,43 @@ + + + + + diff --git a/ota_boot/.cproject b/ota_boot/.cproject new file mode 100644 index 0000000..043116b --- /dev/null +++ b/ota_boot/.cproject @@ -0,0 +1,346 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ${cross_make} + -j24 + all + true + true + true + + + ${cross_make} + -j24 + clean + true + true + true + + + ${cross_make} + -j24 + flash + true + true + true + + + ${cross_make} + -j24 + erase_and_flash + true + true + true + + + ${cross_make} + -j24 + reset + true + true + true + + + ${cross_make} + -j24 + flash_ota + true + true + true + + + + \ No newline at end of file diff --git a/ota_boot/.gitignore b/ota_boot/.gitignore new file mode 100644 index 0000000..a3bb0a0 --- /dev/null +++ b/ota_boot/.gitignore @@ -0,0 +1,7 @@ +bin +Listings +Objects +TestTHB2.asm +TestTHB2.uvguix.* +TestTHB2.uvoptx +build diff --git a/ota_boot/.project b/ota_boot/.project new file mode 100644 index 0000000..8ce4333 --- /dev/null +++ b/ota_boot/.project @@ -0,0 +1,34 @@ + + + ota_boot + + + + + + org.python.pydev.PyDevBuilder + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.autotools.core.autotoolsNatureV2 + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + org.eclipse.cdt.core.ccnature + org.python.pydev.pythonNature + + diff --git a/ota_boot/.pydevproject b/ota_boot/.pydevproject new file mode 100644 index 0000000..2b04565 --- /dev/null +++ b/ota_boot/.pydevproject @@ -0,0 +1,5 @@ + + + Default + python interpreter + diff --git a/ota_boot/.settings/language.settings.xml b/ota_boot/.settings/language.settings.xml new file mode 100644 index 0000000..84095c5 --- /dev/null +++ b/ota_boot/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/ota_boot/.settings/org.eclipse.cdt.codan.core.prefs b/ota_boot/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..da30759 --- /dev/null +++ b/ota_boot/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,109 @@ +eclipse.preferences.version=1 +org.eclipse.cdt.codan.checkers.errnoreturn=Warning +org.eclipse.cdt.codan.checkers.errnoreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return\\")",implicit\=>false} +org.eclipse.cdt.codan.checkers.errreturnvalue=Error +org.eclipse.cdt.codan.checkers.errreturnvalue.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused return value\\")"} +org.eclipse.cdt.codan.checkers.localvarreturn=-Warning +org.eclipse.cdt.codan.checkers.localvarreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Returning the address of a local variable\\")"} +org.eclipse.cdt.codan.checkers.nocommentinside=-Error +org.eclipse.cdt.codan.checkers.nocommentinside.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Nesting comments\\")"} +org.eclipse.cdt.codan.checkers.nolinecomment=-Error +org.eclipse.cdt.codan.checkers.nolinecomment.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Line comments\\")"} +org.eclipse.cdt.codan.checkers.noreturn=Error +org.eclipse.cdt.codan.checkers.noreturn.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"No return value\\")",implicit\=>false} +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation=Error +org.eclipse.cdt.codan.internal.checkers.AbstractClassCreation.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Abstract class cannot be instantiated\\")"} +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem=Error +org.eclipse.cdt.codan.internal.checkers.AmbiguousProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Ambiguous problem\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.AssignmentInConditionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Assignment in condition\\")"} +org.eclipse.cdt.codan.internal.checkers.AssignmentToItselfProblem=Error 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default in switch\\")",defaultWithAllEnums\=>false} +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissReferenceProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing reference return value in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.MissSelfCheckProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Missing self check in assignment operator\\")"} +org.eclipse.cdt.codan.internal.checkers.MultipleDeclarationsProblem=-Warning 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redefinition\\")"} +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ReturnStyleProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Return with parenthesis\\")"} +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.ScanfFormatStringSecurityProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Format String Vulnerability\\")"} +org.eclipse.cdt.codan.internal.checkers.ShallowCopyProblem=-Warning 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+org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} diff --git a/ota_boot/.settings/org.eclipse.cdt.core.prefs b/ota_boot/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..c8ec5df --- /dev/null +++ b/ota_boot/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,6 @@ +doxygen/doxygen_new_line_after_brief=true +doxygen/doxygen_use_brief_tag=false +doxygen/doxygen_use_javadoc_tags=true +doxygen/doxygen_use_pre_tag=false +doxygen/doxygen_use_structural_commands=false +eclipse.preferences.version=1 diff --git a/ota_boot/.settings/org.eclipse.cdt.managedbuilder.core.prefs b/ota_boot/.settings/org.eclipse.cdt.managedbuilder.core.prefs new file mode 100644 index 0000000..4cabf0c --- /dev/null +++ b/ota_boot/.settings/org.eclipse.cdt.managedbuilder.core.prefs @@ -0,0 +1,13 @@ +eclipse.preferences.version=1 +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPATH/delimiter=; +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPATH/operation=remove +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPLUS_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/CPLUS_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/C_INCLUDE_PATH/delimiter=; +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/C_INCLUDE_PATH/operation=remove +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/append=true +environment/buildEnvironmentInclude/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/appendContributed=true +environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/LIBRARY_PATH/delimiter=; +environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/LIBRARY_PATH/operation=remove +environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/append=true +environment/buildEnvironmentLibrary/ilg.gnuarmeclipse.managedbuild.cross.toolchain.base.28719871/appendContributed=true diff --git a/ota_boot/.settings/org.eclipse.core.resources.prefs b/ota_boot/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..99f26c0 --- /dev/null +++ b/ota_boot/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/ota_boot/.settings/org.eclipse.embedcdt.managedbuild.cross.arm.core.prefs b/ota_boot/.settings/org.eclipse.embedcdt.managedbuild.cross.arm.core.prefs new file mode 100644 index 0000000..2f7e5c4 --- /dev/null +++ b/ota_boot/.settings/org.eclipse.embedcdt.managedbuild.cross.arm.core.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +toolchain.path.1287942917=D\:\\MCU\\GNU_Tools_ARM_Embedded\\13.2.rel1\\bin diff --git a/ota_boot/Makefile b/ota_boot/Makefile new file mode 100644 index 0000000..63c11a2 --- /dev/null +++ b/ota_boot/Makefile @@ -0,0 +1,138 @@ +############################################################################## +PROJECT_NAME ?= ota_upboot +#POJECT_DEF ?= -DDEVICE=DEVICE_THB2 +############################################################################## +COM_PORT = COM11 +############################################################################## +# Source +SRC_PATH = ./source +SRC_PRJ = main.c + +INCLUDES = -I$(SRC_PATH) +INCLUDES += -I$(SRC_PATH)/include +INCLUDES += -I$(SRC_PATH)/misc +INCLUDES += -I$(SRC_PATH)/misc/CMSIS/include +INCLUDES += -I$(SRC_PATH)/misc/CMSIS/device/phyplus + +STARTUP_ASM = $(SRC_PATH)/misc/CMSIS/device/phyplus/phy6222_start.s + +SRCS = $(addprefix $(SRC_PATH)/, $(SRC_PRJ)) +SRCS += $(SRC_PATH)/misc/CMSIS/device/phyplus/phy6222_vectors.c + +############################################################################## +DEFINES += -D__GCC +DEFINES += $(POJECT_DEF) +DEFINES += -DPHY_MCU_TYPE=MCU_BUMBEE_M0 + +############################################################################## +BIN_DIR = ./bin +OBJ_DIR = ./build +PYTHON = python3 +GCC_PATH = +CC = $(GCC_PATH)arm-none-eabi-gcc +OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy +OBJDUMP = $(GCC_PATH)arm-none-eabi-objdump +SIZE = $(GCC_PATH)arm-none-eabi-size +READELF = $(GCC_PATH)arm-none-eabi-readelf +############################################################################## +ARCH_FLAGS := -mcpu=cortex-m0 -mthumb -mthumb-interwork +OPT_CFLAGS ?= -Os +DEB_CFLAGS ?= -g3 -ggdb +############################################################################## +ASFLAGS := $(ARCH_FLAGS) $(OPT_CFLAGS) $(DEB_CFLAGS) +CFLAGS := $(ARCH_FLAGS) $(OPT_CFLAGS) $(DEB_CFLAGS) +CFLAGS += -W -Wall --std=gnu99 +CFLAGS += -fno-diagnostics-show-caret +CFLAGS += -fdata-sections -ffunction-sections +CFLAGS += -funsigned-char -funsigned-bitfields +#CFLAGS += -fpack-struct +#CFLAGS += -mno-unaligned-access +#CFLAGS += -munaligned-access +CFLAGS += -fms-extensions +CFLAGS += -specs=nosys.specs +CFLAGS += -Wl,--gc-sections + +LDSCRIPT ?= $(SRC_PATH)/misc/ota_upboot.ld +#BIN_OTA = $(OBJ_DIR)/$(PROJECT_NAME).bin +BIN_OTA = ./$(PROJECT_NAME).add + +LDFLAGS := $(ARCH_FLAGS) +LDFLAGS += --static -nostartfiles -nostdlib +LDFLAGS += -Wl,--gc-sections +LDFLAGS += -Wl,--script=$(LDSCRIPT) +LDFLAGS += -Wl,--just-symbols=$(SRC_PATH)/misc/bb_rom_sym_m0.gcc +LDFLAGS += -Wl,-Map=$(OBJ_DIR)/$(PROJECT_NAME).map +LIBS += -Wl,--start-group -lgcc -lnosys -Wl,--end-group + +############################################################################## + +CFLAGS += $(DEFINES) $(INCLUDES) + +#SRC_O = $(patsubst %.c,%.o,$(patsubst sdk/%, $(SRC_PATH)%, $(SRCS))) + +SRC_O = $(SRCS:%.c=%.o) $(STARTUP_ASM:%.s=%.o) +OBJS = $(patsubst %, $(OBJ_DIR)/%, $(patsubst ./%, %, $(SRC_O))) + +DEPENDENCY_LIST = $(OBJS:%o=%d) + +############################################################################## +.PHONY: all directory clean size flash erase_and_flash + +all: directory $(SRC_O) $(OBJ_DIR)/$(PROJECT_NAME).elf $(OBJ_DIR)/$(PROJECT_NAME).hex $(BIN_OTA) $(OBJ_DIR)/$(PROJECT_NAME).asm size + +%.elf %.map: $(SRC_O) $(LDSCRIPT) Makefile + @echo LD: $@ + @$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o $@ + +%.hex: %.elf + @echo OBJCOPY: $@ + @$(OBJCOPY) -O ihex $^ $@ + +%.add: %.hex + @echo Make: $@ + $(PYTHON) ./phy62x2_ota.py -o $(BIN_OTA) $(OBJ_DIR)/$(PROJECT_NAME).hex + +%.asm: %.elf + @echo OBJDUMP: $@ + @$(OBJDUMP) -s -S $^ >$@ + +%.o : %.c + @echo CC: $< + @mkdir -p $(OBJ_DIR)/$(dir $@) + @$(CC) $(CFLAGS) $(INCFLAGS) -c $< -o $(OBJ_DIR)/$@ + @$(CC) -MM $(CFLAGS) $(INCFLAGS) $< -MT $@ -MF $(OBJ_DIR)/$(patsubst %.o,%.d,$@) + +%.o : %.s + @echo CC: $< + @mkdir -p $(OBJ_DIR)/$(dir $@) + @$(CC) $(CFLAGS) $(INCFLAGS) -c $< -o $(OBJ_DIR)/$@ + @$(CC) -MM $(CFLAGS) $(INCFLAGS) $< -MT $@ -MF $(OBJ_DIR)/$(patsubst %.o,%.d,$@) + +flash: + @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex + +flash_ota: + @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -r we 0x10000 $(BIN_OTA) + +erase_and_flash: + @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -b 1000000 -e -r wh $(OBJ_DIR)/$(PROJECT_NAME).hex + +reset: + @$(PYTHON) ./rdwr_phy62x2.py -p$(COM_PORT) -r i + +directory: + @mkdir -p $(OBJ_DIR) + +size: $(OBJ_DIR)/$(PROJECT_NAME).elf + @echo size: + @$(SIZE) -t $^ + @$(READELF) -l $^ + @echo + +clean: + @echo clean + @-rm -rf $(OBJ_DIR) + +-include $(DEPENDENCY_LIST) + +VPATH:=$(OBJ_DIR) diff --git a/ota_boot/ota_upboot.add b/ota_boot/ota_upboot.add new file mode 100644 index 0000000..ce77bf4 Binary files /dev/null and b/ota_boot/ota_upboot.add differ diff --git a/ota_boot/phy62x2_ota.py b/ota_boot/phy62x2_ota.py new file mode 100644 index 0000000..baf4c4c --- /dev/null +++ b/ota_boot/phy62x2_ota.py @@ -0,0 +1,242 @@ +#!/usr/bin/env python3 + +# phy62x2_ota.py 22.01.2024 pvvx # + +import argparse +import io +import os +import struct +import sys +import zlib + +START_UP_FLAG = 0x36594850 #"PHY6" + +MAX_FLASH_SIZE = 0x200000 +EXT_FLASH_ADD = 0x400000 + +DEF_START_RUN_APP_ADDR = 0x1FFF1838 +DEF_START_WR_FLASH_ADDR = 0x010000 + +PHY_FLASH_SECTOR_SIZE = 4096 +PHY_FLASH_SECTOR_MASK = 0xfffff000 +PHY_WR_BLK_SIZE = 0x2000 + +__progname__ = 'PHY62x2 OTA Utility' +__filename__ = 'phy62x2_ota.py' +__version__ = "25.02.24" + +def do_crc(s, c): + return zlib.crc32(s, c) & 0xffffffff + +class phy_ota: + def ParseHexFile(self, hexfile, faddr = DEF_START_WR_FLASH_ADDR): + try: + fin = open(hexfile) + except: + print('No file opened', hexfile) + return None + table = [] + result = bytearray() + addr = 0 + naddr = 0 + taddr = 0 + addr_flg = 0 + table.append([0, result, faddr]) + for hexstr in fin.readlines(): + hexstr = hexstr.strip() + if hexstr[7:9] == '04': + if(len(result)): + #print(hex(addr)) + table.append([addr, result, 0]) + addr = int(hexstr[9:13],16) << 16 + addr_flg = 0 + result = bytearray() + continue + if hexstr[7:9] == '05' or hexstr[7:9] == '01': + table.append([addr, result, 0]) + break + taddr = (int(hexstr[3:7],16)) + if addr_flg == 0: + addr_flg = 1 + addr = addr | taddr + naddr = taddr + if taddr != naddr: + addr_flg = 1 + table.append([addr, result, 0]) + addr = (addr & 0xFFFF0000) | taddr + result = bytearray() + #print(hexstr[9:-3]) + result.extend(bytearray.fromhex(hexstr[9:-2])) + naddr = taddr + int(hexstr[1:3],16) + fin.close() + return table + def WriteHexf(self, sn, ph): + offset = ph[2] + offset &= 0x00ffffff + idx = 0 + size = len(ph[1]) + return True + def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, wrfaddr = DEF_START_WR_FLASH_ADDR, otaid = START_UP_FLAG): + if len(hp) > 1: + if len(hp) > 15: + print('Maximum number of segments = 15!') + return None + size = 0x100 + sections = 15 + wfaddr = (wrfaddr & (MAX_FLASH_SIZE-1)) + size + wrfaddr = wfaddr; + faddr_min = MAX_FLASH_SIZE-1 # xip addr min + faddr_max = 0 # xip addr max + rsize = 0 # size ram data + hexf = bytearray(struct.pack(' offset: + faddr_min = offset + send = offset + len(ihp[1]) + if faddr_max <= send: + faddr_max = send + if (wrfaddr + rsize) >= faddr_min: + wrfaddr = (faddr_max + 3) & 0xfffffffc # start wr faddr ram data + #print('Test: Flash addr min: %08x, max: %08x, RAM addr: %08x' % (faddr_min, faddr_max, wrfaddr)) + print ('---- Segments Table -------------------------------------') + + for ihp in hp: + if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM + faddr = wrfaddr # wr faddr ram data + wrfaddr += (len(ihp[1])+3) & 0xfffffffc # next wr faddr ram data + elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash + faddr = ihp[0] & (MAX_FLASH_SIZE-1) + if wfaddr != faddr: + print('Error: The segment Flash addr: 0x%08x, Size: 0x%08x does not match the markup (0x%08x)!' % (ihp[0], len(ihp[1]), wfaddr)) + return None + elif ihp[0] == 0: + continue + else: + print('Error: Invalid Segment Address 0x%08x!' % ihp[0]) + return None + ihp[2] = faddr + sections -= 1 + print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], faddr, len(ihp[1]))) + crc = 0xffffffff - do_crc(ihp[1], 0) + hexf.extend(bytearray(struct.pack(' 0: + hexf.extend(bytearray(b'\xff')*(0x10*sections)) + fill = size % 16 + if fill != 0: + hp[len(hp)-1][1].extend(bytearray(b'\xff')*(16 - fill)) + size += 16 - fill + hexf[12:16] = int.to_bytes(size, 4, byteorder='little') + return hexf + return None + +class FatalError(RuntimeError): + def __init__(self, message): + RuntimeError.__init__(self, message) + + @staticmethod + def WithResult(message, result): + message += " (result was %s)" % hexify(result) + return FatalError(message) + +def arg_auto_int(x): + return int(x, 0) + +def main(): + parser = argparse.ArgumentParser(description='%s version %s' % (__progname__, __version__), prog = __filename__) + parser.add_argument('--idota', '-i', help = 'Flag ID OTA (default: 0x%08x)' % START_UP_FLAG, type = arg_auto_int, default = START_UP_FLAG); + parser.add_argument('--runaddr', '-r', help = 'Application run-start address (default: 0x%08x)' % DEF_START_RUN_APP_ADDR, type = arg_auto_int, default = DEF_START_RUN_APP_ADDR); + parser.add_argument('--wraddr', '-w', help = 'Application write address (default: 0x%08x)' % DEF_START_WR_FLASH_ADDR, type = arg_auto_int, default = DEF_START_WR_FLASH_ADDR); + parser.add_argument('--fbup', '-f', help = 'Boot update file (default: none)', default = None); + parser.add_argument('--outfile', '-o', help = 'Output bin file') + parser.add_argument('filename', help = 'Name of hex file') + + args = parser.parse_args() + + print('=========================================================') + print('%s version %s' % (__progname__, __version__)) + print('---------------------------------------------------------') + + if args.fbup != None: + try: + fbup = open(args.fbup, 'rb') + except Exception as e: + print('Error: Open file %s, %s' % (args.fbup, e)) + exit(1) + try: + datafbup = fbup.read(); + except Exception as e: + print('Error: Read file %s,: %s' % (args.fbup, e)) + exit(1) + fbup.close() + fbupid = int.from_bytes(datafbup[0:4], byteorder='little') + fbuplen = int.from_bytes(datafbup[12:16], byteorder='little') + print("Boot update file id: %08x:%08x" %(fbupid, fbuplen)) + if (fbupid != START_UP_FLAG) or ((fbuplen + 4) != len(datafbup)) or (fbuplen > 4096) or (fbuplen <= 256): + print('Error: Boot update file %s format!' % args.fbup) + exit(2) + datafbup = bytearray(datafbup[0:-4]) + + phy = phy_ota() + + hp = phy.ParseHexFile(args.filename, args.wraddr) + + if hp == None: + sys.exit(3) + hexf = phy.HexfHeader(hp, args.runaddr, args.wraddr, args.idota) + if hexf == None: + sys.exit(4) + hp[0][1] = hexf + + print ('---- File Structure -------------------------------------') + (outfile, ext) = os.path.splitext(args.filename) + outfile += '.bin' + if args.outfile != None: + outfile = args.outfile + try: + fout = open(outfile, 'wb') + except: + print('No file opened', outfile) + sys.exit(5) + fsize = 0 + for ihp in hp: + fsize += len(ihp[1]) + segment = 0 + crc = 0 + try: + if args.fbup != None: + #print('size: %08x , %08x' % (fsize, fbuplen)) + datafbup[12:16] = int.to_bytes(fsize + fbuplen, 4, byteorder='little') + datafbup[0xfc:0x100] = int.to_bytes((fbuplen + DEF_START_WR_FLASH_ADDR) | 0x11000000, 4, byteorder='little') + crc = do_crc(datafbup, crc) + fout.write(datafbup) + for ihp in hp: + if ihp[0] == 0: + print('Segment Table[%02d] <- Flash addr: %08x, Size: %08x' % (len(hp) - 1, ihp[2], len(ihp[1]))) + else: + print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], ihp[2], len(ihp[1]))) + fout.write(ihp[1]) + crc = do_crc(ihp[1], crc) + segment += 1 + crc = 0xffffffff - crc + #print('CRC32: %04x' % crc) + fout.write(bytearray(struct.pack('>:' + def SendResetCmd(self): + return self._port.write(str.encode('reset ')); + def read_reg(self, addr): + pkt = 'rdreg%08x' % addr; + sent = self._port.write(pkt.encode()); + read = self._port.read(17); + if len(read) == 17 and read[0:3] == b'=0x' and read[11:17] == b'#OK>>:': + return int(read[1:11], 16) + return None + def write_reg(self, addr, data): + return self.write_cmd('wrreg%08x %08x ' % (addr, data)) + def ExpFlashSize(self): + if not self.write_reg(0x1fff0898, EXT_FLASH_ADD): + print('Error set ext.Flash size %08x!' % EXT_FLASH_ADD) + return False + return True + def wr_flash_cmd(self, cmd, data = 0, wrlen = 0, addr = 0, addrlen = 0, rdlen = 0, mbit = 0, dummy = 0): + regcmd = cmd << 24 + if wrlen > 0: + regcmd = regcmd | 0x8000 | ((wrlen - 1) << 12) + if not self.write_reg(0x4000c8a8, data): #Flash Command Write Data Register + print('Error write Flash Data Register!') + return False + if addrlen > 0: + regcmd = regcmd | 0x80000 | ((addrlen - 1) << 16) + if not self.write_reg(0x4000c894, addr): #Flash Command Write Addr Register + print('Error write Flash Address Register!') + return False + if rdlen > 0: + regcmd = regcmd | 0x800000 | ((rdlen - 1) << 20) + if mbit > 0: + regcmd = regcmd | 0x40000 + if dummy > 0: + regcmd = regcmd | (dummy << 7); + if not self.write_reg(0x4000c890, regcmd | 1): + print('Error write Flash Command Register!') + return False + return True + def flash_wait_idle(self): + i = 5; + while i > 0: + r = self.read_reg(0x4000c890) + if r == None: + return False + if (r & 2) == 0: + i = 5 + while i > 0: + r = self.read_reg(0x4000c800) + if r == None: + return False + if (r & 0x80000000) != 0: + return True + i -= 1 + return False + i -= 1 + return False + def flash_read_unique_id(self): + if self.wr_flash_cmd(0x4B,0,0,0,4,8): # and self.flash_wait_idle(): + r1 = self.read_reg(0x4000c8a0) + if r1 == None: + return None + r2 = self.read_reg(0x4000c8a4) + if r2 == None: + return None + ret = bytearray(8) + ret[0] = r1 & 0xff + ret[1] = (r1 >> 8) & 0xff + ret[2] = (r1 >> 16) & 0xff + ret[3] = (r1 >> 24) & 0xff + ret[4] = r2 & 0xff + ret[5] = (r2 >> 8) & 0xff + ret[6] = (r2 >> 16) & 0xff + ret[7] = (r2 >> 24) & 0xff + return ret + return None + def flash_read_status(self): + #Flash cmd: Read status + if self.wr_flash_cmd(5,0,0,0,0,1): # and self.flash_wait_idle(): + r = self.read_reg(0x4000c8a0) + if r == None: + return None + return r & 0x0ff + return None + def FlashUnlock(self): + #Flash cmd: Write Enable, Write Status Register 0x00 + return self.wr_flash_cmd(6) and self.wr_flash_cmd(1, 0, 1) + def ReadRevision(self): + #0x001364c8 6222M005 #OK>>: + self._port.write(str.encode('rdrev+ ')); + self._port.timeout = 0.1 + read = self._port.read(26); + if len(read) == 26 and read[0:2] == b'0x' and read[20:26] == b'#OK>>:': + print('Revision:', read[2:19]) + if read[11:15] != b'6222': + print('Wrong Version!') + self.flash_id = int(read[2:11], 16) + self.flash_size = 1 << ((self.flash_id >> 16) & 0xff) + print('FlashID: %06x, size: %d kbytes' % (self.flash_id, self.flash_size >> 10)) + return True + else: + print('Error read Revision!') + return False + def SetBaud(self, baud): + if self._port.baudrate != baud: + print ('Reopen %s port %i baud...' % (self.port, baud), end = ' '), + self._port.write(str.encode("uarts%i" % baud)); + self._port.timeout = 1 + read = self._port.read(3); + if read == b'#OK': + print ('ok') + self._port.close() + self.baud = baud + self._port.baudrate = baud + try: + self._port.open(); + except Exception as e: + print ('Error: Open %s, %d baud! Error: %s' % (self.port, self.baud, e)) + sys.exit(1) + else: + print ('error!') + print ('Error set %i baud on %s port!' % (baud, self.port)) + self._port.close() + sys.exit(3) + return True + def Connect(self, baud=DEF_RUN_BAUD): + self._port.setDTR(True) #TM (lo) + self._port.setRTS(True) #RSTN (lo) + time.sleep(0.1) + self._port.flushOutput() + self._port.flushInput() + time.sleep(0.1) + self._port.setDTR(False) #TM (hi) + self._port.setRTS(False) #RSTN (hi) + self._port.timeout = 0.04 + ttcl = 50; + fct_mode = False + pkt = 'UXTDWU' # UXTL16 UDLL48 UXTDWU + while ttcl > 0: + sent = self._port.write(pkt.encode()); + read = self._port.read(6); + if read == b'cmd>>:' : + break + if read == b'fct>>:' : + fct_mode = True + break + ttcl = ttcl - 1 + if ttcl < 1: + print('PHY62x2 - Error Reset!') + print('Check connection TX->RX, RX<-TX and Chip Power!') + self._port.close() + exit(4) + print('PHY62x2 - Reset Ok') + self._port.close() + self._port.baudrate = DEF_RUN_BAUD + self._port.open(); + self._port.timeout = 0.2 + if fct_mode: + print('PHY62x2 in FCT mode!') + return False + if not self.ReadRevision(): + self._port.close() + exit(4) + if not self.FlashUnlock(): + self._port.close() + exit(4) + if not self.write_reg(0x4000f054, 0): + print('PHY62x2 - Error init1!') + self._port.close() + exit(4) + if not self.write_reg(0x4000f140, 0): + print('PHY62x2 - Error init2!') + self._port.close() + exit(4) + if not self.write_reg(0x4000f144, 0): + print('PHY62x2 - Error init3!') + self._port.close() + exit(4) + print('PHY62x2 - connected Ok') + return self.SetBaud(baud) + def cmd_era4k(self, offset): + print ('Erase sector Flash at 0x%08x...' % offset, end = ' ') + tmp = self._port.timeout + self._port.timeout = 0.5 + ret = self.write_cmd('era4k %X' % (offset | MAX_FLASH_SIZE)) + self._port.timeout = tmp + if not ret: + print ('error!') + else: + print ('ok') + return ret + def cmd_era64k(self, offset): + print ('Erase block 64k Flash at 0x%08x...' % offset, end = ' '), + tmp = self._port.timeout + self._port.timeout = 2 + ret = self.write_cmd('er64k %X' % (offset | MAX_FLASH_SIZE)) + self._port.timeout = tmp + if not ret: + print ('error!') + else: + print ('ok') + return ret + def cmd_er512(self, offset = 0): + print ('Erase block 512k Flash at 0x%08x...' % offset, end = ' '), + tmp = self._port.timeout + self._port.timeout = 2 + ret = self.write_cmd('er512 %X' % (offset | MAX_FLASH_SIZE)) + self._port.timeout = tmp + if not ret: + print ('error!') + else: + print ('ok') + return ret + def cmd_erase_work_flash(self): + print ('Erase Flash work area...', end = ' '), + tmp = self._port.timeout + self._port.timeout = 7 + ret = self.write_cmd('erall ') + self._port.timeout = tmp + if not ret: + print ('error!') + else: + print ('ok') + return ret + def cmd_erase_all_flash(self): + print ('Erase All Chip Flash...', end = ' '), + if self.wr_flash_cmd(6) and self.wr_flash_cmd(0x60): #Write Enable, Chip Erase + i = 77; + while i > 0: + r = self.flash_read_status() + if r == None: + print ('Error!') + return False + if (r & 1) == 0: + print ('ok') + return True + i -= 1 + print ('Timeout!') + return False + def EraseSectorsFlash(self, offset = 0, size = MAX_FLASH_SIZE): + count = int((size + PHY_FLASH_SECTOR_SIZE - 1) / PHY_FLASH_SECTOR_SIZE) + offset &= PHY_FLASH_SECTOR_MASK + if count > 0 and count < 0x10000 and offset >= 0: # 1 byte .. 16 Mbytes + while count > 0: + if offset >= self.old_erase_start and offset < self.old_erase_end: + offset += PHY_FLASH_SECTOR_SIZE + count -= 1 + continue + if (offset & 0x0FFFF) == 0 and count > 15: + if not self.cmd_era64k(offset): + return False + self.old_erase_start = offset + self.old_erase_end = offset + 0x10000 + offset += 0x10000 + count -= 16 + else: + if not self.cmd_era4k(offset): + return False + self.old_erase_start = offset + self.old_erase_end = offset + PHY_FLASH_SECTOR_SIZE + offset += PHY_FLASH_SECTOR_SIZE + count -= 1 + else: + return False + return True + def EraseSectorsFlash2(self, offset = 0, size = MAX_FLASH_SIZE): + count = int((size + PHY_FLASH_SECTOR_SIZE - 1) / PHY_FLASH_SECTOR_SIZE) + offset &= PHY_FLASH_SECTOR_MASK + if count > 0 and count < 0x10000 and offset >= 0: # 1 byte .. 16 Mbytes + while count > 0: + if (offset & 0x0FFFF) == 0 and count > 15: + if not self.cmd_era64k(offset): + return False + offset += 0x10000 + count-=16 + else: + if not self.cmd_era4k(offset): + return False + offset += PHY_FLASH_SECTOR_SIZE + count-=1 + else: + return False + return True + def send_blk(self, stream, offset, size, blkcnt, blknum): + self._port.timeout = 1 + print ('Write 0x%08x bytes to Flash at 0x%08x...' % (size, offset), end = ' '), + if blknum == 0: + if not self.write_cmd('cpnum %d ' % blkcnt): + print ('error!') + return False + self._port.write(str.encode('cpbin c%d %X %X %X' % (blknum, offset | MAX_FLASH_SIZE, size, 0x1FFF0000 + offset))) + read = self._port.read(12) + if read != b'by hex mode:': + print ('error!') + return False + data = stream.read(size) + self._port.write(data) + read = self._port.read(23); #'checksum is: 0x00001d1e' + #print ('%s' % read), + if read[0:15] != b'checksum is: 0x': + print ('error!') + return False + self._port.write(read[15:]) + read = self._port.read(6) + if read != b'#OK>>:': + print ('error!') + return False + print ('ok') + return True + def WriteBlockFlash(self, stream, offset = 0, size = 0x8000): + offset &= 0x00ffffff + if self.autoerase: + if not self.EraseSectorsFlash(offset, size): + return False + sblk = PHY_WR_BLK_SIZE + blkcount = (size + sblk - 1) / sblk + blknum = 0 + while(size > 0): + if size < sblk: + sblk = size + if not self.send_blk(stream, offset, sblk, blkcount, blknum): + return False + blknum+=1 + offset+=sblk + size-=sblk + return True + def ReadBusToFile(self, ff, addr=0x11000000, size=0x80000): + flg = size > 128 + if not flg: + print('\rRead 0x%08x...' % addr, end=' ') #, flush=True + while size > 0: + if flg and addr & 127 == 0: + print('\rRead 0x%08x...' % addr, end=' ') #, flush=True + rw = self.read_reg(addr) + if rw == None: + print('error!') + print('\rError read address 0x%08x!' % addr) + return False + dw = struct.pack(' 0): + if size < sblk: + sblk = size + if not self.send_blk(stream, offset, sblk, blkcount, blknum): + return False + blknum+=1 + offset+=sblk + size-=sblk + return True + def HexStartSend(self): + return self.write_cmd('spifs 0 1 3 0 ') and self.write_cmd('sfmod 2 2 ') and self.write_cmd('cpnum ffffffff ') + def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, raddr = DEF_START_WR_FLASH_ADDR): + if len(hp) > 1: + hexf = bytearray(b'\xff')*(0x100) + hexf[0:4] = int.to_bytes(len(hp)-1, 4, byteorder='little') + hexf[8:12] = int.to_bytes(start, 4, byteorder='little') + #sections = 0 + faddr_min = MAX_FLASH_SIZE-1 + faddr_max = 0 + rsize = 0 + for ihp in hp: + if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM + rsize += len(ihp[1]) + elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash + offset = ihp[0] & (MAX_FLASH_SIZE-1) + if faddr_min > offset: + faddr_min = offset + send = offset + len(ihp[1]) + if faddr_max <= send: + faddr_max = send + if (raddr + rsize) >= faddr_min: + raddr = (faddr_max + 3) & 0xfffffffc + #print('Test: Flash addr min: %08x, max: %08x, RAM addr: %08x' % (faddr_min, faddr_max, raddr)) + print ('---- Segments Table -------------------------------------') + for ihp in hp: + if (ihp[0] & 0x1fff0000) == 0x1fff0000: # SRAM + faddr = raddr + raddr += (len(ihp[1])+3) & 0xfffffffc + elif (ihp[0] & (~(MAX_FLASH_SIZE-1))) == 0x11000000: # Flash + faddr = ihp[0] & (MAX_FLASH_SIZE-1) + elif ihp[0] == 0: + continue + else: + print('Invalid Segment Address 0x%08x!' % ihp[0]) + return None + ihp[2] = faddr + print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], faddr, len(ihp[1]))) + hexf.extend(bytearray(struct.pack(' 1024: + print("%.3f KBytes saved to file '%s'" % (byteSaved/1024, args.filename)) + else: + print("%i Bytes saved to file '%s'" % (byteSaved, args.filename)) + ff.close() + #--------------------------------wr flash bin + if args.operation == 'we' or args.operation == 'wf': + offset = args.address & (MAX_FLASH_SIZE-1) + if offset >= MAX_FLASH_SIZE: + print ('Error Start Flash address!') + sys.exit(1) + stream = open(args.filename, 'rb') + size = os.path.getsize(args.filename) + if size < 1: + stream.close() + print ('Error: File size = 0!') + sys.exit(1) + offset = args.address & (MAX_FLASH_SIZE-1) + if size + offset > MAX_FLASH_SIZE: + size = MAX_FLASH_SIZE - offset + if size < 1: + stream.close() + print ('Error: Write File size = 0!') + sys.exit(1) + aerase = args.operation == 'we' + if args.erase == True or args.allerase == True: + aerase = False; + if args.allerase == True: + if not phy.cmd_erase_all_flash(): + stream.close() + print ('Error: Erase All Flash!') + sys.exit(3) + else: + if args.erase == True: + if not phy.cmd_erase_work_flash(): + stream.close + print ('Error: Erase Flash!') + sys.exit(3) + phy.SetAutoErase(aerase) + print ('Write Flash data 0x%08x to 0x%08x from file: %s ...' % (offset, offset + size, args.filename)) + if not phy.ExpFlashSize(): + exit(4) + if size > 0: + if not phy.WriteBlockFlash(stream, offset, size): + stream.close() + print ('Error: Write Flash!') + sys.exit(2) + stream.close() + print ('----------------------------------------------------------') + print ('Write Flash data 0x%08x to 0x%08x from file: %s - ok.' % (offset, offset + size, args.filename)) + #--------------------------------wr flash hex + if args.operation == 'wh': + hp = ParseHexFile(args.filename) + if hp == None: + sys.exit(2) + hexf = phy.HexfHeader(hp, args.start, args.write) + if hexf == None: + sys.exit(2) + hp[0][1] = hexf + if not phy.HexStartSend(): + sys.exit(2) + print ('----------------------------------------------------------') + aerase = True + if args.erase == True or args.allerase == True: + aerase = False; + if args.allerase == True: + if not phy.cmd_erase_all_flash(): + stream.close() + print ('Error: Erase All Flash!') + sys.exit(3) + else: + if args.erase == True: + if not phy.cmd_erase_work_flash(): + stream.close + print ('Error: Erase Flash!') + sys.exit(3) + phy.SetAutoErase(aerase) + if not phy.ExpFlashSize(): + exit(4) + segment = 0 + for ihp in hp: + if ihp[0] == 0: + print('Segment Table[%02d] <- Flash addr: %08x, Size: %08x' % (len(hp) - 1, ihp[2], len(ihp[1]))) + else: + print('Segment: %08x <- Flash addr: %08x, Size: %08x' % (ihp[0], ihp[2], len(ihp[1]))) + stream = io.BytesIO(ihp[1]) + if not phy.WriteBlockFlash(stream, ihp[2], len(ihp[1])): + stream.close() + sys.exit(2) + stream.close() + segment += 1 + print ('----------------------------------------------------------') + print ('Write Flash from file: %s - ok.' % args.filename) + #--------------------------------erase flash region + if args.operation == 'er': + offset = args.address & (MAX_FLASH_SIZE-1) + if offset >= MAX_FLASH_SIZE: + print ('Error Flash Start address!') + sys.exit(1) + size = args.size & (MAX_FLASH_SIZE-1) + if size >= MAX_FLASH_SIZE: + print ('Error Flash Erase size!') + sys.exit(1) + if size + offset > MAX_FLASH_SIZE: + size = MAX_FLASH_SIZE - offset + if size < 1: + print ('Error Flash Erase size!') + sys.exit(1) + if not phy.ExpFlashSize(): + exit(4) + if not phy.EraseSectorsFlash(offset, size): + sys.exit(2) + #--------------------------------erase flash all + if args.operation == 'ea': + if not phy.cmd_erase_all_flash(): + print ('Error: Erase All Flash!') + sys.exit(3) + if args.operation == 'ew': + if not phy.cmd_erase_work_flash(): + print ('Error: Erase Flash Work Area!') + sys.exit(3) + if args.reset: + phy.SendResetCmd() + print ("Send command 'reset' - ok") + sys.exit(0) + +if __name__ == '__main__': + main() diff --git a/ota_boot/source/include/bus_dev.h b/ota_boot/source/include/bus_dev.h new file mode 100644 index 0000000..921e9f8 --- /dev/null +++ b/ota_boot/source/include/bus_dev.h @@ -0,0 +1,80 @@ +/************************************************************************************************** + Filename: bus_dev.h + Revised: + Revision: + + Description: This file contains the SoC MCU relate definitions + + SDK_LICENSE + + **************************************************************************************************/ + +#ifndef __BUS_DEV_H__ +#define __BUS_DEV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +//#include "mcu.h" + +enum +{ + RSTC_COLD_UP = 0, + RSTC_WARM_UP = 1, + RSTC_OFF_MODE = 2, + RSTC_WAKE_IO = 3, + RSTC_WAKE_RTC = 4, + RSTC_WARM_NDWC = 5 //user mode, no dwc + +}; + +/* ------------------------- Interrupt Number Definition ------------------------ */ + +typedef enum IRQn +{ + /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 HardFault Interrupt */ + + + + SVCall_IRQn = -5, /* 11 SV Call Interrupt */ + + PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 System Tick Interrupt */ + + /* ---------------------- PHY BUMBEE M0 Interrupt Numbers --------------------- */ + BB_IRQn = 4, /* Base band Interrupt */ + KSCAN_IRQn = 5, /* Key scan Interrupt */ + RTC_IRQn = 6, /* RTC Timer Interrupt */ + + WDT_IRQn = 10, /* Watchdog Timer Interrupt */ + UART0_IRQn = 11, /* UART0 Interrupt */ + I2C0_IRQn = 12, /* I2C0 Interrupt */ + I2C1_IRQn = 13, /* I2C1 Interrupt */ + SPI0_IRQn = 14, /* SPI0 Interrupt */ + SPI1_IRQn = 15, /* SPI1 Interrupt */ + GPIO_IRQn = 16, /* GPIO Interrupt */ + UART1_IRQn = 17, /* UART1 Interrupt */ + SPIF_IRQn = 18, /* SPIF Interrupt */ + DMAC_IRQn = 19, /* DMAC Interrupt */ + TIM1_IRQn = 20, /* Timer1 Interrupt */ + TIM2_IRQn = 21, /* Timer2 Interrupt */ + TIM3_IRQn = 22, /* Timer3 Interrupt */ + TIM4_IRQn = 23, /* Timer4 Interrupt */ + TIM5_IRQn = 24, /* Timer5 Interrupt */ + TIM6_IRQn = 25, /* Timer6 Interrupt */ + + AES_IRQn = 28, /* AES Interrupt */ + ADCC_IRQn = 29, /* ADC Interrupt */ + QDEC_IRQn = 30, /* QDEC Interrupt */ + RNG_IRQn = 31 /* RNG Interrupt */ +} IRQn_Type; + + +#include "core_bumbee_m0.h" + +#include "mcu_phy_bumbee.h" + +#endif diff --git a/ota_boot/source/include/core_bumbee_m0.h b/ota_boot/source/include/core_bumbee_m0.h new file mode 100644 index 0000000..3ad7038 --- /dev/null +++ b/ota_boot/source/include/core_bumbee_m0.h @@ -0,0 +1,90 @@ + +#ifndef PHY_BUMBEE_M0_H +#define PHY_BUMBEE_M0_H + +#ifdef __cplusplus +extern "C" { +#endif + + + + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M0 Processor and Core Peripherals ------- */ +//#define __CM0_REV 0x0000U /* Core revision r0p0 */ +//#define __MPU_PRESENT 0U /* MPU present or not */ +//#define __VTOR_PRESENT 0U /* no VTOR present*/ +#define __NVIC_PRIO_BITS 2U /* Number of Bits used for Priority Levels */ +//#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ + +#include "core_cm0.h" /* Processor and core peripherals */ +#if defined ( __CC_ARM ) +#include "system_ARMCM0.h" /* System Header */ +#endif /*__CC_ARM*/ + +#define NVIC_GetPendingIRQs() (NVIC->ISPR[0U]) +#define NVIC_ClearPendingIRQs(icpr) (NVIC->ICPR[0U] = (unsigned int)icpr) +#define NVIC_SetPendingIRQs(ispr) (NVIC->ISPR[0U] = (unsigned int)ispr) + +#define NVIC_GetEnableIRQs() (NVIC->ISER[0U]) +#define NVIC_DisableIRQs(irqs) (NVIC->ICER[0U] = (unsigned int)irqs) +#define NVIC_EnableIRQs(iser) (NVIC->ISER[0U] = (unsigned int)iser) + +#define NVIC_ClearWakeupIRQ(irqn) +#define NVIC_SetWakeupIRQ(irqn) + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + + + +#ifdef __cplusplus +} +#endif + +#endif /* PHY_BUMBEE_M0 */ diff --git a/ota_boot/source/include/global_config.h b/ota_boot/source/include/global_config.h new file mode 100644 index 0000000..42caa73 --- /dev/null +++ b/ota_boot/source/include/global_config.h @@ -0,0 +1,233 @@ +/** + **************************************************************************************** + + @file global_config.h + + @brief This file contains the definitions of index of global configuration which + will be configured in APP project. + + + $Rev: $ + + SDK_LICENSE + + **************************************************************************************** +*/ + + +#ifndef _GLOBAL_CONFIG_H_ +#define _GLOBAL_CONFIG_H_ + +#include "types.h" + +/******************************************************************************* + software configuration parameters definition +*/ + +#define CONFIG_BASE_ADDR 0x1fff0400 + +#define SOFT_PARAMETER_NUM 256 +// parameter index of configuration array +#define ADV_CHANNEL_INTERVAL 0 // interval between adv channel in the same adv event +#define SCAN_RSP_DELAY 1 // to adjust scan req -> scan rsp delay +#define CONN_REQ_TO_SLAVE_DELAY 2 // to calibrate the delay between conn req & 1st slave conn event +#define SLAVE_CONN_DELAY 3 // to adjust the delay between 2 slave connection events +#define SLAVE_CONN_DELAY_BEFORE_SYNC 4 // to adjust the delay between 2 slave connection events before 1st anchor is acquired +#define MAX_SLEEP_TIME 5 // maximum sleep time in us +#define MIN_SLEEP_TIME 6 // minimum sleep time in us +#define WAKEUP_ADVANCE 7 // wakeup advance time, to cover HW delay, crystal settle time, sw delay, ... etc. +#define WAKEUP_DELAY 8 // cycles of SW delay to wait crystal settle + +#define HDC_DIRECT_ADV_INTERVAL 9 +#define LDC_DIRECT_ADV_INTERVAL 10 + + +#define LL_SWITCH 11 // Link Layer switch, 1 enable, 0 disable +#define NON_ADV_CHANNEL_INTERVAL 12 // interval between non-adv channel in the same adv event + +#define CLOCK_SETTING 14 // HCLK +#define LL_HW_BB_DELAY 15 +#define LL_HW_AFE_DELAY 16 +#define LL_HW_PLL_DELAY 17 + +#define LL_HW_RTLP_LOOP_TIMEOUT 18 +#define LL_HW_RTLP_1ST_TIMEOUT 19 + +#define MIN_TIME_TO_STABLE_32KHZ_XOSC 20 + +#define LL_TX_PKTS_PER_CONN_EVT 21 +#define LL_RX_PKTS_PER_CONN_EVT 22 + + +// ============= A1 ROM metal change add +#define DIR_ADV_DELAY 23 + + +#define LL_TX_PWR_TO_REG_BIAS 24 + + +#define LL_SMART_WINDOW_COEF_ALPHA 25 +#define LL_SMART_WINDOW_TARGET 26 +#define LL_SMART_WINDOW_INCREMENT 27 +#define LL_SMART_WINDOW_LIMIT 28 +#define LL_SMART_WINDOW_ACTIVE_THD 29 +#define LL_SMART_WINDOW_ACTIVE_RANGE 30 + +#define LL_SMART_WINDOW_FIRST_WINDOW 31 + +#define LL_HW_Tx_TO_RX_INTV 32 +#define LL_HW_Rx_TO_TX_INTV 33 + +#define INITIAL_STACK_PTR 34 +#define ALLOW_TO_SLEEP_TICK_RC32K 35 + +#define LL_HW_BB_DELAY_ADV 36 +#define LL_HW_AFE_DELAY_ADV 37 +#define LL_HW_PLL_DELAY_ADV 38 + +// For scan & master, add 2018-6-15 +#define LL_ADV_TO_SCAN_REQ_DELAY 39 +#define LL_ADV_TO_CONN_REQ_DELAY 40 + +#define LL_MOVE_TO_MASTER_DELAY 41 + +#define LL_HW_TRLP_LOOP_TIMEOUT 42 + +#define LL_CONN_REQ_WIN_SIZE 43 +#define LL_CONN_REQ_WIN_OFFSET 44 + +#define LL_MASTER_PROCESS_TARGET 45 +#define LL_MASTER_TIRQ_DELAY 46 + + +#define LL_HW_BB_DELAY_2MPHY 47 +#define LL_HW_AFE_DELAY_2MPHY 48 +#define LL_HW_PLL_DELAY_2MPHY 49 + +#define LL_HW_Tx_TO_RX_INTV_2MPHY 50 +#define LL_HW_Rx_TO_TX_INTV_2MPHY 51 + +#define LL_HW_BB_DELAY_500KPHY 52 +#define LL_HW_AFE_DELAY_500KPHY 53 +#define LL_HW_PLL_DELAY_500KPHY 54 + +#define LL_HW_Tx_TO_RX_INTV_500KPHY 55 +#define LL_HW_Rx_TO_TX_INTV_500KPHY 56 + +#define LL_HW_BB_DELAY_125KPHY 57 +#define LL_HW_AFE_DELAY_125KPHY 58 +#define LL_HW_PLL_DELAY_125KPHY 59 + +#define LL_HW_Tx_TO_RX_INTV_125KPHY 60 +#define LL_HW_Rx_TO_TX_INTV_125KPHY 61 + +#define LL_HW_TRLP_TO_GAP 62 +#define LL_HW_RTLP_TO_GAP 63 + +#define LL_TRX_NUM_ADAPTIVE_CONFIG 64 +#define OSAL_SYS_TICK_WAKEUP_TRIM 65 + +// ==== A2 add, for secondary adv/scan +#define LL_NOCONN_ADV_EST_TIME 70 +#define LL_NOCONN_ADV_MARGIN 71 +#define LL_SEC_SCAN_MARGIN 72 +#define LL_MIN_SCAN_TIME 73 +// Bumblebee ROM code +#define LL_CONN_ADV_EST_TIME 74 +#define LL_SCANABLE_ADV_EST_TIME 75 + + + +#define MAC_ADDRESS_LOC 80 + +// ==== For Extended Adv & Periodic adv +#define LL_EXT_ADV_INTER_PRI_CHN_INT 81 +#define LL_EXT_ADV_INTER_AUX_CHN_INT 82 +#define LL_EXT_ADV_RSC_POOL_PERIOD 83 +#define LL_EXT_ADV_RSC_POOL_UNIT 84 + +#define LL_EXT_ADV_TASK_DURATION 86 +#define LL_PRD_ADV_TASK_DURATION 87 +#define LL_CONN_TASK_DURATION 88 + +#define TIMER_ISR_ENTRY_TIME 90 // time from HW timer expiry to ISR entry, unit: us +#define LL_MULTICONN_MASTER_PREEMP 91 +#define LL_MULTICONN_SLAVE_PREEMP 92 + +#define LL_EXT_ADV_INTER_SEC_CHN_INT 93 +#define LL_EXT_ADV_PRI_2_SEC_CHN_INT 94 + +#define LL_EXT_ADV_RSC_PERIOD 95 +#define LL_EXT_ADV_RSC_SLOT_DURATION 96 + +#define LL_PRD_ADV_RSC_PERIOD 97 +#define LL_PRD_ADV_RSC_SLOT_DURATION 98 + +#define LL_EXT_ADV_PROCESS_TARGET 99 +#define LL_PRD_ADV_PROCESS_TARGET 100 + +#define EXT_ADV_AUXSCANRSP_DELAY_1MPHY 101 +#define EXT_ADV_AUXCONNRSP_DELAY_1MPHY 102 + +#define EXT_ADV_AUXSCANRSP_DELAY_2MPHY 103 +#define EXT_ADV_AUXCONNRSP_DELAY_2MPHY 104 + +#define EXT_ADV_AUXSCANRSP_DELAY_500KPHY 105 +#define EXT_ADV_AUXCONNRSP_DELAY_500KPHY 106 + +#define EXT_ADV_AUXSCANRSP_DELAY_125KPHY 107 +#define EXT_ADV_AUXCONNRSP_DELAY_125KPHY 108 + +#define EXT_ADV_AUXSCANREQ_DELAY_1MPHY 109 +#define EXT_ADV_AUXCONNREQ_DELAY_1MPHY 110 + +#define EXT_ADV_AUXSCANREQ_DELAY_2MPHY 111 +#define EXT_ADV_AUXCONNREQ_DELAY_2MPHY 112 + +#define EXT_ADV_AUXSCANREQ_DELAY_125KPHY 113 +#define EXT_ADV_AUXCONNREQ_DELAY_125KPHY 114 + +#define LL_EXT_ADV_INTER_SEC_CHN_INT_2MPHY 115 + +//Open the RX window in advance if the connection interval is too large in sleep mode +#define LL_ENLARGE_ADVANCE_RX_WINDOW_VALUE 116 /// 200 + +#define GARBAGE_DATA_RESOURCE 117 /// 1000 +#define MAXSCANRSPONSES 118 /// 64 + + + + + + + + +// ============== + +#define RC32_TRACKINK_ALLOW 0x00000001 // enable tracking RC 32KHz clock with 16MHz hclk +#define SLAVE_LATENCY_ALLOW 0x00000002 // slave latency allow switch +#define LL_DEBUG_ALLOW 0x00000004 // enable invoke RAM project debug output fucntion +#define LL_WHITELIST_ALLOW 0x00000008 // enable whitelist filter +#define LL_RC32K_SEL 0x00000010 // select RC32K RTC, otherwise select crystal 32K RTC +#define SIMUL_CONN_ADV_ALLOW 0x00000020 // allow send adv in connect state +#define SIMUL_CONN_SCAN_ALLOW 0x00000040 // allow scan in connect state + +#define CONN_CSA2_ALLOW 0x00000080 // allow using CSA2 in connection state + +#define GAP_DUP_RPT_FILTER_DISALLOW 0x00000100 // duplicate report filter in GAP layer, allow default +#define ENH_CONN_CMP_EVENT_ALLOW 0x00000200 // allow LL to send enhanced connection complete event. +// delete 2018-7-17, should use enum H_SYSCLK_SEL +//enum +//{ +// CLOCK_16MHZ = 0, +// CLOCK_32MHZ = 1, +// CLOCK_48MHZ = 2, +// CLOCK_64MHZ = 3, +// CLOCK_96MHZ = 4, +// CLOCK_32MHZ_DBL=5 +//}; + +//extern uint32 global_config[SOFT_PARAMETER_NUM]; +extern uint32* pGlobal_config; // note: app project needn't this variable + +#endif // _GLOBAL_CONFIG_H_ diff --git a/ota_boot/source/include/mcu_phy_bumbee.h b/ota_boot/source/include/mcu_phy_bumbee.h new file mode 100644 index 0000000..d324e48 --- /dev/null +++ b/ota_boot/source/include/mcu_phy_bumbee.h @@ -0,0 +1,843 @@ +/************* + mcu_phy_bumbee.h + SDK_LICENSE +***************/ +#ifndef __MCU_BUMBEE_M0__ +#define __MCU_BUMBEE_M0__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "types.h" + +typedef enum +{ + MOD_NONE = 0, MOD_CK802_CPU = 0, + MOD_DMA = 3, + MOD_AES = 4, + MOD_IOMUX = 7, + MOD_UART0 = 8, + MOD_I2C0 = 9, + MOD_I2C1 = 10, + MOD_SPI0 = 11, + MOD_SPI1 = 12, + MOD_GPIO = 13, + MOD_QDEC = 15, + MOD_ADCC = 17, + MOD_PWM = 18, + MOD_SPIF = 19, + MOD_VOC = 20, + MOD_TIMER5 = 21, + MOD_TIMER6 = 22, + MOD_UART1 = 25, + + MOD_CP_CPU = 0+32, + MOD_BB = MOD_CP_CPU+3, + MOD_TIMER = MOD_CP_CPU+4, + MOD_WDT = MOD_CP_CPU+5, + MOD_COM = MOD_CP_CPU+6, + MOD_KSCAN = MOD_CP_CPU+7, + MOD_BBREG = MOD_CP_CPU+9, + BBLL_RST = MOD_CP_CPU+10,//can reset,but not gate in here + BBTX_RST = MOD_CP_CPU+11,//can reset,but not gate in here + BBRX_RST = MOD_CP_CPU+12,//can reset,but not gate in here + BBMIX_RST = MOD_CP_CPU+13,//can reset,but not gate in here + MOD_TIMER1 = MOD_CP_CPU+21, + MOD_TIMER2 = MOD_CP_CPU+22, + MOD_TIMER3 = MOD_CP_CPU+23, + MOD_TIMER4 = MOD_CP_CPU+24, + + MOD_PCLK_CACHE = 0+64, + MOD_HCLK_CACHE = MOD_PCLK_CACHE+1, + + MOD_USR0 = 0+96, + MOD_USR1 = MOD_USR0+1, + MOD_USR2 = MOD_USR0+2, + MOD_USR3 = MOD_USR0+3, + MOD_USR4 = MOD_USR0+4, + MOD_USR5 = MOD_USR0+5, + MOD_USR6 = MOD_USR0+6, + MOD_USR7 = MOD_USR0+7, + MOD_USR8 = MOD_USR0+8, + MOD_SYSTEM = 0xFF, +} MODULE_e; + +//SW_CLK -->0x4000f008 +#define _CLK_NONE (BIT(0)) +#define _CLK_CK802_CPU (BIT(0)) +#define _CLK_DMA (BIT(3)) +#define _CLK_AES (BIT(4)) +#define _CLK_IOMUX (BIT(7)) +#define _CLK_UART0 (BIT(8)) +#define _CLK_I2C0 (BIT(9)) +#define _CLK_I2C1 (BIT(10)) +#define _CLK_SPI0 (BIT(11)) +#define _CLK_SPI1 (BIT(12)) +#define _CLK_GPIO (BIT(13)) +#define _CLK_QDEC (BIT(15)) +#define _CLK_ADCC (BIT(17)) +#define _CLK_PWM (BIT(18)) +#define _CLK_SPIF (BIT(19)) +#define _CLK_VOC (BIT(20)) +#define _CLK_TIMER5 (BIT(21)) +#define _CLK_TIMER6 (BIT(22)) +#define _CLK_UART1 (BIT(25)) + + +//SW_CLK1 -->0x4000f014 +#define _CLK_M0_CPU (BIT(0)) +#define _CLK_BB (BIT(3)) +#define _CLK_TIMER (BIT(4)) +#define _CLK_WDT (BIT(5)) +#define _CLK_COM (BIT(6)) +#define _CLK_KSCAN (BIT(7)) +#define _CLK_BBREG (BIT(9)) +#define _CLK_TIMER1 (BIT(21)) +#define _CLK_TIMER2 (BIT(22)) +#define _CLK_TIMER3 (BIT(23)) +#define _CLK_TIMER4 (BIT(24)) + +#define BB_IRQ_HANDLER V4_IRQ_HANDLER +#define KSCAN_IRQ_HANDLER V5_IRQ_HANDLER +#define RTC_IRQ_HANDLER V6_IRQ_HANDLER +#define CP_COM_IRQ_HANDLER V7_IRQ_HANDLER +#define AP_COM_IRQ_HANDLER V8_IRQ_HANDLER +#define WDT_IRQ_HANDLER V10_IRQ_HANDLER +#define UART0_IRQ_HANDLER V11_IRQ_HANDLER +#define I2C0_IRQ_HANDLER V12_IRQ_HANDLER +#define I2C1_IRQ_HANDLER V13_IRQ_HANDLER +#define SPI0_IRQ_HANDLER V14_IRQ_HANDLER +#define SPI1_IRQ_HANDLER V15_IRQ_HANDLER +#define GPIO_IRQ_HANDLER V16_IRQ_HANDLER +#define UART1_IRQ_HANDLER V17_IRQ_HANDLER +#define SPIF_IRQ_HANDLER V18_IRQ_HANDLER +#define DMAC_IRQ_HANDLER V19_IRQ_HANDLER +#define TIM1_IRQ_HANDLER V20_IRQ_HANDLER +#define TIM2_IRQ_HANDLER V21_IRQ_HANDLER +#define TIM3_IRQ_HANDLER V22_IRQ_HANDLER +#define TIM4_IRQ_HANDLER V23_IRQ_HANDLER +#define TIM5_IRQ_HANDLER V24_IRQ_HANDLER +#define TIM6_IRQ_HANDLER V25_IRQ_HANDLER +#define AES_IRQ_HANDLER V28_IRQ_HANDLER +#define ADCC_IRQ_HANDLER V29_IRQ_HANDLER +#define QDEC_IRQ_HANDLER V30_IRQ_HANDLER + +/******************************************************************************* + TYPEDEFS +*/ +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t CH0_AP_MBOX; //0x00 + __IO uint32_t CH0_CP_MBOX; //0x04 + __IO uint32_t CH1_AP_MBOX; //0x08 + __IO uint32_t CH1_CP_MBOX; //0x0c + __IO uint32_t AP_STATUS; //0x10 + __IO uint32_t CP_STATUS; //0x14 + __IO uint32_t AP_INTEN; //0x18 + __IO uint32_t CP_INTEN; //0x1c + __IO uint32_t remap; //0x20 + __IO uint32_t RXEV_EN; //0x24 + __IO uint32_t STCALIB; //0x28 + __IO uint32_t PERI_MASTER_SELECT; //0x2c +} AP_COM_TypeDef; + +typedef struct +{ + __IO uint32_t CTRL0;//0x40 + __IO uint32_t CTRL1;//0x44 + uint32_t reserverd[13]; + __IO uint32_t REMAP_TABLE;//0x7c + __IO uint32_t REMAP_CTRL[32];//0x80 +} AP_CACHE_TypeDef; + +typedef struct +{ + __IO uint8_t CR; //0x0 + uint8_t RESERVED0[3]; + __IO uint32_t TORR; //0x4 + __O uint32_t CCVR; //0x8 + __IO uint32_t CRR; //0xc + uint8_t STAT; //0x10 + uint8_t reserverd1[3]; + __IO uint8_t EOI; //0x14 + uint8_t reserverd2[3]; +} AP_WDT_TypeDef; + + + +typedef struct +{ + __IO uint32_t SW_RESET0; //0x0 + __IO uint32_t SW_RESET1; //0x4 + __IO uint32_t SW_CLK; //0x8 + __IO uint32_t SW_RESET2; //0xc + __IO uint32_t SW_RESET3; //0x10 bit 1: M0 cpu reset pulse, bit 0: M0 system reset pulse. + __IO uint32_t SW_CLK1; //0x14 + __IO uint32_t APB_CLK; //0x18 + __IO uint32_t APB_CLK_UPDATE; //0x1c + __IO uint32_t CACHE_CLOCK_GATE;//0x20 + __IO uint32_t CACHE_RST;//0x24 + __IO uint32_t CACHE_BYPASS;//0x28 +} AP_PCR_TypeDef; + +typedef struct +{ + __IO uint32_t LoadCount; //0x0 + __IO uint32_t CurrentCount; //0x4 + __IO uint32_t ControlReg; //0x8 + __IO uint32_t EOI; //0xc + __IO uint32_t status; //0x10 + +} AP_TIM_TypeDef; + +typedef struct +{ + __IO uint32_t IntStatus; + __IO uint32_t EOI; + __IO uint32_t unMaskIntStatus; + __IO uint32_t version; +} AP_TIM_SYS_TypeDef; + + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ + +typedef struct +{ + union + { + __I uint8_t RBR; + __IO uint8_t THR; + __IO uint8_t DLL; + uint32_t RESERVED0; //0x0 + }; + union + { + __IO uint8_t DLM; + __IO uint32_t IER; //0x4 + }; + union + { + __I uint32_t IIR; //0x8 + __IO uint8_t FCR; + }; + __IO uint8_t LCR; //0xc + uint8_t RESERVED1[3];//Reserved + __IO uint32_t MCR; //0x10 + __I uint8_t LSR; //0x14 + uint8_t RESERVED2[3];//Reserved + __IO uint32_t MSR; //0x18 + __IO uint8_t SCR; //0x1c + uint8_t RESERVED3[3];//Reserved + __IO uint32_t LPDLL; //0x20 + __IO uint32_t LPDLH; //0x24 + __IO uint32_t recerved[2]; + union + { + __IO uint32_t SRBR[16]; // 0x30~60xc + __IO uint32_t STHR[16]; + }; + __IO uint32_t FAR; //0x70 + __IO uint32_t TFR; //0x74 + __IO uint32_t RFW; // 0x78 + __IO uint32_t USR; // 0x7c + __IO uint32_t TFL; + __IO uint32_t RFL; + __IO uint32_t SRR; + __IO uint32_t SRTS; + __IO uint32_t SBCR; + __IO uint32_t SDMAM; + __IO uint32_t SFE; + __IO uint32_t SRT; + __IO uint32_t STET; //0xa0 + __IO uint32_t HTX; + __IO uint32_t DMASA; //0xa8 + __IO uint32_t reserved[18]; + __IO uint32_t CPR; //0xf4 + __IO uint32_t UCV; + __IO uint32_t CTR; +} AP_UART_TypeDef; + + +/*------------- Inter-Integrated Circuit (I2C) setup by zjp-------------------------------*/ +typedef struct +{ + __IO uint32_t IC_CON; + __IO uint32_t IC_TAR; + __IO uint32_t IC_SAR; + __IO uint32_t IC_HS_MADDR; + __IO uint32_t IC_DATA_CMD; //0x10 + __IO uint32_t IC_SS_SCL_HCNT; + __IO uint32_t IC_SS_SCL_LCNT; + __IO uint32_t IC_FS_SCL_HCNT; + __IO uint32_t IC_FS_SCL_LCNT; //0x20 + __IO uint32_t IC_HS_SCL_HCNT; + __IO uint32_t IC_HS_SCL_LCNT; + __IO uint32_t IC_INTR_STAT; + __IO uint32_t IC_INTR_MASK; //0x30 + __IO uint32_t IC_RAW_INTR_STAT; + __IO uint32_t IC_RX_TL; + __IO uint32_t IC_TX_TL; + __IO uint32_t IC_CLR_INTR; //0x40 + __IO uint32_t IC_CLR_UNDER; + __IO uint32_t IC_CLR_RX_OVER; + __IO uint32_t IC_CLR_TX_OVER; + __IO uint32_t IC_CLR_RD_REG; //0x50 + __IO uint32_t IC_CLR_TX_ABRT; + __IO uint32_t IC_CLR_RX_DONE; + __IO uint32_t IC_CLR_ACTIVITY; + __IO uint32_t IC_CLR_STOP_DET; //0x60 + __IO uint32_t IC_CLR_START_DET; + __IO uint32_t IC_CLR_GEN_CALL; + __IO uint32_t IC_ENABLE; + __IO uint32_t IC_STATUS; //0x70 + __IO uint32_t IC_TXFLR; + __IO uint32_t IC_RXFLR; + __IO uint32_t IC_SDA_HOLD; + __IO uint32_t IC_TX_ABRT_SOURCE; //0x80 + __IO uint32_t IC_SLV_DATA_NACK_ONLY; + __IO uint32_t IC_DMA_CR; + __IO uint32_t IC_DMA_TDLR; + __IO uint32_t IC_DMA_RDLR; //0x90 + __IO uint32_t IC_SDA_SETUP; + __IO uint32_t IC_ACK_GENERAL_CALL; + __IO uint32_t IC_ENABLE_STATUS; + __IO uint32_t IC_FS_SPKLEN; //0xa0 + __IO uint32_t IC_HS_SPKLEN; + +} AP_I2C_TypeDef; + + +/*------------- Inter IC Sound (I2S) -----------------------------------------*/ +typedef struct +{ + __IO uint32_t IER; + __IO uint32_t IRER; + __IO uint32_t ITER; + __IO uint32_t CER; + __IO uint32_t CCR; + __IO uint32_t RXFFR; + __IO uint32_t TXFFR; + +} AP_I2S_BLOCK_TypeDef; + +typedef struct +{ + union + { + __IO uint32_t LRBR; //0x20 + __IO uint32_t LTHR; //0x20 + }; + union + { + __IO uint32_t RRBR; // 0x24 + __IO uint32_t RTHR; //0x24 + }; + __IO uint32_t RER; //0x28 + __IO uint32_t TER; //0x2c + __IO uint32_t RCR; //0x30 + __IO uint32_t TCR; //0x34 + __IO uint32_t ISR; //0x38 + __IO uint32_t IMR; //0x3c + __IO uint32_t ROR; //0x40 + __IO uint32_t TOR; //0x44 + __IO uint32_t RFCR; //0x48 + __IO uint32_t TFCR; //0x4c + __IO uint32_t RFF; //0x50 + __IO uint32_t TFF; //0x54 + +} AP_I2S_TypeDef; + + +/*------------- General Purpose Input/Output (GPIO) --------------------------*/ +typedef struct +{ + __IO uint32_t swporta_dr; //0x00 + __IO uint32_t swporta_ddr; //0x04 + __IO uint32_t swporta_ctl; //0x08 + uint32_t reserved8[9]; //0x18-0x2c portC&D + __IO uint32_t inten; //0x30 + __IO uint32_t intmask; //0x34 + __IO uint32_t inttype_level; //0x38 + __IO uint32_t int_polarity; //0x3c + __I uint32_t int_status; //0x40 + __IO uint32_t raw_instatus; //0x44 + __IO uint32_t debounce; //0x48 + __O uint32_t porta_eoi; //0x4c + __I uint32_t ext_porta; //0x50 + uint32_t reserved9[3]; //0x58 0x5c + __IO uint32_t ls_sync; //0x60 + __I uint32_t id_code; //0x64 + uint32_t reserved10[1]; //0x68 + __I uint32_t ver_id_code; //0x6c + __I uint32_t config_reg2; //0x70 + __I uint32_t config_reg1; //0x74 +} AP_GPIO_TypeDef; + + +/*-------------------- (SPI) --------------------------------*/ +typedef struct +{ + __IO uint16_t CR0; //0x0 /*!< Offset: 0x000 Control Register 0 (R/W) */ + uint16_t reserved1; + __IO uint16_t CR1; //0x04 /*!< Offset: 0x004 Control Register 1 (R/W) */ + uint16_t reserved2; + __IO uint8_t SSIEN; //0x08 + uint8_t reserved3[3]; + __IO uint8_t MWCR; // 0x0c + uint8_t reserved4[3]; + __IO uint8_t SER; //0x10 + uint8_t reserved5[3]; + __IO uint32_t BAUDR; //0x14 + __IO uint32_t TXFTLR; //0x18 + __IO uint32_t RXFTLR; //0x1c + __O uint32_t TXFLR; //0x20 + __O uint32_t RXFLR; //0x24 + + __IO uint8_t SR; //0x28 + uint8_t reserved7[3]; + __IO uint32_t IMR; //0x2c + __IO uint32_t ISR; //0x30 + __IO uint32_t RISR; //0x34 + __IO uint32_t TXOICR; //0x38 + __IO uint32_t RXOICR; //0x3c + __IO uint32_t RXUICR; //0x40 + __IO uint32_t MSTICR; //0x44 + __IO uint32_t ICR; //0x48 + __IO uint32_t DMACR; //0x4c + __IO uint32_t DMATDLR; //0x50 + __IO uint32_t DMARDLR; //0x54 + __IO uint32_t IDR; //0x5c + __IO uint32_t SSI_COM_VER; //0x5c + __IO uint32_t DataReg; + +} AP_SSI_TypeDef; + + +typedef struct +{ + __IO uint32_t Analog_IO_en;//0x00 + __IO uint32_t SPI_debug_en;//0x04 + __IO uint32_t debug_mux_en;//0x08 + __IO uint32_t full_mux0_en;//0x0c + __IO uint32_t full_mux1_en;//0x10 reserved in some soc + __IO uint32_t gpio_pad_en; //0x14 + __IO uint32_t gpio_sel[9]; //0x18 + __IO uint32_t pad_pe0;//0x3c + __IO uint32_t pad_pe1;//0x40 + __IO uint32_t pad_ps0;//0x44 + __IO uint32_t pad_ps1;//0x48 + __IO uint32_t keyscan_in_en;//0x4c + __IO uint32_t keyscan_out_en;//0x50 +} IOMUX_TypeDef; + + +// 0x4000f05C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k +// 0x4000f064 - RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle +// uint32_t counter_tracking // 24bit tracking counter, read from 0x4000f064 +// counter_tracking = g_counter_traking_avg = STD_RC32_16_CYCLE_16MHZ_CYCLE; hal_rc32k_clk_tracking_init() +// 0x4000f0C0 - SLEEP_R[0] flags =2 RSTC_OFF_MODE, =4 RSTC_WARM_NDWC +// 0x4000f0C4 - SLEEP_R[1] bit7 - first wakeupinit, tracking flags +// 0x4000f0C8 - SLEEP_R[2] использую для сохранения UTC счета времени при перезагрузке +// 0x4000f0CС - SLEEP_R[3] использую для сохранения UTC счета времени при перезагрузке + +typedef struct +{ + __IO uint32_t PWROFF; //0x00 = 0x5a5aa5a5 enter system off mode + __IO uint32_t PWRSLP; //0x04 = 0xa5a55a5a system sleep mode + __IO uint32_t IOCTL[3]; //0x08 0x0c 0x10 + __IO uint32_t PMCTL0; //0x14 + __IO uint32_t PMCTL1; //0x18 + __IO uint32_t PMCTL2_0; //0x1c bit6 enable software control 32k_clk + __IO uint32_t PMCTL2_1; //0x20 + __IO uint32_t RTCCTL; //0x24 bit20 - enable comparator0 envent, bit18 counter overflow interrupt, bit15 enable comparator0 inerrupt, + __IO uint32_t RTCCNT; //0x28 current RTC counter + __IO uint32_t RTCCC0; //0x2c + __IO uint32_t RTCCC1; //0x30 + __IO uint32_t RTCCC2; //0x34 + __IO uint32_t RTCFLAG; //0x38 + __IO uint32_t RTCCLK0; //0x3C bit3:0 = sysclk_t: 1 dll 32m, 2 xtal 16m, 3 dll 48m, 4 dll 64m, 5 dll 96m + __IO uint32_t RTCCLK1; //0x40 bit18 - xtal output to digital enable + __IO uint32_t RTCCFG1; //0x44 - [bit16] enable digclk 96M, [bit7] enable DLL, 25:24 g_rxAdcClkSel 26:25 sel_rxadc_dbl_clk_32M_polarity, 23:22 g_rfPhyClkSel, 6:5 trim dll/dbl ldo vout + __IO uint32_t reserved0[5]; //0x48 4c 50 54 58 + __IO uint32_t RTCCFG2; //0x5C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k + __IO uint32_t reserved1; //0x60 + __IO uint32_t RTCTRCCNT; //0x64 RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle, counter_tracking_wakeup + __IO uint32_t RTCTRCNT; //0x68 + __IO uint32_t reserved2[13]; //0x6c 70 74 78 7c 80 84 88 8c 90 94 98 9c + __IO uint32_t REG_S9; //0xa0 + __IO uint32_t REG_S10; //0xa4 + __IO uint32_t REG_S11; //0xa8 bit0 sleep_flag + __IO uint32_t IDLE_REG; //0xac + __IO uint32_t GPIO_WAKEUP_SRC[2]; //0xb0 b4 + __IO uint32_t PCLK_CLK_GATE; //0xb8 bit0 pclk_clk_gate_en + __IO uint32_t XTAL_16M_CTRL; //0xbc + __IO uint32_t SLEEP_R[4]; //0xc0 c4 c8 cc + +} AP_AON_TypeDef; + + +typedef struct +{ + __IO uint32_t RTCCTL; //0x24 + __IO uint32_t RTCCNT; //0x28 + __IO uint32_t RTCCC0; //0x2c + __IO uint32_t RTCCC1; //0x30 + __IO uint32_t RTCCC2; //0x34 + __IO uint32_t RTCFLAG; //0x38 +} AP_RTC_TypeDef; + +typedef struct +{ + __IO uint32_t io_wu_mask_31_0; //0xa0 + __IO uint32_t io_wu_mask_34_32; //0xa4 +} AP_Wakeup_TypeDef; + +typedef struct +{ + __IO uint32_t CLKSEL; //0x3c + __IO uint32_t CLKHF_CTL0; //0x40 + __IO uint32_t CLKHF_CTL1; //0x44 + __IO uint32_t ANA_CTL; //0x48 + __IO uint32_t mem_0_1_dvs; //0x4c + __IO uint32_t mem_2_3_4_dvs; //0x50 + __IO uint32_t efuse_cfg; //0x54 + __IO uint32_t chip_state; //0x58 + __IO uint32_t cal_rw; //0x5c + __IO uint32_t cal_ro0; //0x60 + __IO uint32_t cal_ro1; //0x64 + __IO uint32_t cal_ro2; //0x68 + __IO uint32_t ADC_CTL0; //0x6c + __IO uint32_t ADC_CTL1; //0x70 + __IO uint32_t ADC_CTL2; //0x74 + __IO uint32_t ADC_CTL3; //0x78 + __IO uint32_t ADC_CTL4; //0x7c + uint32_t reserved1[48]; + __IO uint32_t EFUSE_PROG[2];//0x140 + uint32_t reserved2[6]; + __IO uint32_t EFUSE0[2];//0x160 + __IO uint32_t EFUSE1[2];//0x168 + __IO uint32_t EFUSE2[2];//0x170 + __IO uint32_t EFUSE3[2];//0x178 + __IO uint32_t SECURTY_STATE;//0x180 +} AP_PCRM_TypeDef; + +typedef struct +{ + __IO uint32_t enable; //0x00 + __IO uint32_t reserve0[2]; //0x04~0x08 + __IO uint32_t control_1; //0x0c + __IO uint32_t control_2; //0x10 + __IO uint32_t control_3; //0x14 + __IO uint32_t control_4; //0x18 + __IO uint32_t compare_reset; //0x1c + __IO uint32_t int_pointer_ch0_ch3; //0x20 + __IO uint32_t int_pointer_ch4_ch7; //0x24 + //__IO uint32_t int_pointer[2]; //0x20~0x24 + __IO uint32_t reserve1[3]; //0x28~0x30 + __IO uint32_t intr_mask; //0x34 + __IO uint32_t intr_clear; //0x38 + __IO uint32_t intr_status; //0x3c + __IO uint32_t compare_cfg[8]; //0x40~0x5c +} AP_ADCC_TypeDef; + +typedef struct +{ + __IO uint32_t config; //0x0,QSPI Configuration Register,R/W + __IO uint32_t read_instr; //0x4,Device Read Instruction Register,R/W + __IO uint32_t write_instr; //0x8,Device Write Instruction Register,R/W + __IO uint32_t delay; //0xC,QSPI Device Delay Register,R/W + __IO uint32_t rddata_capture; //0x10,Read Data Capture Register,R/W + __IO uint32_t dev_size; //0x14,Device Size Register,R/W + __IO uint32_t sram_part; //0x18,SRAM Partition Register,R/W + __IO uint32_t indirect_ahb_addr_trig; //0x1C,Indirect AHB Address Trigger Register,R/W + __IO uint32_t dma_peripheral; //0x20,DMA Peripheral Register,R/W + __IO uint32_t remap; //0x24,Remap Address Register,R/W + __IO uint32_t mode_bit; //0x28,Mode Bit Register,R/W + __IO uint32_t sram_fill_level; //0x2C,SRAM Fill Level Register,RO + __IO uint32_t tx_threshold; //0x30,TX Threshold Register,R/W + __IO uint32_t rx_threshold; //0x34,RX Threshold Register,R/W + __IO uint32_t wr_completion_ctrl; //0x38,Write Completion Control Register,R/W + __IO uint32_t poll_expire; //0x3C,Polling Expiration Register,R/W + __IO uint32_t int_status; //0x40,Interrupt Status Register,R/W + __IO uint32_t int_mask; //0x44,Interrupt Mask,R/W + __I uint32_t n1[2]; //0x48~0x4c,Empty + __IO uint32_t low_wr_protection; //0x50,Lower Write Protection Register,R/W + __IO uint32_t up_wr_protection; //0x54,Upper Write Protection Register,R/W + __IO uint32_t wr_protection; //0x58,Write Protection Register,R/W + __I uint32_t n2; //0x5c,Empty + __IO uint32_t indirect_rd; //0x60,Indirect Read Transfer Register,R/W + __IO uint32_t indirect_rd_watermark; //0x64,Indirect Read Transfer Watermark Register,R/W + __IO uint32_t indirect_rd_start_addr; //0x68,Indirect Read Transfer Start Address Register,R/W + __IO uint32_t indirect_rd_num; //0x6C,Indirect Read Transfer Number Bytes Register,R/W + __IO uint32_t indirect_wr; //0x70,Indirect Write Transfer Register,R/W + __IO uint32_t indirect_wr_watermark; //0x74,Indirect Write Transfer Watermark Register,R/W + __IO uint32_t indirect_wr_start_addr; //0x78,Indirect Write Transfer Start Address Register,R/W + __IO uint32_t indirect_wr_cnt; //0x7C,Indirect Write Transfer Count Register,R/W + __IO uint32_t indirect_ahb_trig_addr_range; //0x80,Indirect AHB Trigger Address Range Register,R/W + __I uint32_t n3[3]; //0x84~0x8c,Empty + __IO uint32_t fcmd; //0x90,Flash Command Register,R/W + __IO uint32_t fcmd_addr; //0x94,Flash Command Address Registers,R/W + __I uint32_t n4[2]; //0x98~0x9c,Empty + __IO uint32_t fcmd_rddata[2]; //0xA0,Flash Command Read Data Register (low-a0, up-a4),RO + __IO uint32_t fcmd_wrdata[2]; //0xA8,Flash Command Write Data Register (low-a8, up-ac),R/W + __IO uint32_t poll_fstatus; //0xB0,Polling Flash Status Register,RO + //__IO uint32_t ; //0xFC,Module ID Register,RO +} AP_SPIF_TypeDef; + +typedef struct +{ + __IO uint32_t ctrl0; //0xc0 + __IO uint32_t ctrl1; //0xc4 + __IO uint32_t mk_in_en; //0xc8 + __IO uint32_t mkc[6]; //0xcc~0xe0 +} AP_KSCAN_TypeDef; + +typedef struct +{ + __IO uint32_t pwmen; +} AP_PWM_TypeDef; + + +typedef struct +{ + __IO uint32_t ctrl0; + __IO uint32_t ctrl1; +} AP_PWMCTRL_TypeDef; + + + +typedef struct +{ + __IO uint32_t SAR; + __IO uint32_t SAR_H; + __IO uint32_t DAR; + __IO uint32_t DAR_H; + __IO uint32_t LLP; + __IO uint32_t LLP_H; + __IO uint32_t CTL; + __IO uint32_t CTL_H; + __IO uint32_t SSTAT; + __IO uint32_t SSTAT_H; + __IO uint32_t DSTAT; + __IO uint32_t DSTAT_L; + __IO uint32_t SSTATAR; + __IO uint32_t SSTATAR_H; + __IO uint32_t DSTATAR; + __IO uint32_t DSTATAR_H; + __IO uint32_t CFG; + __IO uint32_t CFG_H; + __IO uint32_t rsv[4]; + +} AP_DMA_CH_TypeDef; + +typedef struct +{ + + __IO uint32_t RawTfr; //0x2c0 + __IO uint32_t RawTfr_H; //0x2c4 + __IO uint32_t RawBlock; //0x2c8 + __IO uint32_t RawBlock_H; //0x2cc + __IO uint32_t RawSrcTran; //0x2d0 + __IO uint32_t RawSrcTran_H; //0x2d4 + __IO uint32_t RawDstTran; //0x2d8 + __IO uint32_t RawDstTran_H; //0x2dc + __IO uint32_t RawErr; //0x2e0 + __IO uint32_t RawErr_H; //0x2e4 + + __IO uint32_t StatusTfr; //0x2e8 + __IO uint32_t StatusTfr_H; //0x2ec + __IO uint32_t StatusBlock; //0x2f0 + __IO uint32_t StatusBlock_H; //0x2f4 + __IO uint32_t StatusSrcTran; //0x2f8 + __IO uint32_t StatusSrcTran_H; //0x2fc + __IO uint32_t StatusDstTran; //0x300 + __IO uint32_t StatusDstTran_H; //0x304 + __IO uint32_t StatusErr; //0x308 + __IO uint32_t StatusErr_H; //0x30c + + __IO uint32_t MaskTfr; //0x310 + __IO uint32_t MaskTfr_H; //0x314 + __IO uint32_t MaskBlock; //0x318 + __IO uint32_t MaskBlock_H; //0x31c + __IO uint32_t MaskSrcTran; //0x320 + __IO uint32_t MaskSrcTran_H; //0x324 + __IO uint32_t MaskDstTran; //0x328 + __IO uint32_t MaskDstTran_H; //0x32c + __IO uint32_t MaskErr; //0x330 + __IO uint32_t MaskErr_H; //0x334 + + __IO uint32_t ClearTfr; //0x338 + __IO uint32_t ClearTfr_H; //0x33c + __IO uint32_t ClearBlock; //0x340 + __IO uint32_t ClearBlock_H; //0x344 + __IO uint32_t ClearSrcTran; //0x348 + __IO uint32_t ClearSrcTran_H; //0x34c + __IO uint32_t ClearDstTran; //0x350 + __IO uint32_t ClearDstTran_H; //0x354 + __IO uint32_t ClearErr; //0x358 + __IO uint32_t ClearErr_H; //0x35c + __IO uint32_t StatusInt; //0x360 + __IO uint32_t StatusInt_H; //0x364 + +} AP_DMA_INT_TypeDef; + +typedef struct +{ + __IO uint32_t ReqSrcReg; //0x368 + __IO uint32_t ReqSrcReg_H; //0x36c + __IO uint32_t ReqDstReg; //0x370 + __IO uint32_t ReqDstReg_H; //0x374 + __IO uint32_t SglReqSrcReg; //0x378 + __IO uint32_t SglReqSrcReg_H; //0x37c + __IO uint32_t SglReqDstReg; //0x380 + __IO uint32_t SglReqDstReg_H; //0x384 + __IO uint32_t LstSrcReg; //0x388 + __IO uint32_t LstSrcReg_H; //0x38c + __IO uint32_t LstDstReg; //0x390 + __IO uint32_t LstDstReg_H; //0x394 + +} AP_DMA_SW_HANDSHAKE_TypeDef; + +typedef struct +{ + __IO uint32_t DmaCfgReg; //0x398 + __IO uint32_t DmaCfgReg_H; //0x39c + __IO uint32_t ChEnReg; //0x3a0 + __IO uint32_t ChEnReg_H; //0x3a4 + __IO uint32_t DmaIdReg; //0x3a8 + __IO uint32_t DmaIdReg_H; //0x3ac + __IO uint32_t DmaTestReg; //0x3b0 + __IO uint32_t DmaTestReg_H; //0x3b4 + __IO uint32_t rsv1[4]; + __IO uint32_t DMA_COMP_PARAMS_6; //0x3c8 + __IO uint32_t DMA_COMP_PARAMS_6_H; //0x3cc + __IO uint32_t DMA_COMP_PARAMS_5; //0x3d0 + __IO uint32_t DMA_COMP_PARAMS_5_H; //0x3d4 + __IO uint32_t DMA_COMP_PARAMS_4; //0x3d8 + __IO uint32_t DMA_COMP_PARAMS_4_H; //0x3dc + __IO uint32_t DMA_COMP_PARAMS_3; //0x3e0 + __IO uint32_t DMA_COMP_PARAMS_3_H; //0x3e4 + __IO uint32_t DMA_COMP_PARAMS_2; //0x3e8 + __IO uint32_t DMA_COMP_PARAMS_2_H; //0x3ec + __IO uint32_t DMA_COMP_PARAMS_1; //0x3f0 + __IO uint32_t DMA_COMP_PARAMS_1_H; //0x3f4 + __IO uint32_t DMA_ID; //0x3f8 + __IO uint32_t DMA_ID_H; //0x3fc +} AP_DMA_MISC_TypeDef; + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + + +/******************************************************************************/ +/* Peripheral memory map(AP) */ +/******************************************************************************/ +/* Base addresses */ +#define AP_APB0_BASE (0x40000000UL) +#define SPIF_BASE_ADDR (0x11000000) /*spif*/ + +#define AP_PCR_BASE (AP_APB0_BASE + 0x0000)/*pcr*//* APB0 peripherals */ + +#define AP_TIM1_BASE (AP_APB0_BASE + 0x1000) +#define AP_TIM2_BASE (AP_APB0_BASE + 0x1014) +#define AP_TIM3_BASE (AP_APB0_BASE + 0x1028) +#define AP_TIM4_BASE (AP_APB0_BASE + 0x103c) +#define AP_TIM5_BASE (AP_APB0_BASE + 0x1050) +#define AP_TIM6_BASE (AP_APB0_BASE + 0x1064) +#define AP_TIM_SYS_BASE (AP_APB0_BASE + 0x10a0) + +#define AP_WDT_BASE (AP_APB0_BASE + 0x2000) +#define AP_COM_BASE (AP_APB0_BASE + 0x3000)/*com*/ +#define AP_IOMUX_BASE (AP_APB0_BASE + 0x3800)/*iomux*/ +#define AP_UART0_BASE (AP_APB0_BASE + 0x4000)/*uart0*/ +#define AP_I2C0_BASE (AP_APB0_BASE + 0x5000)/*i2c0*/ +#define AP_I2C1_BASE (AP_APB0_BASE + 0x5800)/*i2c1*/ +#define AP_SPI0_BASE (AP_APB0_BASE + 0x6000)/*spi0*/ +#define AP_SPI1_BASE (AP_APB0_BASE + 0x7000)/*spi1*/ +#define AP_GPIOA_BASE (AP_APB0_BASE + 0x8000)/*gpio*/ +#define AP_UART1_BASE (AP_APB0_BASE + 0x9000)/*uart1*/ +#define AP_DMIC_BASE (AP_APB0_BASE + 0xA000) +#define AP_QDEC_BASE (AP_APB0_BASE + 0xB000)/*qdec*/ +#define AP_CACHE_BASE (AP_APB0_BASE + 0xC000) +#define AP_SPIF_BASE (AP_APB0_BASE + 0xC800)/*spif*/ +#define AP_KSCAN_BASE (AP_APB0_BASE + 0xD0C0)/*kscan*/ +#define AP_PWM_BASE (AP_APB0_BASE + 0xE000)/*pwm*/ +#define AP_AON_BASE (AP_APB0_BASE + 0xF000)/*aon*/ +#define AP_RTC_BASE (AP_APB0_BASE + 0xF024)/*rtc*/ +#define AP_PCRM_BASE (AP_APB0_BASE + 0xF03c)/*pcrm*/ +#define AP_WAKEUP_BASE (AP_APB0_BASE + 0xF0a0)/*wakeup*/ +#define AP_DMAC_BASE (AP_APB0_BASE + 0x10000)/*dmac*/ +#define ADCC_BASE_ADDR (AP_APB0_BASE + 0x50000)/*adcc*/ + +/*bb_top*/ +/*linklayer*/ + +#define SRAM0_BASE_ADDRESS 0x1FFF0000 +#define SRAM1_BASE_ADDRESS 0x1FFF4000 +#define SRAM2_BASE_ADDRESS 0x1FFF8000 + + +///////////////////////////////////////////////////////////// +#define AP_PCR ((AP_PCR_TypeDef *) AP_PCR_BASE) + +#define AP_TIM1 ((AP_TIM_TypeDef *) AP_TIM1_BASE) +#define AP_TIM2 ((AP_TIM_TypeDef *) AP_TIM2_BASE) +#define AP_TIM3 ((AP_TIM_TypeDef *) AP_TIM3_BASE) +#define AP_TIM4 ((AP_TIM_TypeDef *) AP_TIM4_BASE) +#define AP_TIM5 ((AP_TIM_TypeDef *) AP_TIM5_BASE) +#define AP_TIM6 ((AP_TIM_TypeDef *) AP_TIM6_BASE) +#define AP_TIMS ((AP_TIM_SYS_TypeDef *) AP_TIM_SYS_BASE) + +#define AP_WDT ((AP_WDT_TypeDef *) AP_WDT_BASE) +#define AP_COM ((AP_COM_TypeDef *) AP_COM_BASE) +#define AP_IOMUX ((IOMUX_TypeDef *) AP_IOMUX_BASE) +#define AP_UART0 ((AP_UART_TypeDef *) AP_UART0_BASE) +#define AP_I2C0 ((AP_I2C_TypeDef *) AP_I2C0_BASE) +#define AP_I2C1 ((AP_I2C_TypeDef *) AP_I2C1_BASE) +#define AP_SPI0 ((AP_SSI_TypeDef *) AP_SPI0_BASE) +#define AP_SPI1 ((AP_SSI_TypeDef *) AP_SPI1_BASE) +#define AP_GPIO ((AP_GPIO_TypeDef *) AP_GPIOA_BASE) +#define AP_UART1 ((AP_UART_TypeDef *) AP_UART1_BASE) +#define AP_CACHE ((AP_CACHE_TypeDef *) AP_CACHE_BASE) +#define AP_SPIF ((AP_SPIF_TypeDef *) AP_SPIF_BASE) +#define AP_KSCAN ((AP_KSCAN_TypeDef *) AP_KSCAN_BASE) +#define AP_PWM ((AP_PWM_TypeDef *) AP_PWM_BASE) +#define AP_PWM_CTRL(n) ((AP_PWMCTRL_TypeDef *) (AP_PWM_BASE + 4 + n*12)) +#define AP_AON ((AP_AON_TypeDef *) AP_AON_BASE) +#define AP_RTC ((AP_RTC_TypeDef *) AP_RTC_BASE) +#define AP_PCRM ((AP_PCRM_TypeDef *) AP_PCRM_BASE) +#define AP_WAKEUP ((AP_Wakeup_TypeDef*) AP_WAKEUP_BASE) +#define AP_ADCC ((AP_ADCC_TypeDef *) ADCC_BASE_ADDR) + +#define AP_DMA_CH_CFG(n) ((AP_DMA_CH_TypeDef *) (AP_DMAC_BASE+0x58*n)) +#define AP_DMA_INT ((AP_DMA_INT_TypeDef *) (AP_DMAC_BASE+0x2c0)) +#define AP_DMA_SW_HANDSHAKE ((AP_DMA_SW_HANDSHAKE_TypeDef *) (AP_DMAC_BASE+0x368)) +#define AP_DMA_MISC ((AP_DMA_MISC_TypeDef *) (AP_DMAC_BASE+0x398)) +/* + watchdog enable state,enable or not. +*/ +#define AP_WDT_ENABLE_STATE ((AP_WDT->CR & 0x01))//1:enable 0:disable +#define AP_WDT_FEED do{AP_WDT->CRR = 0x76;}while(0) + +/******************************************************************************/ +/* Peripheral memory map(CP) */ +/******************************************************************************/ +/* Base addresses */ +#define IRQ_PRIO_REALTIME 0 +#define IRQ_PRIO_HIGH 1 +#define IRQ_PRIO_HAL 2 +#define IRQ_PRIO_THREAD 3 +#define IRQ_PRIO_APP 3 + + +#endif diff --git a/ota_boot/source/include/types.h b/ota_boot/source/include/types.h new file mode 100644 index 0000000..541526a --- /dev/null +++ b/ota_boot/source/include/types.h @@ -0,0 +1,156 @@ + +#ifndef _TYPES_H_ +#define _TYPES_H_ + +#include +#include +typedef signed char int8; //!< Signed 8 bit integer +typedef unsigned char uint8; //!< Unsigned 8 bit integer + +typedef signed short int16; //!< Signed 16 bit integer +typedef unsigned short uint16; //!< Unsigned 16 bit integer + +typedef signed long int32; //!< Signed 32 bit integer +typedef unsigned long uint32; //!< Unsigned 32 bit integer + +typedef uint8 halDataAlign_t; //!< Used for byte alignment + +#ifdef __GCC + #define ALIGN4_U8 _Alignas(4) uint8 + #define ALIGN4_U16 _Alignas(4) uint16 + #define ALIGN4_INT8 _Alignas(4) int8 + #define ALIGN4_INT16 _Alignas(4) int16 +#else + #define ALIGN4_U8 __align(4) uint8 + #define ALIGN4_U16 __align(4) uint16 + #define ALIGN4_INT8 __align(4) int8 + #define ALIGN4_INT16 __align(4) int16 +#endif + +#define BIT(n) (1ul << (n)) + +#define write_reg(addr,data) (*(volatile unsigned int *)(addr)=(unsigned int)(data)) +#define read_reg(addr) (*(volatile unsigned int *)(addr)) + +//bit operations +#define BM_SET(addr,bit) ( *(addr) |= (bit) ) //bit set +#define BM_CLR(addr,bit) ( *(addr) &= ~(bit) ) //bit clear +#define BM_IS_SET(addr,bit) ( *(addr) & (bit) ) //judge bit is set + + + +#ifndef BV + #define BV(n) (1 << (n)) +#endif + +#ifndef BF + #define BF(x,b,s) (((x) & (b)) >> (s)) +#endif + +#ifndef MIN + #define MIN(n,m) (((n) < (m)) ? (n) : (m)) +#endif + +#ifndef MAX + #define MAX(n,m) (((n) < (m)) ? (m) : (n)) +#endif + +#ifndef ABS + #define ABS(n) (((n) < 0) ? -(n) : (n)) +#endif + + +/* takes a byte out of a uint32 : var - uint32, ByteNum - byte to take out (0 - 3) */ +#define BREAK_UINT32( var, ByteNum ) \ + (uint8)((uint32)(((var) >>((ByteNum) * 8)) & 0x00FF)) + +#define BUILD_UINT32(Byte0, Byte1, Byte2, Byte3) \ + ((uint32)((uint32)((Byte0) & 0x00FF) \ + + ((uint32)((Byte1) & 0x00FF) << 8) \ + + ((uint32)((Byte2) & 0x00FF) << 16) \ + + ((uint32)((Byte3) & 0x00FF) << 24))) + +#define BUILD_UINT16(loByte, hiByte) \ + ((uint16)(((loByte) & 0x00FF) + (((hiByte) & 0x00FF) << 8))) + +#define HI_UINT16(a) (((a) >> 8) & 0xFF) +#define LO_UINT16(a) ((a) & 0xFF) + +#define BUILD_UINT8(hiByte, loByte) \ + ((uint8)(((loByte) & 0x0F) + (((hiByte) & 0x0F) << 4))) + + +// Write the 32bit value of 'val' in little endian format to the buffer pointed +// to by pBuf, and increment pBuf by 4 +#define UINT32_TO_BUF_LITTLE_ENDIAN(pBuf,val) \ + do { \ + *(pBuf)++ = (((val) >> 0) & 0xFF); \ + *(pBuf)++ = (((val) >> 8) & 0xFF); \ + *(pBuf)++ = (((val) >> 16) & 0xFF); \ + *(pBuf)++ = (((val) >> 24) & 0xFF); \ + } while (0) + +// Return the 32bit little-endian formatted value pointed to by pBuf, and increment pBuf by 4 +#define BUF_TO_UINT32_LITTLE_ENDIAN(pBuf) (((pBuf) += 4), BUILD_UINT32((pBuf)[-4], (pBuf)[-3], (pBuf)[-2], (pBuf)[-1])) + +#ifndef GET_BIT + #define GET_BIT(DISCS, IDX) (((DISCS)[((IDX) / 8)] & BV((IDX) % 8)) ? TRUE : FALSE) +#endif +#ifndef SET_BIT + #define SET_BIT(DISCS, IDX) (((DISCS)[((IDX) / 8)] |= BV((IDX) % 8))) +#endif +#ifndef CLR_BIT + #define CLR_BIT(DISCS, IDX) (((DISCS)[((IDX) / 8)] &= (BV((IDX) % 8) ^ 0xFF))) +#endif + + +/* ------------------------------------------------------------------------------------------------ + Standard Defines + ------------------------------------------------------------------------------------------------ +*/ +#ifndef TRUE + #define TRUE 1 +#endif + +#ifndef FALSE + #define FALSE 0 +#endif + +#ifndef NULL + #define NULL 0 +#endif + +#define HAL_WAIT_CONDITION(condition) {while(!(condition)){}} + + +#define HAL_WAIT_CONDITION_TIMEOUT(condition, timeout) {\ + volatile int val = 0;\ + while(!(condition)){\ + if(val ++ > timeout)\ + return PPlus_ERR_TIMEOUT;\ + }\ + } + +#define HAL_WAIT_CONDITION_TIMEOUT_WO_RETURN(condition, timeout) {\ + volatile int val = 0;\ + while(!(condition)){\ + if(val ++ > timeout)\ + break;\ + }\ + } + + +typedef struct _comm_evt_t +{ + unsigned int type; + unsigned char* data; + unsigned int len; +} comm_evt_t; + +typedef void (*comm_cb_t)(comm_evt_t* pev); + +#define __ATTR_SECTION_SRAM__ __attribute__((section("_section_sram_code_"))) +#define __ATTR_SECTION_XIP__ __attribute__((section("_section_xip_code_"))) + +#endif + diff --git a/ota_boot/source/main.c b/ota_boot/source/main.c new file mode 100644 index 0000000..d92c469 --- /dev/null +++ b/ota_boot/source/main.c @@ -0,0 +1,124 @@ +/* + main.c +*/ +#include +#include "global_config.h" +#include "rom_sym_def.h" +#include "ota_boot.h" +#include "bus_dev.h" + + +/*******************************************************************************/ +extern int m_in_critical_region; +extern const uint32_t _sbss; +extern const uint32_t _ebss; + +/**************************************************************************** + Name: c_start + + Description: + This is the reset entry point. + + ****************************************************************************/ + +#define WR_BLK_SIZE 256 + +/* Заголовок OTA */ +typedef struct _app_info_t { + uint32_t flag; // id = START_UP_FLAG + uint32_t seg_count; // кол-во сегментов + uint32_t start_addr; // стартовый/run адрес (if = -1 -> берестя из первого значения != -1 у сегмента) + uint32_t app_size; // размер OTA без 4-х байт CRC32 +} app_info_t; + +app_info_t info_app; + +/* Описание сегментов OTA */ +typedef struct _app_info_seg_t { + uint32_t faddr; // адрес записи в Flash + uint32_t size; // размер сегмента + uint32_t waddr; // рабочий адрес + uint32_t chk; // не используется +} app_info_seg_t; + +app_info_seg_t seg_info; + +uint8_t sector_buf[WR_BLK_SIZE]; + +__attribute__ ((naked)) +void copy_app_code(void) { + uint32_t blksize = WR_BLK_SIZE; + uint32_t rfaddr = FADDR_APP_SEC + 0xfc; + uint32_t dfaddr = 0; + uint32_t wfaddr = FADDR_BOOT_ROM_INFO; + uint32_t count; + __disable_irq(); + spif_read(rfaddr, (uint8_t*)&rfaddr, 4); + spif_read(rfaddr, (uint8_t*)&info_app, sizeof(info_app)); + if(info_app.flag == START_UP_FLAG + && info_app.seg_count + && info_app.seg_count < 16 + && info_app.app_size < FADDR_APP_SEC - FADDR_OTA_SEC + ){ + dfaddr = rfaddr + 0x100; + count = info_app.seg_count; + spif_erase_sector(wfaddr); + spif_write(wfaddr, (uint8_t*)&info_app.seg_count, 4); + spif_write(wfaddr + 8, (uint8_t*)&info_app.start_addr, 4); + wfaddr += 0x100; + while(count--) { + rfaddr += 16; + spif_read(rfaddr, (uint8_t*)&seg_info, 12); + spif_write(wfaddr, (uint8_t*)&seg_info, 12); + wfaddr += 16; + } + wfaddr = FADDR_OTA_SEC; + count = info_app.app_size; + while(count) { + if(count < WR_BLK_SIZE) + blksize = count; + if((wfaddr & (FLASH_SECTOR_SIZE - 1)) == 0) + spif_erase_sector(wfaddr); + spif_read(dfaddr, sector_buf, blksize); + spif_write(wfaddr, sector_buf, blksize); + dfaddr += blksize; + wfaddr += blksize; + count -= blksize; + } + spif_erase_sector(FADDR_APP_SEC); + } + //__disable_irq(); + m_in_critical_region++; + /** + config reset casue as RSTC_WARM_NDWC + reset path walkaround dwc + */ + AP_AON->RTCCC2 = BOOT_FLG_OTA; // [0x4000f034] == 0x55 -> OTA + AP_AON->SLEEP_R[0] = 4; + AP_AON->SLEEP_R[1] = 0; + AP_PCR->SW_RESET1 = 0; + while(1); +} + +///////////////////////////////////////////////////////////////////////////////////////////////////////// +//xip flash read instrcution +#define XFRD_FCMD_READ 0x0000003 +#define XFRD_FCMD_READ_DUAL 0x801003B +#define XFRD_FCMD_READ_QUAD 0x801006B + +int main(void) { + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + certain that there are no issues with the state of global variables. + */ + uint8_t* dest = (uint8_t*)&_sbss; + uint8_t* edest = (uint8_t*)&_ebss; + + memset(dest, 0, edest - dest); + + g_system_clk = SYS_CLK_XTAL_16M; // SYS_CLK_XTAL_16M, SYS_CLK_DBL_32M, SYS_CLK_DLL_64M + spif_config(SYS_CLK_DLL_64M, 1, XFRD_FCMD_READ_DUAL, 0, 0); + copy_app_code(); + return 0; +} + + diff --git a/ota_boot/source/misc/CMSIS/device/phyplus/phy6222.h b/ota_boot/source/misc/CMSIS/device/phyplus/phy6222.h new file mode 100644 index 0000000..e09f1b4 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/device/phyplus/phy6222.h @@ -0,0 +1,116 @@ + +#ifndef __PHY62XX_H +#define __PHY62XX_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_section_for_CMSIS + @{ +*/ +/** + @brief Configuration of the Cortex-M0+ Processor and Core Peripherals +*/ +#define __CM0_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< M0 provides an MPU */ +#define __VTOR_PRESENT 0 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< M0 uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + + +/** + @} +*/ + +/** @addtogroup Peripheral_interrupt_number_definition + @{ +*/ + +/** + @brief STM32L0xx Interrupt Number Definition, according to the selected device + in @ref Library_configuration_section +*/ + +/*!< Interrupt Number Definition */ +typedef enum +{ + /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + + /****** STM32L-0 specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_IRQn = 4, /*!< RCC Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM6_IRQn = 17, /*!< TIM6 Interrupt */ + TIM21_IRQn = 20, /*!< TIM21 Interrupt */ + TIM22_IRQn = 22, /*!< TIM22 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + LPUART1_IRQn = 29, /*!< LPUART1 Interrupts */ +} IRQn_Type; + +/** + @} +*/ + +#include "core_cm0.h" +//#include "system_m0.h" +#include + + + +/** + @} +*/ + +/******************************************************************************/ +/* For a painless codes migration between the STM32L0xx device product */ +/* lines, the aliases defined below are put in place to overcome the */ +/* differences in the interrupt handlers and IRQn definitions. */ +/* No need to update developed interrupt code when moving across */ +/* product lines within the same STM32L0 Family */ +/******************************************************************************/ + +/* Aliases for __IRQn */ + +/** + @} +*/ + +/** + @} +*/ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __PHY62XX_H */ + + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + diff --git a/ota_boot/source/misc/CMSIS/device/phyplus/phy6222_start.s b/ota_boot/source/misc/CMSIS/device/phyplus/phy6222_start.s new file mode 100644 index 0000000..7d5d08d --- /dev/null +++ b/ota_boot/source/misc/CMSIS/device/phyplus/phy6222_start.s @@ -0,0 +1,55 @@ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .file "phy6222_start.s" + + /* *.ld: g_top_irqstack = ORIGIN(sram) + LENGTH(sram) */ + .global g_stack + +.text + .align 2 + .code 16 + .globl __start + .thumb_func + .type __start, %function +__start: + + ldr r1, = g_irqstack_top + msr msp, r1 /* r2>>sp */ + bl main /* R0=IRQ, R1=register save area on stack */ + + + .size __start, .-__start + +#if 0 // Implemented in phy6222_vectors.c +.section .isr_vector + .align 4 + .globl __Vectors + .type __Vectors, %object +__Vectors: + .long 0 + .long __start + + .size __Vectors, . - __Vectors +#endif + +.section .irq_stack + + .align 4 + .global g_irqstack_base + .global g_irqstack_top + +g_irqstack_base: + .space 0x400 +g_irqstack_top: + +.end + + diff --git a/ota_boot/source/misc/CMSIS/device/phyplus/phy6222_vectors.c b/ota_boot/source/misc/CMSIS/device/phyplus/phy6222_vectors.c new file mode 100644 index 0000000..cd06fa6 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/device/phyplus/phy6222_vectors.c @@ -0,0 +1,13 @@ + +#define locate_data(n) __attribute__ ((section(n))) +extern unsigned int g_irqstack_top; +extern void __start(void); +const unsigned _vectors[] locate_data(".isr_vector") = +{ + /* Initial stack */ + (unsigned)(&g_irqstack_top), + + /* Reset exception handler */ + (unsigned)(&__start), + +}; diff --git a/ota_boot/source/misc/CMSIS/include/arm_common_tables.h b/ota_boot/source/misc/CMSIS/include/arm_common_tables.h new file mode 100644 index 0000000..437d816 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/arm_common_tables.h @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------- + Copyright (C) 2010-2013 ARM Limited. All rights reserved. + + $Date: 17. January 2013 + $Revision: V1.4.1 + + Project: CMSIS DSP Library + Title: arm_common_tables.h + + Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions + + Target Processor: Cortex-M4/Cortex-M3 + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + - Neither the name of ARM LIMITED nor the names of its contributors + may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/ota_boot/source/misc/CMSIS/include/arm_const_structs.h b/ota_boot/source/misc/CMSIS/include/arm_const_structs.h new file mode 100644 index 0000000..d3d1d15 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/arm_const_structs.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------- + Copyright (C) 2010-2013 ARM Limited. All rights reserved. + + $Date: 17. January 2013 + $Revision: V1.4.1 + + Project: CMSIS DSP Library + Title: arm_const_structs.h + + Description: This file has constant structs that are initialized for + user convenience. For example, some can be given as + arguments to the arm_cfft_f32() function. + + Target Processor: Cortex-M4/Cortex-M3 + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + - Neither the name of ARM LIMITED nor the names of its contributors + may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = +{ + 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = +{ + 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = +{ + 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = +{ + 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = +{ + 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = +{ + 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = +{ + 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = +{ + 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH +}; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = +{ + 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH +}; + +#endif diff --git a/ota_boot/source/misc/CMSIS/include/arm_math.h b/ota_boot/source/misc/CMSIS/include/arm_math.h new file mode 100644 index 0000000..b201dda --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/arm_math.h @@ -0,0 +1,7080 @@ +/* ---------------------------------------------------------------------- + Copyright (C) 2010-2013 ARM Limited. All rights reserved. + + $Date: 17. January 2013 + $Revision: V1.4.1 + + Project: CMSIS DSP Library + Title: arm_math.h + + Description: Public header file for CMSIS DSP Library + + Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + - Neither the name of ARM LIMITED nor the names of its contributors + may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + + Introduction + + This user manual describes the CMSIS DSP software library, + a suite of common signal processing functions for use on Cortex-M processor based devices. + + The library is divided into a number of functions each covering a specific category: + - Basic math functions + - Fast math functions + - Complex math functions + - Filters + - Matrix functions + - Transforms + - Motor control functions + - Statistical functions + - Support functions + - Interpolation functions + + The library has separate functions for operating on 8-bit integers, 16-bit integers, + 32-bit integer and 32-bit floating-point values. + + Using the Library + + The library installer contains prebuilt versions of the libraries in the Lib folder. + - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + + The library functions are declared in the public file arm_math.h which is placed in the Include folder. + Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + + Examples + + The library ships with a number of examples which demonstrate how to use the library functions. + + Toolchain Support + + The library has been developed and tested with MDK-ARM version 4.60. + The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + + Building the Library + + The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + - arm_cortexM0b_math.uvproj + - arm_cortexM0l_math.uvproj + - arm_cortexM3b_math.uvproj + - arm_cortexM3l_math.uvproj + - arm_cortexM4b_math.uvproj + - arm_cortexM4l_math.uvproj + - arm_cortexM4bf_math.uvproj + - arm_cortexM4lf_math.uvproj + + + The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + + Pre-processor Macros + + Each library project have differant pre-processor macros. + + - UNALIGNED_SUPPORT_DISABLE: + + Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + + - ARM_MATH_BIG_ENDIAN: + + Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + + - ARM_MATH_MATRIX_CHECK: + + Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + + - ARM_MATH_ROUNDING: + + Define macro ARM_MATH_ROUNDING for rounding on support functions + + - ARM_MATH_CMx: + + Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + + - __FPU_PRESENT: + + Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + + Copyright Notice + + Copyright (C) 2010-2013 ARM Limited. All rights reserved. +*/ + + +/** + @defgroup groupMath Basic Math Functions +*/ + +/** + @defgroup groupFastMath Fast Math Functions + This set of functions provides a fast approximation to sine, cosine, and square root. + As compared to most of the other functions in the CMSIS math library, the fast math functions + operate on individual values and not arrays. + There are separate functions for Q15, Q31, and floating-point data. + +*/ + +/** + @defgroup groupCmplxMath Complex Math Functions + This set of functions operates on complex data vectors. + The data in the complex arrays is stored in an interleaved fashion + (real, imag, real, imag, ...). + In the API functions, the number of samples in a complex array refers + to the number of complex values; the array contains twice this number of + real values. +*/ + +/** + @defgroup groupFilters Filtering Functions +*/ + +/** + @defgroup groupMatrix Matrix Functions + + This set of functions provides basic matrix math operations. + The functions operate on matrix data structures. For example, + the type + definition for the floating-point matrix structure is shown + below: + 
+       typedef struct
+       {
+         uint16_t numRows;     // number of rows of the matrix.
+         uint16_t numCols;     // number of columns of the matrix.
+         float32_t *pData;     // points to the data of the matrix.
+       } arm_matrix_instance_f32;
+
+ There are similar definitions for Q15 and Q31 data types. + + The structure specifies the size of the matrix and then points to + an array of data. The array is of size numRows X numCols + and the values are arranged in row order. That is, the + matrix element (i, j) is stored at: + 
+       pData[i*numCols + j]
+
+ + \par Init Functions + There is an associated initialization function for each type of matrix + data structure. + The initialization function sets the values of the internal structure fields. + Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + + \par + Use of the initialization function is optional. However, if initialization function is used + then the instance structure cannot be placed into a const data section. + To place the instance structure in a const data + section, manually initialize the data structure. For example: + 
+    arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+    arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+    arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+
+ where nRows specifies the number of rows, nColumns + specifies the number of columns, and pData points to the + data array. + + \par Size Checking + By default all of the matrix functions perform size checking on the input and + output matrices. For example, the matrix addition function verifies that the + two input matrices and the output matrix all have the same number of rows and + columns. If the size check fails the functions return: + 
+       ARM_MATH_SIZE_MISMATCH
+
+ Otherwise the functions return + 
+       ARM_MATH_SUCCESS
+
+ There is some overhead associated with this matrix size checking. + The matrix size checking is enabled via the \#define + 
+       ARM_MATH_MATRIX_CHECK
+
+ within the library project settings. By default this macro is defined + and size checking is enabled. By changing the project settings and + undefining this macro size checking is eliminated and the functions + run a bit faster. With size checking disabled the functions always + return ARM_MATH_SUCCESS. +*/ + +/** + @defgroup groupTransforms Transform Functions +*/ + +/** + @defgroup groupController Controller Functions +*/ + +/** + @defgroup groupStats Statistics Functions +*/ +/** + @defgroup groupSupport Support Functions +*/ + +/** + @defgroup groupInterpolation Interpolation Functions + These functions perform 1- and 2-dimensional interpolation of data. + Linear interpolation is used for 1-dimensional data and + bilinear interpolation is used for 2-dimensional data. +*/ + +/** + @defgroup groupExamples Examples +*/ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined (ARM_MATH_CM4) + #include "core_cm4.h" +#elif defined (ARM_MATH_CM3) + #include "core_cm3.h" +#elif defined (ARM_MATH_CM0) + #include "core_cm0.h" + #define ARM_MATH_CM0_FAMILY +#elif defined (ARM_MATH_CM0PLUS) + #include "core_cm0plus.h" + #define ARM_MATH_CM0_FAMILY +#else + #include "ARMCM4.h" + #warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** + @brief Macros required for reciprocal calculation in Normalized LMS +*/ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + @brief Macros required for SINE and COSINE Fast math approximations +*/ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + +/** + @brief Macros required for SINE and COSINE Controller functions +*/ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + @brief Macro for Unaligned Support +*/ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined (__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + @brief Error status returned by some functions in the library. +*/ + +typedef enum +{ + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + @brief 8-bit fractional data type in 1.7 format. +*/ +typedef int8_t q7_t; + +/** + @brief 16-bit fractional data type in 1.15 format. +*/ +typedef int16_t q15_t; + +/** + @brief 32-bit fractional data type in 1.31 format. +*/ +typedef int32_t q31_t; + +/** + @brief 64-bit fractional data type in 1.63 format. +*/ +typedef int64_t q63_t; + +/** + @brief 32-bit floating-point type definition. +*/ +typedef float float32_t; + +/** + @brief 64-bit floating-point type definition. +*/ +typedef double float64_t; + +/** + @brief definition to read/write two 16 bit values. +*/ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) + +#define __SIMD64(addr) (*(int64_t **) & (addr)) + +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) +/** + @brief definition to pack two 16 bit values. +*/ +#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) +#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) + +#endif + + +/** + @brief definition to pack four 8 bit values. +*/ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) +#else + +#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ + (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) + +#endif + + +/** + @brief Clips Q63 to Q31 values. +*/ +static __INLINE q31_t clip_q63_to_q31( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; +} + +/** + @brief Clips Q63 to Q15 values. +*/ +static __INLINE q15_t clip_q63_to_q15( + q63_t x) +{ + return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? + ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); +} + +/** + @brief Clips Q31 to Q7 values. +*/ +static __INLINE q7_t clip_q31_to_q7( + q31_t x) +{ + return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? + ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; +} + +/** + @brief Clips Q31 to Q15 values. +*/ +static __INLINE q15_t clip_q31_to_q15( + q31_t x) +{ + return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? + ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; +} + +/** + @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. +*/ + +static __INLINE q63_t mult32x64( + q63_t x, + q31_t y) +{ + return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + + (((q63_t) (x >> 32) * y))); +} + + +#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +#define __CLZ __clz +#endif + +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) + +static __INLINE uint32_t __CLZ( + q31_t data); + + +static __INLINE uint32_t __CLZ( + q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while((data & mask) == 0) + { + count += 1u; + mask = mask >> 1u; + } + + return (count); +} + +#endif + +/** + @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. +*/ + +static __INLINE uint32_t arm_recip_q31( + q31_t in, + q31_t* dst, + q31_t* pRecipTable) +{ + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if(in > 0) + { + signBits = __CLZ(in) - 1; + } + else + { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + /* calculation of index for initial approximated Val */ + index = (uint32_t) (in >> 24u); + index = (index & INDEX_MASK); + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) + { + tempVal = (q31_t) (((q63_t) in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); +} + +/** + @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. +*/ +static __INLINE uint32_t arm_recip_q15( + q15_t in, + q15_t* dst, + q15_t* pRecipTable) +{ + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if(in > 0) + { + signBits = __CLZ(in) - 17; + } + else + { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) + { + tempVal = (q15_t) (((q31_t) in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t) (((q31_t) out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + /* return num of signbits of out = 1/in value */ + return (signBits + 1); +} + + +/* + @brief C custom defined intrinisic function for only M0 processors +*/ +#if defined(ARM_MATH_CM0_FAMILY) + +static __INLINE q31_t __SSAT( + q31_t x, + uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + posMax = 1; + + for (i = 0; i < (y - 1); i++) + { + posMax = posMax * 2; + } + + if(x > 0) + { + posMax = (posMax - 1); + + if(x > posMax) + { + x = posMax; + } + } + else + { + negMin = -posMax; + + if(x < negMin) + { + x = negMin; + } + } + + return (x); +} + +#endif /* end of ARM_MATH_CM0_FAMILY */ + + + +/* + @brief C custom defined intrinsic function for M3 and M0 processors +*/ +#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) + +/* + @brief C custom defined QADD8 for M3 and M0 processors +*/ +static __INLINE q31_t __QADD8( + q31_t x, + q31_t y) +{ + q31_t sum; + q7_t r, s, t, u; + r = (q7_t) x; + s = (q7_t) y; + r = __SSAT((q31_t) (r + s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); + sum = + (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | + (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); + return sum; +} + +/* + @brief C custom defined QSUB8 for M3 and M0 processors +*/ +static __INLINE q31_t __QSUB8( + q31_t x, + q31_t y) +{ + q31_t sum; + q31_t r, s, t, u; + r = (q7_t) x; + s = (q7_t) y; + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; + sum = + (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & + 0x000000FF); + return sum; +} + +/* + @brief C custom defined QADD16 for M3 and M0 processors +*/ + +/* + @brief C custom defined QADD16 for M3 and M0 processors +*/ +static __INLINE q31_t __QADD16( + q31_t x, + q31_t y) +{ + q31_t sum; + q31_t r, s; + r = (short) x; + s = (short) y; + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; +} + +/* + @brief C custom defined SHADD16 for M3 and M0 processors +*/ +static __INLINE q31_t __SHADD16( + q31_t x, + q31_t y) +{ + q31_t sum; + q31_t r, s; + r = (short) x; + s = (short) y; + r = ((r >> 1) + (s >> 1)); + s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; +} + +/* + @brief C custom defined QSUB16 for M3 and M0 processors +*/ +static __INLINE q31_t __QSUB16( + q31_t x, + q31_t y) +{ + q31_t sum; + q31_t r, s; + r = (short) x; + s = (short) y; + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; +} + +/* + @brief C custom defined SHSUB16 for M3 and M0 processors +*/ +static __INLINE q31_t __SHSUB16( + q31_t x, + q31_t y) +{ + q31_t diff; + q31_t r, s; + r = (short) x; + s = (short) y; + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return diff; +} + +/* + @brief C custom defined QASX for M3 and M0 processors +*/ +static __INLINE q31_t __QASX( + q31_t x, + q31_t y) +{ + q31_t sum = 0; + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16))); + return sum; +} + +/* + @brief C custom defined SHASX for M3 and M0 processors +*/ +static __INLINE q31_t __SHASX( + q31_t x, + q31_t y) +{ + q31_t sum; + q31_t r, s; + r = (short) x; + s = (short) y; + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; +} + + +/* + @brief C custom defined QSAX for M3 and M0 processors +*/ +static __INLINE q31_t __QSAX( + q31_t x, + q31_t y) +{ + q31_t sum = 0; + sum = + ((sum + + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) + + clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16))); + return sum; +} + +/* + @brief C custom defined SHSAX for M3 and M0 processors +*/ +static __INLINE q31_t __SHSAX( + q31_t x, + q31_t y) +{ + q31_t sum; + q31_t r, s; + r = (short) x; + s = (short) y; + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + return sum; +} + +/* + @brief C custom defined SMUSDX for M3 and M0 processors +*/ +static __INLINE q31_t __SMUSDX( + q31_t x, + q31_t y) +{ + return ((q31_t) (((short) x * (short) (y >> 16)) - + ((short) (x >> 16) * (short) y))); +} + +/* + @brief C custom defined SMUADX for M3 and M0 processors +*/ +static __INLINE q31_t __SMUADX( + q31_t x, + q31_t y) +{ + return ((q31_t) (((short) x * (short) (y >> 16)) + + ((short) (x >> 16) * (short) y))); +} + +/* + @brief C custom defined QADD for M3 and M0 processors +*/ +static __INLINE q31_t __QADD( + q31_t x, + q31_t y) +{ + return clip_q63_to_q31((q63_t) x + y); +} + +/* + @brief C custom defined QSUB for M3 and M0 processors +*/ +static __INLINE q31_t __QSUB( + q31_t x, + q31_t y) +{ + return clip_q63_to_q31((q63_t) x - y); +} + +/* + @brief C custom defined SMLAD for M3 and M0 processors +*/ +static __INLINE q31_t __SMLAD( + q31_t x, + q31_t y, + q31_t sum) +{ + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); +} + +/* + @brief C custom defined SMLADX for M3 and M0 processors +*/ +static __INLINE q31_t __SMLADX( + q31_t x, + q31_t y, + q31_t sum) +{ + return (sum + ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); +} + +/* + @brief C custom defined SMLSDX for M3 and M0 processors +*/ +static __INLINE q31_t __SMLSDX( + q31_t x, + q31_t y, + q31_t sum) +{ + return (sum - ((short) (x >> 16) * (short) (y)) + + ((short) x * (short) (y >> 16))); +} + +/* + @brief C custom defined SMLALD for M3 and M0 processors +*/ +static __INLINE q63_t __SMLALD( + q31_t x, + q31_t y, + q63_t sum) +{ + return (sum + ((short) (x >> 16) * (short) (y >> 16)) + + ((short) x * (short) y)); +} + +/* + @brief C custom defined SMLALDX for M3 and M0 processors +*/ +static __INLINE q63_t __SMLALDX( + q31_t x, + q31_t y, + q63_t sum) +{ + return (sum + ((short) (x >> 16) * (short) y)) + + ((short) x * (short) (y >> 16)); +} + +/* + @brief C custom defined SMUAD for M3 and M0 processors +*/ +static __INLINE q31_t __SMUAD( + q31_t x, + q31_t y) +{ + return (((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +/* + @brief C custom defined SMUSD for M3 and M0 processors +*/ +static __INLINE q31_t __SMUSD( + q31_t x, + q31_t y) +{ + return (-((x >> 16) * (y >> 16)) + + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + + +/* + @brief C custom defined SXTB16 for M3 and M0 processors +*/ +static __INLINE q31_t __SXTB16( + q31_t x) +{ + return ((((x << 24) >> 24) & 0x0000FFFF) | + (((x << 8) >> 8) & 0xFFFF0000)); +} + + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + + +/** + @brief Instance structure for the Q7 FIR filter. +*/ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + @brief Instance structure for the Q15 FIR filter. +*/ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + @brief Instance structure for the Q31 FIR filter. +*/ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + @brief Instance structure for the floating-point FIR filter. +*/ +typedef struct +{ + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + + +/** + @brief Processing function for the Q7 FIR filter. + @param[in] *S points to an instance of the Q7 FIR filter structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_q7( + const arm_fir_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the Q7 FIR filter. + @param[in,out] *S points to an instance of the Q7 FIR structure. + @param[in] numTaps Number of filter coefficients in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of samples that are processed. + @return none +*/ +void arm_fir_init_q7( + arm_fir_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + uint32_t blockSize); + + +/** + @brief Processing function for the Q15 FIR filter. + @param[in] *S points to an instance of the Q15 FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + @param[in] *S points to an instance of the Q15 FIR filter structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_fast_q15( + const arm_fir_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the Q15 FIR filter. + @param[in,out] *S points to an instance of the Q15 FIR filter structure. + @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of samples that are processed at a time. + @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + numTaps is not a supported value. +*/ + +arm_status arm_fir_init_q15( + arm_fir_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + @brief Processing function for the Q31 FIR filter. + @param[in] *S points to an instance of the Q31 FIR filter structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + @param[in] *S points to an instance of the Q31 FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_fast_q31( + const arm_fir_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the Q31 FIR filter. + @param[in,out] *S points to an instance of the Q31 FIR structure. + @param[in] numTaps Number of filter coefficients in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of samples that are processed at a time. + @return none. +*/ +void arm_fir_init_q31( + arm_fir_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + +/** + @brief Processing function for the floating-point FIR filter. + @param[in] *S points to an instance of the floating-point FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_f32( + const arm_fir_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the floating-point FIR filter. + @param[in,out] *S points to an instance of the floating-point FIR filter structure. + @param[in] numTaps Number of filter coefficients in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of samples that are processed at a time. + @return none. +*/ +void arm_fir_init_f32( + arm_fir_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + @brief Instance structure for the Q15 Biquad cascade filter. +*/ +typedef struct +{ + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q15; + + +/** + @brief Instance structure for the Q31 Biquad cascade filter. +*/ +typedef struct +{ + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q31; + +/** + @brief Instance structure for the floating-point Biquad cascade filter. +*/ +typedef struct +{ + uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t* pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + + +} arm_biquad_casd_df1_inst_f32; + + + +/** + @brief Processing function for the Q15 Biquad cascade filter. + @param[in] *S points to an instance of the Q15 Biquad cascade structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cascade_df1_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the Q15 Biquad cascade filter. + @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + @return none +*/ + +void arm_biquad_cascade_df1_init_q15( + arm_biquad_casd_df1_inst_q15* S, + uint8_t numStages, + q15_t* pCoeffs, + q15_t* pState, + int8_t postShift); + + +/** + @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + @param[in] *S points to an instance of the Q15 Biquad cascade structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cascade_df1_fast_q15( + const arm_biquad_casd_df1_inst_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + @brief Processing function for the Q31 Biquad cascade filter + @param[in] *S points to an instance of the Q31 Biquad cascade structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cascade_df1_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + @param[in] *S points to an instance of the Q31 Biquad cascade structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cascade_df1_fast_q31( + const arm_biquad_casd_df1_inst_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the Q31 Biquad cascade filter. + @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + @return none +*/ + +void arm_biquad_cascade_df1_init_q31( + arm_biquad_casd_df1_inst_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q31_t* pState, + int8_t postShift); + +/** + @brief Processing function for the floating-point Biquad cascade filter. + @param[in] *S points to an instance of the floating-point Biquad cascade structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cascade_df1_f32( + const arm_biquad_casd_df1_inst_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the floating-point Biquad cascade filter. + @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @return none +*/ + +void arm_biquad_cascade_df1_init_f32( + arm_biquad_casd_df1_inst_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + +/** + @brief Instance structure for the floating-point matrix structure. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t* pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + +/** + @brief Instance structure for the Q15 matrix structure. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t* pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q15; + +/** + @brief Instance structure for the Q31 matrix structure. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t* pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q31; + + + +/** + @brief Floating-point matrix addition. + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_add_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + @brief Q15 matrix addition. + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_add_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + +/** + @brief Q31 matrix addition. + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_add_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + @brief Floating-point matrix transpose. + @param[in] *pSrc points to the input matrix + @param[out] *pDst points to the output matrix + @return The function returns either ARM_MATH_SIZE_MISMATCH + or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_trans_f32( + const arm_matrix_instance_f32* pSrc, + arm_matrix_instance_f32* pDst); + + +/** + @brief Q15 matrix transpose. + @param[in] *pSrc points to the input matrix + @param[out] *pDst points to the output matrix + @return The function returns either ARM_MATH_SIZE_MISMATCH + or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_trans_q15( + const arm_matrix_instance_q15* pSrc, + arm_matrix_instance_q15* pDst); + +/** + @brief Q31 matrix transpose. + @param[in] *pSrc points to the input matrix + @param[out] *pDst points to the output matrix + @return The function returns either ARM_MATH_SIZE_MISMATCH + or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_trans_q31( + const arm_matrix_instance_q31* pSrc, + arm_matrix_instance_q31* pDst); + + +/** + @brief Floating-point matrix multiplication + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_mult_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + @brief Q15 matrix multiplication + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @param[in] *pState points to the array for storing intermediate results + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_mult_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + +/** + @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @param[in] *pState points to the array for storing intermediate results + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_mult_fast_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst, + q15_t* pState); + +/** + @brief Q31 matrix multiplication + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_mult_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_mult_fast_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + + +/** + @brief Floating-point matrix subtraction + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_sub_f32( + const arm_matrix_instance_f32* pSrcA, + const arm_matrix_instance_f32* pSrcB, + arm_matrix_instance_f32* pDst); + +/** + @brief Q15 matrix subtraction + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_sub_q15( + const arm_matrix_instance_q15* pSrcA, + const arm_matrix_instance_q15* pSrcB, + arm_matrix_instance_q15* pDst); + +/** + @brief Q31 matrix subtraction + @param[in] *pSrcA points to the first input matrix structure + @param[in] *pSrcB points to the second input matrix structure + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_sub_q31( + const arm_matrix_instance_q31* pSrcA, + const arm_matrix_instance_q31* pSrcB, + arm_matrix_instance_q31* pDst); + +/** + @brief Floating-point matrix scaling. + @param[in] *pSrc points to the input matrix + @param[in] scale scale factor + @param[out] *pDst points to the output matrix + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_scale_f32( + const arm_matrix_instance_f32* pSrc, + float32_t scale, + arm_matrix_instance_f32* pDst); + +/** + @brief Q15 matrix scaling. + @param[in] *pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] *pDst points to output matrix + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_scale_q15( + const arm_matrix_instance_q15* pSrc, + q15_t scaleFract, + int32_t shift, + arm_matrix_instance_q15* pDst); + +/** + @brief Q31 matrix scaling. + @param[in] *pSrc points to input matrix + @param[in] scaleFract fractional portion of the scale factor + @param[in] shift number of bits to shift the result by + @param[out] *pDst points to output matrix structure + @return The function returns either + ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. +*/ + +arm_status arm_mat_scale_q31( + const arm_matrix_instance_q31* pSrc, + q31_t scaleFract, + int32_t shift, + arm_matrix_instance_q31* pDst); + + +/** + @brief Q31 matrix initialization. + @param[in,out] *S points to an instance of the floating-point matrix structure. + @param[in] nRows number of rows in the matrix. + @param[in] nColumns number of columns in the matrix. + @param[in] *pData points to the matrix data array. + @return none +*/ + +void arm_mat_init_q31( + arm_matrix_instance_q31* S, + uint16_t nRows, + uint16_t nColumns, + q31_t* pData); + +/** + @brief Q15 matrix initialization. + @param[in,out] *S points to an instance of the floating-point matrix structure. + @param[in] nRows number of rows in the matrix. + @param[in] nColumns number of columns in the matrix. + @param[in] *pData points to the matrix data array. + @return none +*/ + +void arm_mat_init_q15( + arm_matrix_instance_q15* S, + uint16_t nRows, + uint16_t nColumns, + q15_t* pData); + +/** + @brief Floating-point matrix initialization. + @param[in,out] *S points to an instance of the floating-point matrix structure. + @param[in] nRows number of rows in the matrix. + @param[in] nColumns number of columns in the matrix. + @param[in] *pData points to the matrix data array. + @return none +*/ + +void arm_mat_init_f32( + arm_matrix_instance_f32* S, + uint16_t nRows, + uint16_t nColumns, + float32_t* pData); + + + +/** + @brief Instance structure for the Q15 PID Control. +*/ +typedef struct +{ + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + #ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; + #else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ + #endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + @brief Instance structure for the Q31 PID Control. +*/ +typedef struct +{ + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + +} arm_pid_instance_q31; + +/** + @brief Instance structure for the floating-point PID Control. +*/ +typedef struct +{ + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + + + +/** + @brief Initialization function for the floating-point PID Control. + @param[in,out] *S points to an instance of the PID structure. + @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + @return none. +*/ +void arm_pid_init_f32( + arm_pid_instance_f32* S, + int32_t resetStateFlag); + +/** + @brief Reset function for the floating-point PID Control. + @param[in,out] *S is an instance of the floating-point PID Control structure + @return none +*/ +void arm_pid_reset_f32( + arm_pid_instance_f32* S); + + +/** + @brief Initialization function for the Q31 PID Control. + @param[in,out] *S points to an instance of the Q15 PID structure. + @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + @return none. +*/ +void arm_pid_init_q31( + arm_pid_instance_q31* S, + int32_t resetStateFlag); + + +/** + @brief Reset function for the Q31 PID Control. + @param[in,out] *S points to an instance of the Q31 PID Control structure + @return none +*/ + +void arm_pid_reset_q31( + arm_pid_instance_q31* S); + +/** + @brief Initialization function for the Q15 PID Control. + @param[in,out] *S points to an instance of the Q15 PID structure. + @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + @return none. +*/ +void arm_pid_init_q15( + arm_pid_instance_q15* S, + int32_t resetStateFlag); + +/** + @brief Reset function for the Q15 PID Control. + @param[in,out] *S points to an instance of the q15 PID Control structure + @return none +*/ +void arm_pid_reset_q15( + arm_pid_instance_q15* S); + + +/** + @brief Instance structure for the floating-point Linear Interpolate function. +*/ +typedef struct +{ + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t* pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + @brief Instance structure for the floating-point bilinear interpolation function. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** + @brief Instance structure for the Q31 bilinear interpolation function. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** + @brief Instance structure for the Q15 bilinear interpolation function. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** + @brief Instance structure for the Q15 bilinear interpolation function. +*/ + +typedef struct +{ + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t* pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + + +/** + @brief Q7 vector multiplication. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_mult_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Q15 vector multiplication. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_mult_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Q31 vector multiplication. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_mult_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector multiplication. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_mult_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + + + + + + +/** + @brief Instance structure for the Q15 CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +arm_status arm_cfft_radix2_init_q15( + arm_cfft_radix2_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void arm_cfft_radix2_q15( + const arm_cfft_radix2_instance_q15* S, + q15_t* pSrc); + + + +/** + @brief Instance structure for the Q15 CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +arm_status arm_cfft_radix4_init_q15( + arm_cfft_radix4_instance_q15* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void arm_cfft_radix4_q15( + const arm_cfft_radix4_instance_q15* S, + q15_t* pSrc); + +/** + @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +arm_status arm_cfft_radix2_init_q31( + arm_cfft_radix2_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +void arm_cfft_radix2_q31( + const arm_cfft_radix2_instance_q31* S, + q31_t* pSrc); + +/** + @brief Instance structure for the Q31 CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + + +void arm_cfft_radix4_q31( + const arm_cfft_radix4_instance_q31* S, + q31_t* pSrc); + +arm_status arm_cfft_radix4_init_q31( + arm_cfft_radix4_instance_q31* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + @brief Instance structure for the floating-point CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32( + arm_cfft_radix2_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32( + const arm_cfft_radix2_instance_f32* S, + float32_t* pSrc); + +/** + @brief Instance structure for the floating-point CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32( + arm_cfft_radix4_instance_f32* S, + uint16_t fftLen, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32( + const arm_cfft_radix4_instance_f32* S, + float32_t* pSrc); + +/** + @brief Instance structure for the floating-point CFFT/CIFFT function. +*/ + +typedef struct +{ + uint16_t fftLen; /**< length of the FFT. */ + const float32_t* pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t* pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32( + const arm_cfft_instance_f32* S, + float32_t* p1, + uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + @brief Instance structure for the Q15 RFFT/RIFFT function. +*/ + +typedef struct +{ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15( + arm_rfft_instance_q15* S, + arm_cfft_radix4_instance_q15* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q15( + const arm_rfft_instance_q15* S, + q15_t* pSrc, + q15_t* pDst); + +/** + @brief Instance structure for the Q31 RFFT/RIFFT function. +*/ + +typedef struct +{ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31( + arm_rfft_instance_q31* S, + arm_cfft_radix4_instance_q31* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_q31( + const arm_rfft_instance_q31* S, + q31_t* pSrc, + q31_t* pDst); + +/** + @brief Instance structure for the floating-point RFFT/RIFFT function. +*/ + +typedef struct +{ + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t* pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t* pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32( + arm_rfft_instance_f32* S, + arm_cfft_radix4_instance_f32* S_CFFT, + uint32_t fftLenReal, + uint32_t ifftFlagR, + uint32_t bitReverseFlag); + +void arm_rfft_f32( + const arm_rfft_instance_f32* S, + float32_t* pSrc, + float32_t* pDst); + +/** + @brief Instance structure for the floating-point RFFT/RIFFT function. +*/ + +typedef struct +{ + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t* pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32 ; + +arm_status arm_rfft_fast_init_f32 ( + arm_rfft_fast_instance_f32* S, + uint16_t fftLen); + +void arm_rfft_fast_f32( + arm_rfft_fast_instance_f32* S, + float32_t* p, float32_t* pOut, + uint8_t ifftFlag); + +/** + @brief Instance structure for the floating-point DCT4/IDCT4 function. +*/ + +typedef struct +{ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t* pTwiddle; /**< points to the twiddle factor table. */ + float32_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + +/** + @brief Initialization function for the floating-point DCT4/IDCT4. + @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. +*/ + +arm_status arm_dct4_init_f32( + arm_dct4_instance_f32* S, + arm_rfft_instance_f32* S_RFFT, + arm_cfft_radix4_instance_f32* S_CFFT, + uint16_t N, + uint16_t Nby2, + float32_t normalize); + +/** + @brief Processing function for the floating-point DCT4/IDCT4. + @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + @param[in] *pState points to state buffer. + @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + @return none. +*/ + +void arm_dct4_f32( + const arm_dct4_instance_f32* S, + float32_t* pState, + float32_t* pInlineBuffer); + +/** + @brief Instance structure for the Q31 DCT4/IDCT4 function. +*/ + +typedef struct +{ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t* pTwiddle; /**< points to the twiddle factor table. */ + q31_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + +/** + @brief Initialization function for the Q31 DCT4/IDCT4. + @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. +*/ + +arm_status arm_dct4_init_q31( + arm_dct4_instance_q31* S, + arm_rfft_instance_q31* S_RFFT, + arm_cfft_radix4_instance_q31* S_CFFT, + uint16_t N, + uint16_t Nby2, + q31_t normalize); + +/** + @brief Processing function for the Q31 DCT4/IDCT4. + @param[in] *S points to an instance of the Q31 DCT4 structure. + @param[in] *pState points to state buffer. + @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + @return none. +*/ + +void arm_dct4_q31( + const arm_dct4_instance_q31* S, + q31_t* pState, + q31_t* pInlineBuffer); + +/** + @brief Instance structure for the Q15 DCT4/IDCT4 function. +*/ + +typedef struct +{ + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t* pTwiddle; /**< points to the twiddle factor table. */ + q15_t* pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15* pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15* pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + +/** + @brief Initialization function for the Q15 DCT4/IDCT4. + @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + @param[in] N length of the DCT4. + @param[in] Nby2 half of the length of the DCT4. + @param[in] normalize normalizing factor. + @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. +*/ + +arm_status arm_dct4_init_q15( + arm_dct4_instance_q15* S, + arm_rfft_instance_q15* S_RFFT, + arm_cfft_radix4_instance_q15* S_CFFT, + uint16_t N, + uint16_t Nby2, + q15_t normalize); + +/** + @brief Processing function for the Q15 DCT4/IDCT4. + @param[in] *S points to an instance of the Q15 DCT4 structure. + @param[in] *pState points to state buffer. + @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + @return none. +*/ + +void arm_dct4_q15( + const arm_dct4_instance_q15* S, + q15_t* pState, + q15_t* pInlineBuffer); + +/** + @brief Floating-point vector addition. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_add_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Q7 vector addition. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_add_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Q15 vector addition. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_add_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Q31 vector addition. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_add_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector subtraction. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_sub_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Q7 vector subtraction. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_sub_q7( + q7_t* pSrcA, + q7_t* pSrcB, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Q15 vector subtraction. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_sub_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Q31 vector subtraction. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_sub_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Multiplies a floating-point vector by a scalar. + @param[in] *pSrc points to the input vector + @param[in] scale scale factor to be applied + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_scale_f32( + float32_t* pSrc, + float32_t scale, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Multiplies a Q7 vector by a scalar. + @param[in] *pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_scale_q7( + q7_t* pSrc, + q7_t scaleFract, + int8_t shift, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Multiplies a Q15 vector by a scalar. + @param[in] *pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_scale_q15( + q15_t* pSrc, + q15_t scaleFract, + int8_t shift, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Multiplies a Q31 vector by a scalar. + @param[in] *pSrc points to the input vector + @param[in] scaleFract fractional portion of the scale value + @param[in] shift number of bits to shift the result by + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_scale_q31( + q31_t* pSrc, + q31_t scaleFract, + int8_t shift, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Q7 vector absolute value. + @param[in] *pSrc points to the input buffer + @param[out] *pDst points to the output buffer + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_abs_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Floating-point vector absolute value. + @param[in] *pSrc points to the input buffer + @param[out] *pDst points to the output buffer + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_abs_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Q15 vector absolute value. + @param[in] *pSrc points to the input buffer + @param[out] *pDst points to the output buffer + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_abs_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Q31 vector absolute value. + @param[in] *pSrc points to the input buffer + @param[out] *pDst points to the output buffer + @param[in] blockSize number of samples in each vector + @return none. +*/ + +void arm_abs_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Dot product of floating-point vectors. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] *result output result returned here + @return none. +*/ + +void arm_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t blockSize, + float32_t* result); + +/** + @brief Dot product of Q7 vectors. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] *result output result returned here + @return none. +*/ + +void arm_dot_prod_q7( + q7_t* pSrcA, + q7_t* pSrcB, + uint32_t blockSize, + q31_t* result); + +/** + @brief Dot product of Q15 vectors. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] *result output result returned here + @return none. +*/ + +void arm_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t blockSize, + q63_t* result); + +/** + @brief Dot product of Q31 vectors. + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] blockSize number of samples in each vector + @param[out] *result output result returned here + @return none. +*/ + +void arm_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t blockSize, + q63_t* result); + +/** + @brief Shifts the elements of a Q7 vector a specified number of bits. + @param[in] *pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_shift_q7( + q7_t* pSrc, + int8_t shiftBits, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Shifts the elements of a Q15 vector a specified number of bits. + @param[in] *pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_shift_q15( + q15_t* pSrc, + int8_t shiftBits, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Shifts the elements of a Q31 vector a specified number of bits. + @param[in] *pSrc points to the input vector + @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_shift_q31( + q31_t* pSrc, + int8_t shiftBits, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Adds a constant offset to a floating-point vector. + @param[in] *pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_offset_f32( + float32_t* pSrc, + float32_t offset, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Adds a constant offset to a Q7 vector. + @param[in] *pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_offset_q7( + q7_t* pSrc, + q7_t offset, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Adds a constant offset to a Q15 vector. + @param[in] *pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_offset_q15( + q15_t* pSrc, + q15_t offset, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Adds a constant offset to a Q31 vector. + @param[in] *pSrc points to the input vector + @param[in] offset is the offset to be added + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_offset_q31( + q31_t* pSrc, + q31_t offset, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Negates the elements of a floating-point vector. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_negate_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Negates the elements of a Q7 vector. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_negate_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Negates the elements of a Q15 vector. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_negate_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Negates the elements of a Q31 vector. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] blockSize number of samples in the vector + @return none. +*/ + +void arm_negate_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); +/** + @brief Copies the elements of a floating-point vector. + @param[in] *pSrc input pointer + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_copy_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Copies the elements of a Q7 vector. + @param[in] *pSrc input pointer + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_copy_q7( + q7_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Copies the elements of a Q15 vector. + @param[in] *pSrc input pointer + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_copy_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Copies the elements of a Q31 vector. + @param[in] *pSrc input pointer + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_copy_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); +/** + @brief Fills a constant value into a floating-point vector. + @param[in] value input value to be filled + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_fill_f32( + float32_t value, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Fills a constant value into a Q7 vector. + @param[in] value input value to be filled + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_fill_q7( + q7_t value, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Fills a constant value into a Q15 vector. + @param[in] value input value to be filled + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_fill_q15( + q15_t value, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Fills a constant value into a Q31 vector. + @param[in] value input value to be filled + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_fill_q31( + q31_t value, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Convolution of floating-point sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none. +*/ + +void arm_conv_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** + @brief Convolution of Q15 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none. +*/ + + +void arm_conv_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + @brief Convolution of Q15 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + @return none. +*/ + +void arm_conv_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @return none. +*/ + +void arm_conv_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return none. +*/ + +void arm_conv_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + + +/** + @brief Convolution of Q31 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @return none. +*/ + +void arm_conv_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + +/** + @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @return none. +*/ + +void arm_conv_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + +/** + @brief Convolution of Q7 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none. +*/ + +void arm_conv_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + + +/** + @brief Convolution of Q7 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + @return none. +*/ + +void arm_conv_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + @brief Partial convolution of floating-point sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + +/** + @brief Partial convolution of Q15 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + @brief Partial convolution of Q15 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + +/** + @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + @brief Partial convolution of Q31 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + +/** + @brief Partial convolution of Q7 sequences + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + @brief Partial convolution of Q7 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data + @param[in] firstIndex is the first output sample to start with. + @param[in] numPoints is the number of output points to be computed. + @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. +*/ + +arm_status arm_conv_partial_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + uint32_t firstIndex, + uint32_t numPoints); + + + +/** + @brief Instance structure for the Q15 FIR decimator. +*/ + +typedef struct +{ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + @brief Instance structure for the Q31 FIR decimator. +*/ + +typedef struct +{ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_q31; + +/** + @brief Instance structure for the floating-point FIR decimator. +*/ + +typedef struct +{ + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_f32; + + + +/** + @brief Processing function for the floating-point FIR decimator. + @param[in] *S points to an instance of the floating-point FIR decimator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of input samples to process per call. + @return none +*/ + +void arm_fir_decimate_f32( + const arm_fir_decimate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point FIR decimator. + @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + @param[in] numTaps number of coefficients in the filter. + @param[in] M decimation factor. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of input samples to process per call. + @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + blockSize is not a multiple of M. +*/ + +arm_status arm_fir_decimate_init_f32( + arm_fir_decimate_instance_f32* S, + uint16_t numTaps, + uint8_t M, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + +/** + @brief Processing function for the Q15 FIR decimator. + @param[in] *S points to an instance of the Q15 FIR decimator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of input samples to process per call. + @return none +*/ + +void arm_fir_decimate_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + @param[in] *S points to an instance of the Q15 FIR decimator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of input samples to process per call. + @return none +*/ + +void arm_fir_decimate_fast_q15( + const arm_fir_decimate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + @brief Initialization function for the Q15 FIR decimator. + @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + @param[in] numTaps number of coefficients in the filter. + @param[in] M decimation factor. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of input samples to process per call. + @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + blockSize is not a multiple of M. +*/ + +arm_status arm_fir_decimate_init_q15( + arm_fir_decimate_instance_q15* S, + uint16_t numTaps, + uint8_t M, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + @brief Processing function for the Q31 FIR decimator. + @param[in] *S points to an instance of the Q31 FIR decimator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of input samples to process per call. + @return none +*/ + +void arm_fir_decimate_q31( + const arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + @param[in] *S points to an instance of the Q31 FIR decimator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of input samples to process per call. + @return none +*/ + +void arm_fir_decimate_fast_q31( + arm_fir_decimate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the Q31 FIR decimator. + @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + @param[in] numTaps number of coefficients in the filter. + @param[in] M decimation factor. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of input samples to process per call. + @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + blockSize is not a multiple of M. +*/ + +arm_status arm_fir_decimate_init_q31( + arm_fir_decimate_instance_q31* S, + uint16_t numTaps, + uint8_t M, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + + +/** + @brief Instance structure for the Q15 FIR interpolator. +*/ + +typedef struct +{ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + @brief Instance structure for the Q31 FIR interpolator. +*/ + +typedef struct +{ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t* pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + @brief Instance structure for the floating-point FIR interpolator. +*/ + +typedef struct +{ + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t* pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + + +/** + @brief Processing function for the Q15 FIR interpolator. + @param[in] *S points to an instance of the Q15 FIR interpolator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_interpolate_q15( + const arm_fir_interpolate_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the Q15 FIR interpolator. + @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + @param[in] L upsample factor. + @param[in] numTaps number of filter coefficients in the filter. + @param[in] *pCoeffs points to the filter coefficient buffer. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of input samples to process per call. + @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + the filter length numTaps is not a multiple of the interpolation factor L. +*/ + +arm_status arm_fir_interpolate_init_q15( + arm_fir_interpolate_instance_q15* S, + uint8_t L, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + @brief Processing function for the Q31 FIR interpolator. + @param[in] *S points to an instance of the Q15 FIR interpolator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_interpolate_q31( + const arm_fir_interpolate_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the Q31 FIR interpolator. + @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + @param[in] L upsample factor. + @param[in] numTaps number of filter coefficients in the filter. + @param[in] *pCoeffs points to the filter coefficient buffer. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of input samples to process per call. + @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + the filter length numTaps is not a multiple of the interpolation factor L. +*/ + +arm_status arm_fir_interpolate_init_q31( + arm_fir_interpolate_instance_q31* S, + uint8_t L, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + @brief Processing function for the floating-point FIR interpolator. + @param[in] *S points to an instance of the floating-point FIR interpolator structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_interpolate_f32( + const arm_fir_interpolate_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the floating-point FIR interpolator. + @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + @param[in] L upsample factor. + @param[in] numTaps number of filter coefficients in the filter. + @param[in] *pCoeffs points to the filter coefficient buffer. + @param[in] *pState points to the state buffer. + @param[in] blockSize number of input samples to process per call. + @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + the filter length numTaps is not a multiple of the interpolation factor L. +*/ + +arm_status arm_fir_interpolate_init_f32( + arm_fir_interpolate_instance_f32* S, + uint8_t L, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + uint32_t blockSize); + +/** + @brief Instance structure for the high precision Q31 Biquad cascade filter. +*/ + +typedef struct +{ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t* pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + +} arm_biquad_cas_df1_32x64_ins_q31; + + +/** + @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cas_df1_32x64_q31( + const arm_biquad_cas_df1_32x64_ins_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + @return none +*/ + +void arm_biquad_cas_df1_32x64_init_q31( + arm_biquad_cas_df1_32x64_ins_q31* S, + uint8_t numStages, + q31_t* pCoeffs, + q63_t* pState, + uint8_t postShift); + + + +/** + @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. +*/ + +typedef struct +{ + uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t* pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t* pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + + +/** + @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + @param[in] *S points to an instance of the filter data structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_biquad_cascade_df2T_f32( + const arm_biquad_cascade_df2T_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + @param[in,out] *S points to an instance of the filter data structure. + @param[in] numStages number of 2nd order stages in the filter. + @param[in] *pCoeffs points to the filter coefficients. + @param[in] *pState points to the state buffer. + @return none +*/ + +void arm_biquad_cascade_df2T_init_f32( + arm_biquad_cascade_df2T_instance_f32* S, + uint8_t numStages, + float32_t* pCoeffs, + float32_t* pState); + + + +/** + @brief Instance structure for the Q15 FIR lattice filter. +*/ + +typedef struct +{ + uint16_t numStages; /**< number of filter stages. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + @brief Instance structure for the Q31 FIR lattice filter. +*/ + +typedef struct +{ + uint16_t numStages; /**< number of filter stages. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + @brief Instance structure for the floating-point FIR lattice filter. +*/ + +typedef struct +{ + uint16_t numStages; /**< number of filter stages. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + +/** + @brief Initialization function for the Q15 FIR lattice filter. + @param[in] *S points to an instance of the Q15 FIR lattice structure. + @param[in] numStages number of filter stages. + @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + @param[in] *pState points to the state buffer. The array is of length numStages. + @return none. +*/ + +void arm_fir_lattice_init_q15( + arm_fir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pCoeffs, + q15_t* pState); + + +/** + @brief Processing function for the Q15 FIR lattice filter. + @param[in] *S points to an instance of the Q15 FIR lattice structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ +void arm_fir_lattice_q15( + const arm_fir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the Q31 FIR lattice filter. + @param[in] *S points to an instance of the Q31 FIR lattice structure. + @param[in] numStages number of filter stages. + @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + @param[in] *pState points to the state buffer. The array is of length numStages. + @return none. +*/ + +void arm_fir_lattice_init_q31( + arm_fir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pCoeffs, + q31_t* pState); + + +/** + @brief Processing function for the Q31 FIR lattice filter. + @param[in] *S points to an instance of the Q31 FIR lattice structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_fir_lattice_q31( + const arm_fir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the floating-point FIR lattice filter. + @param[in] *S points to an instance of the floating-point FIR lattice structure. + @param[in] numStages number of filter stages. + @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + @param[in] *pState points to the state buffer. The array is of length numStages. + @return none. +*/ + +void arm_fir_lattice_init_f32( + arm_fir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pCoeffs, + float32_t* pState); + +/** + @brief Processing function for the floating-point FIR lattice filter. + @param[in] *S points to an instance of the floating-point FIR lattice structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_fir_lattice_f32( + const arm_fir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Instance structure for the Q15 IIR lattice filter. +*/ +typedef struct +{ + uint16_t numStages; /**< number of stages in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + @brief Instance structure for the Q31 IIR lattice filter. +*/ +typedef struct +{ + uint16_t numStages; /**< number of stages in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + @brief Instance structure for the floating-point IIR lattice filter. +*/ +typedef struct +{ + uint16_t numStages; /**< number of stages in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t* pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t* pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + +/** + @brief Processing function for the floating-point IIR lattice filter. + @param[in] *S points to an instance of the floating-point IIR lattice structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_iir_lattice_f32( + const arm_iir_lattice_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @brief Initialization function for the floating-point IIR lattice filter. + @param[in] *S points to an instance of the floating-point IIR lattice structure. + @param[in] numStages number of stages in the filter. + @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_iir_lattice_init_f32( + arm_iir_lattice_instance_f32* S, + uint16_t numStages, + float32_t* pkCoeffs, + float32_t* pvCoeffs, + float32_t* pState, + uint32_t blockSize); + + +/** + @brief Processing function for the Q31 IIR lattice filter. + @param[in] *S points to an instance of the Q31 IIR lattice structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_iir_lattice_q31( + const arm_iir_lattice_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the Q31 IIR lattice filter. + @param[in] *S points to an instance of the Q31 IIR lattice structure. + @param[in] numStages number of stages in the filter. + @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_iir_lattice_init_q31( + arm_iir_lattice_instance_q31* S, + uint16_t numStages, + q31_t* pkCoeffs, + q31_t* pvCoeffs, + q31_t* pState, + uint32_t blockSize); + + +/** + @brief Processing function for the Q15 IIR lattice filter. + @param[in] *S points to an instance of the Q15 IIR lattice structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_iir_lattice_q15( + const arm_iir_lattice_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + +/** + @brief Initialization function for the Q15 IIR lattice filter. + @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + @param[in] numStages number of stages in the filter. + @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + @param[in] blockSize number of samples to process per call. + @return none. +*/ + +void arm_iir_lattice_init_q15( + arm_iir_lattice_instance_q15* S, + uint16_t numStages, + q15_t* pkCoeffs, + q15_t* pvCoeffs, + q15_t* pState, + uint32_t blockSize); + +/** + @brief Instance structure for the floating-point LMS filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + +/** + @brief Processing function for floating-point LMS filter. + @param[in] *S points to an instance of the floating-point LMS filter structure. + @param[in] *pSrc points to the block of input data. + @param[in] *pRef points to the block of reference data. + @param[out] *pOut points to the block of output data. + @param[out] *pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_f32( + const arm_lms_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + +/** + @brief Initialization function for floating-point LMS filter. + @param[in] *S points to an instance of the floating-point LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] *pCoeffs points to the coefficient buffer. + @param[in] *pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_init_f32( + arm_lms_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + +/** + @brief Instance structure for the Q15 LMS filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + + +/** + @brief Initialization function for the Q15 LMS filter. + @param[in] *S points to an instance of the Q15 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] *pCoeffs points to the coefficient buffer. + @param[in] *pState points to the state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none. +*/ + +void arm_lms_init_q15( + arm_lms_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint32_t postShift); + +/** + @brief Processing function for Q15 LMS filter. + @param[in] *S points to an instance of the Q15 LMS filter structure. + @param[in] *pSrc points to the block of input data. + @param[in] *pRef points to the block of reference data. + @param[out] *pOut points to the block of output data. + @param[out] *pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_q15( + const arm_lms_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + @brief Instance structure for the Q31 LMS filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + +} arm_lms_instance_q31; + +/** + @brief Processing function for Q31 LMS filter. + @param[in] *S points to an instance of the Q15 LMS filter structure. + @param[in] *pSrc points to the block of input data. + @param[in] *pRef points to the block of reference data. + @param[out] *pOut points to the block of output data. + @param[out] *pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_q31( + const arm_lms_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + +/** + @brief Initialization function for Q31 LMS filter. + @param[in] *S points to an instance of the Q31 LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] *pCoeffs points to coefficient buffer. + @param[in] *pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none. +*/ + +void arm_lms_init_q31( + arm_lms_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint32_t postShift); + +/** + @brief Instance structure for the floating-point normalized LMS filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + +/** + @brief Processing function for floating-point normalized LMS filter. + @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + @param[in] *pSrc points to the block of input data. + @param[in] *pRef points to the block of reference data. + @param[out] *pOut points to the block of output data. + @param[out] *pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_norm_f32( + arm_lms_norm_instance_f32* S, + float32_t* pSrc, + float32_t* pRef, + float32_t* pOut, + float32_t* pErr, + uint32_t blockSize); + +/** + @brief Initialization function for floating-point normalized LMS filter. + @param[in] *S points to an instance of the floating-point LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] *pCoeffs points to coefficient buffer. + @param[in] *pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_norm_init_f32( + arm_lms_norm_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + float32_t mu, + uint32_t blockSize); + + +/** + @brief Instance structure for the Q31 normalized LMS filter. +*/ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t* recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + +/** + @brief Processing function for Q31 normalized LMS filter. + @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + @param[in] *pSrc points to the block of input data. + @param[in] *pRef points to the block of reference data. + @param[out] *pOut points to the block of output data. + @param[out] *pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_norm_q31( + arm_lms_norm_instance_q31* S, + q31_t* pSrc, + q31_t* pRef, + q31_t* pOut, + q31_t* pErr, + uint32_t blockSize); + +/** + @brief Initialization function for Q31 normalized LMS filter. + @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] *pCoeffs points to coefficient buffer. + @param[in] *pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none. +*/ + +void arm_lms_norm_init_q31( + arm_lms_norm_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + q31_t mu, + uint32_t blockSize, + uint8_t postShift); + +/** + @brief Instance structure for the Q15 normalized LMS filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t* pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t* recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + +/** + @brief Processing function for Q15 normalized LMS filter. + @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + @param[in] *pSrc points to the block of input data. + @param[in] *pRef points to the block of reference data. + @param[out] *pOut points to the block of output data. + @param[out] *pErr points to the block of error data. + @param[in] blockSize number of samples to process. + @return none. +*/ + +void arm_lms_norm_q15( + arm_lms_norm_instance_q15* S, + q15_t* pSrc, + q15_t* pRef, + q15_t* pOut, + q15_t* pErr, + uint32_t blockSize); + + +/** + @brief Initialization function for Q15 normalized LMS filter. + @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + @param[in] numTaps number of filter coefficients. + @param[in] *pCoeffs points to coefficient buffer. + @param[in] *pState points to state buffer. + @param[in] mu step size that controls filter coefficient updates. + @param[in] blockSize number of samples to process. + @param[in] postShift bit shift applied to coefficients. + @return none. +*/ + +void arm_lms_norm_init_q15( + arm_lms_norm_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + q15_t mu, + uint32_t blockSize, + uint8_t postShift); + +/** + @brief Correlation of floating-point sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @return none. +*/ + +void arm_correlate_f32( + float32_t* pSrcA, + uint32_t srcALen, + float32_t* pSrcB, + uint32_t srcBLen, + float32_t* pDst); + + +/** + @brief Correlation of Q15 sequences + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none. +*/ +void arm_correlate_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + + +/** + @brief Correlation of Q15 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @return none. +*/ + +void arm_correlate_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + +/** + @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @return none. +*/ + +void arm_correlate_fast_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst); + + + +/** + @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @return none. +*/ + +void arm_correlate_fast_opt_q15( + q15_t* pSrcA, + uint32_t srcALen, + q15_t* pSrcB, + uint32_t srcBLen, + q15_t* pDst, + q15_t* pScratch); + +/** + @brief Correlation of Q31 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @return none. +*/ + +void arm_correlate_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + +/** + @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @return none. +*/ + +void arm_correlate_fast_q31( + q31_t* pSrcA, + uint32_t srcALen, + q31_t* pSrcB, + uint32_t srcBLen, + q31_t* pDst); + + + +/** + @brief Correlation of Q7 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + @return none. +*/ + +void arm_correlate_opt_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst, + q15_t* pScratch1, + q15_t* pScratch2); + + +/** + @brief Correlation of Q7 sequences. + @param[in] *pSrcA points to the first input sequence. + @param[in] srcALen length of the first input sequence. + @param[in] *pSrcB points to the second input sequence. + @param[in] srcBLen length of the second input sequence. + @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + @return none. +*/ + +void arm_correlate_q7( + q7_t* pSrcA, + uint32_t srcALen, + q7_t* pSrcB, + uint32_t srcBLen, + q7_t* pDst); + + +/** + @brief Instance structure for the floating-point sparse FIR filter. +*/ +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + @brief Instance structure for the Q31 sparse FIR filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + @brief Instance structure for the Q15 sparse FIR filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + @brief Instance structure for the Q7 sparse FIR filter. +*/ + +typedef struct +{ + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t* pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t* pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t* pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + +/** + @brief Processing function for the floating-point sparse FIR filter. + @param[in] *S points to an instance of the floating-point sparse FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] *pScratchIn points to a temporary buffer of size blockSize. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_sparse_f32( + arm_fir_sparse_instance_f32* S, + float32_t* pSrc, + float32_t* pDst, + float32_t* pScratchIn, + uint32_t blockSize); + +/** + @brief Initialization function for the floating-point sparse FIR filter. + @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + @param[in] numTaps number of nonzero coefficients in the filter. + @param[in] *pCoeffs points to the array of filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] *pTapDelay points to the array of offset times. + @param[in] maxDelay maximum offset time supported. + @param[in] blockSize number of samples that will be processed per block. + @return none +*/ + +void arm_fir_sparse_init_f32( + arm_fir_sparse_instance_f32* S, + uint16_t numTaps, + float32_t* pCoeffs, + float32_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + @brief Processing function for the Q31 sparse FIR filter. + @param[in] *S points to an instance of the Q31 sparse FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] *pScratchIn points to a temporary buffer of size blockSize. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_sparse_q31( + arm_fir_sparse_instance_q31* S, + q31_t* pSrc, + q31_t* pDst, + q31_t* pScratchIn, + uint32_t blockSize); + +/** + @brief Initialization function for the Q31 sparse FIR filter. + @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + @param[in] numTaps number of nonzero coefficients in the filter. + @param[in] *pCoeffs points to the array of filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] *pTapDelay points to the array of offset times. + @param[in] maxDelay maximum offset time supported. + @param[in] blockSize number of samples that will be processed per block. + @return none +*/ + +void arm_fir_sparse_init_q31( + arm_fir_sparse_instance_q31* S, + uint16_t numTaps, + q31_t* pCoeffs, + q31_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + @brief Processing function for the Q15 sparse FIR filter. + @param[in] *S points to an instance of the Q15 sparse FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] *pScratchIn points to a temporary buffer of size blockSize. + @param[in] *pScratchOut points to a temporary buffer of size blockSize. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_sparse_q15( + arm_fir_sparse_instance_q15* S, + q15_t* pSrc, + q15_t* pDst, + q15_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + + +/** + @brief Initialization function for the Q15 sparse FIR filter. + @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + @param[in] numTaps number of nonzero coefficients in the filter. + @param[in] *pCoeffs points to the array of filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] *pTapDelay points to the array of offset times. + @param[in] maxDelay maximum offset time supported. + @param[in] blockSize number of samples that will be processed per block. + @return none +*/ + +void arm_fir_sparse_init_q15( + arm_fir_sparse_instance_q15* S, + uint16_t numTaps, + q15_t* pCoeffs, + q15_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + +/** + @brief Processing function for the Q7 sparse FIR filter. + @param[in] *S points to an instance of the Q7 sparse FIR structure. + @param[in] *pSrc points to the block of input data. + @param[out] *pDst points to the block of output data + @param[in] *pScratchIn points to a temporary buffer of size blockSize. + @param[in] *pScratchOut points to a temporary buffer of size blockSize. + @param[in] blockSize number of input samples to process per call. + @return none. +*/ + +void arm_fir_sparse_q7( + arm_fir_sparse_instance_q7* S, + q7_t* pSrc, + q7_t* pDst, + q7_t* pScratchIn, + q31_t* pScratchOut, + uint32_t blockSize); + +/** + @brief Initialization function for the Q7 sparse FIR filter. + @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + @param[in] numTaps number of nonzero coefficients in the filter. + @param[in] *pCoeffs points to the array of filter coefficients. + @param[in] *pState points to the state buffer. + @param[in] *pTapDelay points to the array of offset times. + @param[in] maxDelay maximum offset time supported. + @param[in] blockSize number of samples that will be processed per block. + @return none +*/ + +void arm_fir_sparse_init_q7( + arm_fir_sparse_instance_q7* S, + uint16_t numTaps, + q7_t* pCoeffs, + q7_t* pState, + int32_t* pTapDelay, + uint16_t maxDelay, + uint32_t blockSize); + + +/* + @brief Floating-point sin_cos function. + @param[in] theta input value in degrees + @param[out] *pSinVal points to the processed sine output. + @param[out] *pCosVal points to the processed cos output. + @return none. +*/ + +void arm_sin_cos_f32( + float32_t theta, + float32_t* pSinVal, + float32_t* pCcosVal); + +/* + @brief Q31 sin_cos function. + @param[in] theta scaled input value in degrees + @param[out] *pSinVal points to the processed sine output. + @param[out] *pCosVal points to the processed cosine output. + @return none. +*/ + +void arm_sin_cos_q31( + q31_t theta, + q31_t* pSinVal, + q31_t* pCosVal); + + +/** + @brief Floating-point complex conjugate. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] numSamples number of complex samples in each vector + @return none. +*/ + +void arm_cmplx_conj_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + @brief Q31 complex conjugate. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] numSamples number of complex samples in each vector + @return none. +*/ + +void arm_cmplx_conj_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + @brief Q15 complex conjugate. + @param[in] *pSrc points to the input vector + @param[out] *pDst points to the output vector + @param[in] numSamples number of complex samples in each vector + @return none. +*/ + +void arm_cmplx_conj_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + + +/** + @brief Floating-point complex magnitude squared + @param[in] *pSrc points to the complex input vector + @param[out] *pDst points to the real output vector + @param[in] numSamples number of complex samples in the input vector + @return none. +*/ + +void arm_cmplx_mag_squared_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + @brief Q31 complex magnitude squared + @param[in] *pSrc points to the complex input vector + @param[out] *pDst points to the real output vector + @param[in] numSamples number of complex samples in the input vector + @return none. +*/ + +void arm_cmplx_mag_squared_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + @brief Q15 complex magnitude squared + @param[in] *pSrc points to the complex input vector + @param[out] *pDst points to the real output vector + @param[in] numSamples number of complex samples in the input vector + @return none. +*/ + +void arm_cmplx_mag_squared_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + + +/** + @ingroup groupController +*/ + +/** + @defgroup PID PID Motor Control + + A Proportional Integral Derivative (PID) controller is a generic feedback control + loop mechanism widely used in industrial control systems. + A PID controller is the most commonly used type of feedback controller. + + This set of functions implements (PID) controllers + for Q15, Q31, and floating-point data types. The functions operate on a single sample + of data and each call to the function returns a single processed value. + S points to an instance of the PID control data structure. in + is the input sample value. The functions return the output value. + + \par Algorithm: + 
+      y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+      A0 = Kp + Ki + Kd
+      A1 = (-Kp ) - (2 * Kd )
+      A2 = Kd
+ + \par + where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + + \par + \image html PID.gif "Proportional Integral Derivative Controller" + + \par + The PID controller calculates an "error" value as the difference between + the measured output and the reference input. + The controller attempts to minimize the error by adjusting the process control inputs. + The proportional value determines the reaction to the current error, + the integral value determines the reaction based on the sum of recent errors, + and the derivative value determines the reaction based on the rate at which the error has been changing. + + \par Instance Structure + The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + A separate instance structure must be defined for each PID Controller. + There are separate instance structure declarations for each of the 3 supported data types. + + \par Reset Functions + There is also an associated reset function for each data type which clears the state array. + + \par Initialization Functions + There is also an associated initialization function for each data type. + The initialization function performs the following operations: + - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + - Zeros out the values in the state buffer. + + \par + Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + + \par Fixed-Point Behavior + Care must be taken when using the fixed-point versions of the PID Controller functions. + In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + Refer to the function specific documentation below for usage guidelines. +*/ + +/** + @addtogroup PID + @{ +*/ + +/** + @brief Process function for the floating-point PID Control. + @param[in,out] *S is an instance of the floating-point PID Control structure + @param[in] in input sample to process + @return out processed output sample. +*/ + + +static __INLINE float32_t arm_pid_f32( + arm_pid_instance_f32* S, + float32_t in) +{ + float32_t out; + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + /* return to application */ + return (out); +} + +/** + @brief Process function for the Q31 PID Control. + @param[in,out] *S points to an instance of the Q31 PID Control structure + @param[in] in input sample to process + @return out processed output sample. + + Scaling and Overflow Behavior: + \par + The function is implemented using an internal 64-bit accumulator. + The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + Thus, if the accumulator result overflows it wraps around rather than clip. + In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. +*/ + +static __INLINE q31_t arm_pid_q31( + arm_pid_instance_q31* S, + q31_t in) +{ + q63_t acc; + q31_t out; + /* acc = A0 * x[n] */ + acc = (q63_t) S->A0 * in; + /* acc += A1 * x[n-1] */ + acc += (q63_t) S->A1 * S->state[0]; + /* acc += A2 * x[n-2] */ + acc += (q63_t) S->A2 * S->state[1]; + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t) (acc >> 31u); + /* out += y[n-1] */ + out += S->state[2]; + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + /* return to application */ + return (out); +} + +/** + @brief Process function for the Q15 PID Control. + @param[in,out] *S points to an instance of the Q15 PID Control structure + @param[in] in input sample to process + @return out processed output sample. + + Scaling and Overflow Behavior: + \par + The function is implemented using a 64-bit internal accumulator. + Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + Lastly, the accumulator is saturated to yield a result in 1.15 format. +*/ + +static __INLINE q15_t arm_pid_q15( + arm_pid_instance_q15* S, + q15_t in) +{ + q63_t acc; + q15_t out; + #ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE* vstate; + /* Implementation of PID controller */ + /* acc = A0 * x[n] */ + acc = (q31_t) __SMUAD(S->A0, in); + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t) *vstate, acc); + #else + /* acc = A0 * x[n] */ + acc = ((q31_t) S->A0) * in; + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t) S->A1 * S->state[0]; + acc += (q31_t) S->A2 * S->state[1]; + #endif + /* acc += y[n-1] */ + acc += (q31_t) S->state[2] << 15; + /* saturate the output */ + out = (q15_t) (__SSAT((acc >> 15), 16)); + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + /* return to application */ + return (out); +} + +/** + @} end of PID group +*/ + + +/** + @brief Floating-point matrix inverse. + @param[in] *src points to the instance of the input floating-point matrix structure. + @param[out] *dst points to the instance of the output floating-point matrix structure. + @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. +*/ + +arm_status arm_mat_inverse_f32( + const arm_matrix_instance_f32* src, + arm_matrix_instance_f32* dst); + + + +/** + @ingroup groupController +*/ + + +/** + @defgroup clarke Vector Clarke Transform + Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + in the two-phase orthogonal stator axis Ialpha and Ibeta. + When Ialpha is superposed with Ia as shown in the figure below + \image html clarke.gif Stator current space vector and its components in (a,b). + and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + can be calculated using only Ia and Ib. + + The function operates on a single sample of data and each call to the function returns the processed output. + The library provides separate functions for Q31 and floating-point data types. + \par Algorithm + \image html clarkeFormula.gif + where Ia and Ib are the instantaneous stator phases and + pIalpha and pIbeta are the two coordinates of time invariant vector. + \par Fixed-Point Behavior + Care must be taken when using the Q31 version of the Clarke transform. + In particular, the overflow and saturation behavior of the accumulator used must be considered. + Refer to the function specific documentation below for usage guidelines. +*/ + +/** + @addtogroup clarke + @{ +*/ + +/** + + @brief Floating-point Clarke transform + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + @return none. +*/ + +static __INLINE void arm_clarke_f32( + float32_t Ia, + float32_t Ib, + float32_t* pIalpha, + float32_t* pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = + ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); +} + +/** + @brief Clarke transform for Q31 version + @param[in] Ia input three-phase coordinate a + @param[in] Ib input three-phase coordinate b + @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + @return none. + + Scaling and Overflow Behavior: + \par + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. +*/ + +static __INLINE void arm_clarke_q31( + q31_t Ia, + q31_t Ib, + q31_t* pIalpha, + q31_t* pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + @} end of clarke group +*/ + +/** + @brief Converts the elements of the Q7 vector to Q31 vector. + @param[in] *pSrc input pointer + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_q7_to_q31( + q7_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + + + +/** + @ingroup groupController +*/ + +/** + @defgroup inv_clarke Vector Inverse Clarke Transform + Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + + The function operates on a single sample of data and each call to the function returns the processed output. + The library provides separate functions for Q31 and floating-point data types. + \par Algorithm + \image html clarkeInvFormula.gif + where pIa and pIb are the instantaneous stator phases and + Ialpha and Ibeta are the two coordinates of time invariant vector. + \par Fixed-Point Behavior + Care must be taken when using the Q31 version of the Clarke transform. + In particular, the overflow and saturation behavior of the accumulator used must be considered. + Refer to the function specific documentation below for usage guidelines. +*/ + +/** + @addtogroup inv_clarke + @{ +*/ + +/** + @brief Floating-point Inverse Clarke transform + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] *pIa points to output three-phase coordinate a + @param[out] *pIb points to output three-phase coordinate b + @return none. +*/ + + +static __INLINE void arm_inv_clarke_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pIa, + float32_t* pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; +} + +/** + @brief Inverse Clarke transform for Q31 version + @param[in] Ialpha input two-phase orthogonal vector axis alpha + @param[in] Ibeta input two-phase orthogonal vector axis beta + @param[out] *pIa points to output three-phase coordinate a + @param[out] *pIb points to output three-phase coordinate b + @return none. + + Scaling and Overflow Behavior: + \par + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the subtraction, hence there is no risk of overflow. +*/ + +static __INLINE void arm_inv_clarke_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pIa, + q31_t* pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); +} + +/** + @} end of inv_clarke group +*/ + +/** + @brief Converts the elements of the Q7 vector to Q15 vector. + @param[in] *pSrc input pointer + @param[out] *pDst output pointer + @param[in] blockSize number of samples to process + @return none. +*/ +void arm_q7_to_q15( + q7_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + + + +/** + @ingroup groupController +*/ + +/** + @defgroup park Vector Park Transform + + Forward Park transform converts the input two-coordinate vector to flux and torque components. + The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + from the stationary to the moving reference frame and control the spatial relationship between + the stator vector current and rotor flux vector. + If we consider the d axis aligned with the rotor flux, the diagram below shows the + current vector and the relationship from the two reference frames: + \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + + The function operates on a single sample of data and each call to the function returns the processed output. + The library provides separate functions for Q31 and floating-point data types. + \par Algorithm + \image html parkFormula.gif + where Ialpha and Ibeta are the stator vector components, + pId and pIq are rotor vector components and cosVal and sinVal are the + cosine and sine values of theta (rotor flux position). + \par Fixed-Point Behavior + Care must be taken when using the Q31 version of the Park transform. + In particular, the overflow and saturation behavior of the accumulator used must be considered. + Refer to the function specific documentation below for usage guidelines. +*/ + +/** + @addtogroup park + @{ +*/ + +/** + @brief Floating-point Park transform + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] *pId points to output rotor reference frame d + @param[out] *pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none. + + The function implements the forward Park transform. + +*/ + +static __INLINE void arm_park_f32( + float32_t Ialpha, + float32_t Ibeta, + float32_t* pId, + float32_t* pIq, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} + +/** + @brief Park transform for Q31 version + @param[in] Ialpha input two-phase vector coordinate alpha + @param[in] Ibeta input two-phase vector coordinate beta + @param[out] *pId points to output rotor reference frame d + @param[out] *pIq points to output rotor reference frame q + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none. + + Scaling and Overflow Behavior: + \par + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition and subtraction, hence there is no risk of overflow. +*/ + + +static __INLINE void arm_park_q31( + q31_t Ialpha, + q31_t Ibeta, + q31_t* pId, + q31_t* pIq, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + @} end of park group +*/ + +/** + @brief Converts the elements of the Q7 vector to floating-point vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q7_to_float( + q7_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + @ingroup groupController +*/ + +/** + @defgroup inv_park Vector Inverse Park transform + Inverse Park transform converts the input flux and torque components to two-coordinate vector. + + The function operates on a single sample of data and each call to the function returns the processed output. + The library provides separate functions for Q31 and floating-point data types. + \par Algorithm + \image html parkInvFormula.gif + where pIalpha and pIbeta are the stator vector components, + Id and Iq are rotor vector components and cosVal and sinVal are the + cosine and sine values of theta (rotor flux position). + \par Fixed-Point Behavior + Care must be taken when using the Q31 version of the Park transform. + In particular, the overflow and saturation behavior of the accumulator used must be considered. + Refer to the function specific documentation below for usage guidelines. +*/ + +/** + @addtogroup inv_park + @{ +*/ + +/** + @brief Floating-point Inverse Park transform + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none. +*/ + +static __INLINE void arm_inv_park_f32( + float32_t Id, + float32_t Iq, + float32_t* pIalpha, + float32_t* pIbeta, + float32_t sinVal, + float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} + + +/** + @brief Inverse Park transform for Q31 version + @param[in] Id input coordinate of rotor reference frame d + @param[in] Iq input coordinate of rotor reference frame q + @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + @param[in] sinVal sine value of rotation angle theta + @param[in] cosVal cosine value of rotation angle theta + @return none. + + Scaling and Overflow Behavior: + \par + The function is implemented using an internal 32-bit accumulator. + The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + There is saturation on the addition, hence there is no risk of overflow. +*/ + + +static __INLINE void arm_inv_park_q31( + q31_t Id, + q31_t Iq, + q31_t* pIalpha, + q31_t* pIbeta, + q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +} + +/** + @} end of Inverse park group +*/ + + +/** + @brief Converts the elements of the Q31 vector to floating-point vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q31_to_float( + q31_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + +/** + @ingroup groupInterpolation +*/ + +/** + @defgroup LinearInterpolate Linear Interpolation + + Linear interpolation is a method of curve fitting using linear polynomials. + Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + + \par + \image html LinearInterp.gif "Linear interpolation" + + \par + A Linear Interpolate function calculates an output value(y), for the input(x) + using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + + \par Algorithm: + 
+         y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+         where x0, x1 are nearest values of input x
+               y0, y1 are nearest values to output y
+
+ + \par + This set of functions implements Linear interpolation process + for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + sample of data and each call to the function returns a single processed value. + S points to an instance of the Linear Interpolate function data structure. + x is the input sample value. The functions returns the output value. + + \par + if x is outside of the table boundary, Linear interpolation returns first value of the table + if x is below input range and returns last value of table if x is above range. +*/ + +/** + @addtogroup LinearInterpolate + @{ +*/ + +/** + @brief Process function for the floating-point Linear Interpolation Function. + @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + @param[in] x input sample to process + @return y processed output sample. + +*/ + +static __INLINE float32_t arm_linear_interp_f32( + arm_linear_interp_instance_f32* S, + float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t* pYData = S->pYData; /* pointer to output table */ + /* Calculation of index */ + i = (int32_t) ((x - S->x1) / xSpacing); + + if(i < 0) + { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } + else if((uint32_t)i >= S->nValues) + { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } + else + { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + } + + /* returns output value */ + return (y); +} + +/** + + @brief Process function for the Q31 Linear Interpolation Function. + @param[in] *pYData pointer to Q31 Linear Interpolation table + @param[in] x input sample to process + @param[in] nValues number of table values + @return y processed output sample. + + \par + Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + This function can support maximum of table size 2^12. + +*/ + + +static __INLINE q31_t arm_linear_interp_q31( + q31_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t) (((q63_t) y1 * fract) >> 32)); + /* Convert y to 1.31 format */ + return (y << 1u); + } +} + +/** + + @brief Process function for the Q15 Linear Interpolation Function. + @param[in] *pYData pointer to Q15 Linear Interpolation table + @param[in] x input sample to process + @param[in] nValues number of table values + @return y processed output sample. + + \par + Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + This function can support maximum of table size 2^12. + +*/ + + +static __INLINE q15_t arm_linear_interp_q15( + q15_t* pYData, + q31_t x, + uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if(index >= (int32_t)(nValues - 1)) + { + return (pYData[nValues - 1]); + } + else if(index < 0) + { + return (pYData[0]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t) y0 * (0xFFFFF - fract)); + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t) y1 * (fract)); + /* convert y to 1.15 format */ + return (y >> 20); + } +} + +/** + + @brief Process function for the Q7 Linear Interpolation Function. + @param[in] *pYData pointer to Q7 Linear Interpolation table + @param[in] x input sample to process + @param[in] nValues number of table values + @return y processed output sample. + + \par + Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + This function can support maximum of table size 2^12. +*/ + + +static __INLINE q7_t arm_linear_interp_q7( + q7_t* pYData, + q31_t x, + uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) + { + return (pYData[0]); + } + + index = (x >> 20) & 0xfff; + + if(index >= (nValues - 1)) + { + return (pYData[nValues - 1]); + } + else + { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + /* convert y to 1.7(q7) format */ + return (y >> 20u); + } +} +/** + @} end of LinearInterpolate group +*/ + +/** + @brief Fast approximation to the trigonometric sine function for floating-point data. + @param[in] x input value in radians. + @return sin(x). +*/ + +float32_t arm_sin_f32( + float32_t x); + +/** + @brief Fast approximation to the trigonometric sine function for Q31 data. + @param[in] x Scaled input value in radians. + @return sin(x). +*/ + +q31_t arm_sin_q31( + q31_t x); + +/** + @brief Fast approximation to the trigonometric sine function for Q15 data. + @param[in] x Scaled input value in radians. + @return sin(x). +*/ + +q15_t arm_sin_q15( + q15_t x); + +/** + @brief Fast approximation to the trigonometric cosine function for floating-point data. + @param[in] x input value in radians. + @return cos(x). +*/ + +float32_t arm_cos_f32( + float32_t x); + +/** + @brief Fast approximation to the trigonometric cosine function for Q31 data. + @param[in] x Scaled input value in radians. + @return cos(x). +*/ + +q31_t arm_cos_q31( + q31_t x); + +/** + @brief Fast approximation to the trigonometric cosine function for Q15 data. + @param[in] x Scaled input value in radians. + @return cos(x). +*/ + +q15_t arm_cos_q15( + q15_t x); + + +/** + @ingroup groupFastMath +*/ + + +/** + @defgroup SQRT Square Root + + Computes the square root of a number. + There are separate functions for Q15, Q31, and floating-point data types. + The square root function is computed using the Newton-Raphson algorithm. + This is an iterative algorithm of the form: + 
+        x1 = x0 - f(x0)/f'(x0)
+
+ where x1 is the current estimate, + x0 is the previous estimate, and + f'(x0) is the derivative of f() evaluated at x0. + For the square root function, the algorithm reduces to: + 
+       x0 = in/2                         [initial guess]
+       x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+
+*/ + + +/** + @addtogroup SQRT + @{ +*/ + +/** + @brief Floating-point square root function. + @param[in] in input value. + @param[out] *pOut square root of input value. + @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + in is negative value and returns zero output for negative values. +*/ + +static __INLINE arm_status arm_sqrt_f32( + float32_t in, + float32_t* pOut) +{ + if(in > 0) + { +// #if __FPU_USED + #if (__FPU_USED == 1) && defined ( __CC_ARM ) + *pOut = __sqrtf(in); + #else + *pOut = sqrtf(in); + #endif + return (ARM_MATH_SUCCESS); + } + else + { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } +} + + +/** + @brief Q31 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + @param[out] *pOut square root of input value. + @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + in is negative value and returns zero output for negative values. +*/ +arm_status arm_sqrt_q31( + q31_t in, + q31_t* pOut); + +/** + @brief Q15 square root function. + @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + @param[out] *pOut square root of input value. + @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + in is negative value and returns zero output for negative values. +*/ +arm_status arm_sqrt_q15( + q15_t in, + q15_t* pOut); + +/** + @} end of SQRT group +*/ + + + + + + +/** + @brief floating-point Circular write function. +*/ + +static __INLINE void arm_circularWrite_f32( + int32_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const int32_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + /* Copy the value of Index pointer that points + to the current location where the input samples to be copied */ + wOffset = *writeOffset; + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + /* Update the input pointer */ + src += srcInc; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + @brief floating-point Circular Read function. +*/ +static __INLINE void arm_circularRead_f32( + int32_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + int32_t* dst, + int32_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + /* Copy the value of Index pointer that points + to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + /* Update the input pointer */ + dst += dstInc; + + if(dst == (int32_t*) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + +/** + @brief Q15 Circular write function. +*/ + +static __INLINE void arm_circularWrite_q15( + q15_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q15_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + /* Copy the value of Index pointer that points + to the current location where the input samples to be copied */ + wOffset = *writeOffset; + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + /* Update the input pointer */ + src += srcInc; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + @brief Q15 Circular Read function. +*/ +static __INLINE void arm_circularRead_q15( + q15_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q15_t* dst, + q15_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + /* Copy the value of Index pointer that points + to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q15_t*) dst_end) + { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + @brief Q7 Circular write function. +*/ + +static __INLINE void arm_circularWrite_q7( + q7_t* circBuffer, + int32_t L, + uint16_t* writeOffset, + int32_t bufferInc, + const q7_t* src, + int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + /* Copy the value of Index pointer that points + to the current location where the input samples to be copied */ + wOffset = *writeOffset; + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + /* Update the input pointer */ + src += srcInc; + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + + if(wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + + + +/** + @brief Q7 Circular Read function. +*/ +static __INLINE void arm_circularRead_q7( + q7_t* circBuffer, + int32_t L, + int32_t* readOffset, + int32_t bufferInc, + q7_t* dst, + q7_t* dst_base, + int32_t dst_length, + int32_t dstInc, + uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + /* Copy the value of Index pointer that points + to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t) (dst_base + dst_length); + /* Loop over the blockSize */ + i = blockSize; + + while(i > 0u) + { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + /* Update the input pointer */ + dst += dstInc; + + if(dst == (q7_t*) dst_end) + { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if(rOffset >= L) + { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + + +/** + @brief Sum of the squares of the elements of a Q31 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_power_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + @brief Sum of the squares of the elements of a floating-point vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_power_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + @brief Sum of the squares of the elements of a Q15 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_power_q15( + q15_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + @brief Sum of the squares of the elements of a Q7 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_power_q7( + q7_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + @brief Mean value of a Q7 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_mean_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult); + +/** + @brief Mean value of a Q15 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ +void arm_mean_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + @brief Mean value of a Q31 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ +void arm_mean_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + @brief Mean value of a floating-point vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ +void arm_mean_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + @brief Variance of the elements of a floating-point vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_var_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + @brief Variance of the elements of a Q31 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_var_q31( + q31_t* pSrc, + uint32_t blockSize, + q63_t* pResult); + +/** + @brief Variance of the elements of a Q15 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_var_q15( + q15_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + @brief Root Mean Square of the elements of a floating-point vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_rms_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + @brief Root Mean Square of the elements of a Q31 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_rms_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + @brief Root Mean Square of the elements of a Q15 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_rms_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + @brief Standard deviation of the elements of a floating-point vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_std_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult); + +/** + @brief Standard deviation of the elements of a Q31 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_std_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult); + +/** + @brief Standard deviation of the elements of a Q15 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output value. + @return none. +*/ + +void arm_std_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult); + +/** + @brief Floating-point complex magnitude + @param[in] *pSrc points to the complex input vector + @param[out] *pDst points to the real output vector + @param[in] numSamples number of complex samples in the input vector + @return none. +*/ + +void arm_cmplx_mag_f32( + float32_t* pSrc, + float32_t* pDst, + uint32_t numSamples); + +/** + @brief Q31 complex magnitude + @param[in] *pSrc points to the complex input vector + @param[out] *pDst points to the real output vector + @param[in] numSamples number of complex samples in the input vector + @return none. +*/ + +void arm_cmplx_mag_q31( + q31_t* pSrc, + q31_t* pDst, + uint32_t numSamples); + +/** + @brief Q15 complex magnitude + @param[in] *pSrc points to the complex input vector + @param[out] *pDst points to the real output vector + @param[in] numSamples number of complex samples in the input vector + @return none. +*/ + +void arm_cmplx_mag_q15( + q15_t* pSrc, + q15_t* pDst, + uint32_t numSamples); + +/** + @brief Q15 complex dot product + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] numSamples number of complex samples in each vector + @param[out] *realResult real part of the result returned here + @param[out] *imagResult imaginary part of the result returned here + @return none. +*/ + +void arm_cmplx_dot_prod_q15( + q15_t* pSrcA, + q15_t* pSrcB, + uint32_t numSamples, + q31_t* realResult, + q31_t* imagResult); + +/** + @brief Q31 complex dot product + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] numSamples number of complex samples in each vector + @param[out] *realResult real part of the result returned here + @param[out] *imagResult imaginary part of the result returned here + @return none. +*/ + +void arm_cmplx_dot_prod_q31( + q31_t* pSrcA, + q31_t* pSrcB, + uint32_t numSamples, + q63_t* realResult, + q63_t* imagResult); + +/** + @brief Floating-point complex dot product + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[in] numSamples number of complex samples in each vector + @param[out] *realResult real part of the result returned here + @param[out] *imagResult imaginary part of the result returned here + @return none. +*/ + +void arm_cmplx_dot_prod_f32( + float32_t* pSrcA, + float32_t* pSrcB, + uint32_t numSamples, + float32_t* realResult, + float32_t* imagResult); + +/** + @brief Q15 complex-by-real multiplication + @param[in] *pSrcCmplx points to the complex input vector + @param[in] *pSrcReal points to the real input vector + @param[out] *pCmplxDst points to the complex output vector + @param[in] numSamples number of samples in each vector + @return none. +*/ + +void arm_cmplx_mult_real_q15( + q15_t* pSrcCmplx, + q15_t* pSrcReal, + q15_t* pCmplxDst, + uint32_t numSamples); + +/** + @brief Q31 complex-by-real multiplication + @param[in] *pSrcCmplx points to the complex input vector + @param[in] *pSrcReal points to the real input vector + @param[out] *pCmplxDst points to the complex output vector + @param[in] numSamples number of samples in each vector + @return none. +*/ + +void arm_cmplx_mult_real_q31( + q31_t* pSrcCmplx, + q31_t* pSrcReal, + q31_t* pCmplxDst, + uint32_t numSamples); + +/** + @brief Floating-point complex-by-real multiplication + @param[in] *pSrcCmplx points to the complex input vector + @param[in] *pSrcReal points to the real input vector + @param[out] *pCmplxDst points to the complex output vector + @param[in] numSamples number of samples in each vector + @return none. +*/ + +void arm_cmplx_mult_real_f32( + float32_t* pSrcCmplx, + float32_t* pSrcReal, + float32_t* pCmplxDst, + uint32_t numSamples); + +/** + @brief Minimum value of a Q7 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *result is output pointer + @param[in] index is the array index of the minimum value in the input buffer. + @return none. +*/ + +void arm_min_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* result, + uint32_t* index); + +/** + @brief Minimum value of a Q15 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output pointer + @param[in] *pIndex is the array index of the minimum value in the input buffer. + @return none. +*/ + +void arm_min_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + +/** + @brief Minimum value of a Q31 vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output pointer + @param[out] *pIndex is the array index of the minimum value in the input buffer. + @return none. +*/ +void arm_min_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + +/** + @brief Minimum value of a floating-point vector. + @param[in] *pSrc is input pointer + @param[in] blockSize is the number of samples to process + @param[out] *pResult is output pointer + @param[out] *pIndex is the array index of the minimum value in the input buffer. + @return none. +*/ + +void arm_min_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + +/** + @brief Maximum value of a Q7 vector. + @param[in] *pSrc points to the input buffer + @param[in] blockSize length of the input vector + @param[out] *pResult maximum value returned here + @param[out] *pIndex index of maximum value returned here + @return none. +*/ + +void arm_max_q7( + q7_t* pSrc, + uint32_t blockSize, + q7_t* pResult, + uint32_t* pIndex); + +/** + @brief Maximum value of a Q15 vector. + @param[in] *pSrc points to the input buffer + @param[in] blockSize length of the input vector + @param[out] *pResult maximum value returned here + @param[out] *pIndex index of maximum value returned here + @return none. +*/ + +void arm_max_q15( + q15_t* pSrc, + uint32_t blockSize, + q15_t* pResult, + uint32_t* pIndex); + +/** + @brief Maximum value of a Q31 vector. + @param[in] *pSrc points to the input buffer + @param[in] blockSize length of the input vector + @param[out] *pResult maximum value returned here + @param[out] *pIndex index of maximum value returned here + @return none. +*/ + +void arm_max_q31( + q31_t* pSrc, + uint32_t blockSize, + q31_t* pResult, + uint32_t* pIndex); + +/** + @brief Maximum value of a floating-point vector. + @param[in] *pSrc points to the input buffer + @param[in] blockSize length of the input vector + @param[out] *pResult maximum value returned here + @param[out] *pIndex index of maximum value returned here + @return none. +*/ + +void arm_max_f32( + float32_t* pSrc, + uint32_t blockSize, + float32_t* pResult, + uint32_t* pIndex); + +/** + @brief Q15 complex-by-complex multiplication + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] numSamples number of complex samples in each vector + @return none. +*/ + +void arm_cmplx_mult_cmplx_q15( + q15_t* pSrcA, + q15_t* pSrcB, + q15_t* pDst, + uint32_t numSamples); + +/** + @brief Q31 complex-by-complex multiplication + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] numSamples number of complex samples in each vector + @return none. +*/ + +void arm_cmplx_mult_cmplx_q31( + q31_t* pSrcA, + q31_t* pSrcB, + q31_t* pDst, + uint32_t numSamples); + +/** + @brief Floating-point complex-by-complex multiplication + @param[in] *pSrcA points to the first input vector + @param[in] *pSrcB points to the second input vector + @param[out] *pDst points to the output vector + @param[in] numSamples number of complex samples in each vector + @return none. +*/ + +void arm_cmplx_mult_cmplx_f32( + float32_t* pSrcA, + float32_t* pSrcB, + float32_t* pDst, + uint32_t numSamples); + +/** + @brief Converts the elements of the floating-point vector to Q31 vector. + @param[in] *pSrc points to the floating-point input vector + @param[out] *pDst points to the Q31 output vector + @param[in] blockSize length of the input vector + @return none. +*/ +void arm_float_to_q31( + float32_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + +/** + @brief Converts the elements of the floating-point vector to Q15 vector. + @param[in] *pSrc points to the floating-point input vector + @param[out] *pDst points to the Q15 output vector + @param[in] blockSize length of the input vector + @return none +*/ +void arm_float_to_q15( + float32_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Converts the elements of the floating-point vector to Q7 vector. + @param[in] *pSrc points to the floating-point input vector + @param[out] *pDst points to the Q7 output vector + @param[in] blockSize length of the input vector + @return none +*/ +void arm_float_to_q7( + float32_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + @brief Converts the elements of the Q31 vector to Q15 vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q31_to_q15( + q31_t* pSrc, + q15_t* pDst, + uint32_t blockSize); + +/** + @brief Converts the elements of the Q31 vector to Q7 vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q31_to_q7( + q31_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + +/** + @brief Converts the elements of the Q15 vector to floating-point vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q15_to_float( + q15_t* pSrc, + float32_t* pDst, + uint32_t blockSize); + + +/** + @brief Converts the elements of the Q15 vector to Q31 vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q15_to_q31( + q15_t* pSrc, + q31_t* pDst, + uint32_t blockSize); + + +/** + @brief Converts the elements of the Q15 vector to Q7 vector. + @param[in] *pSrc is input pointer + @param[out] *pDst is output pointer + @param[in] blockSize is the number of samples to process + @return none. +*/ +void arm_q15_to_q7( + q15_t* pSrc, + q7_t* pDst, + uint32_t blockSize); + + +/** + @ingroup groupInterpolation +*/ + +/** + @defgroup BilinearInterpolate Bilinear Interpolation + + Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + The underlying function f(x, y) is sampled on a regular grid and the interpolation process + determines values between the grid points. + Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + Bilinear interpolation is often used in image processing to rescale images. + The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + + Algorithm + \par + The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + For floating-point, the instance structure is defined as: + 
+     typedef struct
+     {
+       uint16_t numRows;
+       uint16_t numCols;
+       float32_t *pData;
+    } arm_bilinear_interp_instance_f32;
+
+ + \par + where numRows specifies the number of rows in the table; + numCols specifies the number of columns in the table; + and pData points to an array of size numRows*numCols values. + The data table pTable is organized in row order and the supplied data values fall on integer indexes. + That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + + \par + Let (x, y) specify the desired interpolation point. Then define: + 
+       XF = floor(x)
+       YF = floor(y)
+
+ \par + The interpolated output point is computed as: + 
+    f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+             + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+             + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+             + f(XF+1, YF+1) * (x-XF)*(y-YF)
+
+ Note that the coordinates (x, y) contain integer and fractional components. + The integer components specify which portion of the table to use while the + fractional components control the interpolation processor. + + \par + if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. +*/ + +/** + @addtogroup BilinearInterpolate + @{ +*/ + +/** + + @brief Floating-point bilinear interpolation. + @param[in,out] *S points to an instance of the interpolation structure. + @param[in] X interpolation coordinate. + @param[in] Y interpolation coordinate. + @return out interpolated value. +*/ + + +static __INLINE float32_t arm_bilinear_interp_f32( + const arm_bilinear_interp_instance_f32* S, + float32_t X, + float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t* pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + xIndex = (int32_t) X; + yIndex = (int32_t) Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 + || yIndex > (S->numCols - 1)) + { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex) * S->numCols; + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + /* return to application */ + return (out); +} + +/** + + @brief Q31 bilinear interpolation. + @param[in,out] *S points to an instance of the interpolation structure. + @param[in] X interpolation coordinate in 12.20 format. + @param[in] Y interpolation coordinate in 12.20 format. + @return out interpolated value. +*/ + +static __INLINE q31_t arm_bilinear_interp_q31( + arm_bilinear_interp_instance_q31* S, + q31_t X, + q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); + acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); +} + +/** + @brief Q15 bilinear interpolation. + @param[in,out] *S points to an instance of the interpolation structure. + @param[in] X interpolation coordinate in 12.20 format. + @param[in] Y interpolation coordinate in 12.20 format. + @return out interpolated value. +*/ + +static __INLINE q15_t arm_bilinear_interp_q15( + arm_bilinear_interp_instance_q15* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t) out * (0xFFFFF - yfract)); + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t) out * (xfract)); + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); + acc += ((q63_t) out * (yfract)); + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); +} + +/** + @brief Q7 bilinear interpolation. + @param[in,out] *S points to an instance of the interpolation structure. + @param[in] X interpolation coordinate in 12.20 format. + @param[in] Y interpolation coordinate in 12.20 format. + @return out interpolated value. +*/ + +static __INLINE q7_t arm_bilinear_interp_q7( + arm_bilinear_interp_instance_q7* S, + q31_t X, + q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t* pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) + { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t) out * (0xFFFFF - yfract))); + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t) out * (xfract))); + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t) out * (yfract))); + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t) out * (xfract))); + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); +} + +/** + @} end of BilinearInterpolate group +*/ + + +#if defined ( __CC_ARM ) //Keil +//SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) + +//Enter low optimization region - place directly above function definition +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("push") \ + _Pragma ("O1") + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT \ + _Pragma ("pop") + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR +//SMMLA +#define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +//Enter low optimization region - place directly above function definition +#define LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ + _Pragma ("optimize=low") + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) +//SMMLA +#define multAcc_32x32_keep32_R(a, x, y) \ + a += (q31_t) (((q63_t) x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32_R(a, x, y) \ + a -= (q31_t) (((q63_t) x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32_R(a, x, y) \ + a = (q31_t) (((q63_t) x * y ) >> 32) + +#define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) + +#define LOW_OPTIMIZATION_EXIT + +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + + + + + +#ifdef __cplusplus +} +#endif + + +#endif /* _ARM_MATH_H */ + + +/** + + End of file. +*/ diff --git a/ota_boot/source/misc/CMSIS/include/core_cm0.h b/ota_boot/source/misc/CMSIS/include/core_cm0.h new file mode 100644 index 0000000..5804170 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/core_cm0.h @@ -0,0 +1,690 @@ +/**************************************************************************//** + @file core_cm0.h + @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + @version V3.20 + @date 25. February 2013 + + @note + + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. +*/ + + +/******************************************************************************* + CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ +*/ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0_REV +#define __CM0_REV 0x0000 +#warning "__CM0_REV not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ +*/ + +/** \brief Union type to access the Application Program Status Register (APSR). +*/ +typedef union +{ + struct + { + #if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + #else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + #endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). +*/ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). +*/ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + #if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + #else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + #endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). +*/ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ +*/ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +*/ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ +*/ + +/** \brief Structure type to access the System Control Block (SCB). +*/ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ +*/ + +/** \brief Structure type to access the System Timer (SysTick). +*/ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ +*/ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ +*/ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ +*/ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. +*/ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. +*/ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. +*/ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + if(IRQn < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. +*/ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ +*/ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + +*/ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/ota_boot/source/misc/CMSIS/include/core_cm0plus.h b/ota_boot/source/misc/CMSIS/include/core_cm0plus.h new file mode 100644 index 0000000..a7384af --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/core_cm0plus.h @@ -0,0 +1,801 @@ +/**************************************************************************//** + @file core_cm0plus.h + @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + @version V3.20 + @date 25. February 2013 + + @note + + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. +*/ + + +/******************************************************************************* + CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ +*/ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM0PLUS_REV +#define __CM0PLUS_REV 0x0000 +#warning "__CM0PLUS_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 0 +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 2 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ +*/ + +/** \brief Union type to access the Application Program Status Register (APSR). +*/ +typedef union +{ + struct + { + #if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + #else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + #endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). +*/ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). +*/ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + #if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + #else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + #endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). +*/ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ +*/ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). +*/ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ +*/ + +/** \brief Structure type to access the System Control Block (SCB). +*/ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + #if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + #else + uint32_t RESERVED0; + #endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ +*/ + +/** \brief Structure type to access the System Timer (SysTick). +*/ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ +*/ + +/** \brief Structure type to access the Memory Protection Unit (MPU). +*/ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ +*/ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ +*/ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ +*/ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. +*/ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. +*/ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. +*/ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) + { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } + else + { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); + } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. +*/ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + if(IRQn < 0) + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M0 system interrupts */ + else + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. +*/ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ +*/ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + +*/ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/ota_boot/source/misc/CMSIS/include/core_cmFunc.h b/ota_boot/source/misc/CMSIS/include/core_cmFunc.h new file mode 100644 index 0000000..dc41093 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/core_cmFunc.h @@ -0,0 +1,638 @@ +/**************************************************************************//** + @file core_cmFunc.h + @brief CMSIS Cortex-M Core Function Access Header File + @version V3.20 + @date 25. February 2013 + + @note + + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value +*/ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set +*/ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value +*/ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value +*/ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value +*/ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value +*/ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set +*/ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value +*/ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set +*/ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value +*/ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask +*/ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. +*/ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. +*/ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value +*/ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set +*/ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value +*/ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set +*/ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value +*/ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); + #else + return(0); + #endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set +*/ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); + #endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ +// https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html#Clobbers-and-Scratch-Registers +// The clobber list should not contain the stack pointer register. +// This is because the compiler requires the value of the stack pointer +// to be the same after an asm statement as it was on entry to the statement. +// However, previous versions of GCC did not enforce this rule and allowed the +// stack pointer to appear in the list, with unclear semantics. +// This behavior is deprecated and listing the stack pointer may become an error +// in future versions of GCC. +#if __GNUC__ >= 9 + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack)); +#else + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +#endif +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); + #else + return(0); + #endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); + #endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + The CMSIS functions have been implemented as intrinsics in the compiler. + Please use "carm -?i" to get an up to date list of all instrinsics, + Including the CMSIS ones. +*/ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/ota_boot/source/misc/CMSIS/include/core_cmInstr.h b/ota_boot/source/misc/CMSIS/include/core_cmInstr.h new file mode 100644 index 0000000..e02cf77 --- /dev/null +++ b/ota_boot/source/misc/CMSIS/include/core_cmInstr.h @@ -0,0 +1,677 @@ +/**************************************************************************//** + @file core_cmInstr.h + @brief CMSIS Cortex-M Core Instruction Access Header File + @version V3.20 + @date 05. March 2013 + + @note + + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. +*/ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. +*/ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. +*/ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. +*/ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. +*/ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. +*/ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. +*/ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value +*/ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value +*/ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value +*/ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value +*/ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. +*/ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + + /** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ + #define __RBIT __rbit + + + /** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + + /** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + + /** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + + /** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXB(value, ptr) __strex(value, ptr) + + + /** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXH(value, ptr) __strex(value, ptr) + + + /** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ + #define __STREXW(value, ptr) __strex(value, ptr) + + + /** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ + #define __CLREX __clrex + + + /** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ + #define __SSAT __ssat + + + /** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ + #define __USAT __usat + + + /** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ + #define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + For thumb1, use low register (r0-r7), specified by constrant "l" + Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) + #define __CMSIS_GCC_OUT_REG(r) "=l" (r) + #define __CMSIS_GCC_USE_REG(r) "l" (r) +#else + #define __CMSIS_GCC_OUT_REG(r) "=r" (r) + #define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); + #else + uint32_t result; + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); + #endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); + #else + uint32_t result; + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); + #endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. +*/ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t* addr) +{ + uint32_t result; + #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); + #else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + #endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t* addr) +{ + uint32_t result; + #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); + #else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); + #endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t* addr) +{ + uint32_t result; + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t* addr) +{ + uint32_t result; + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t* addr) +{ + uint32_t result; + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t* addr) +{ + uint32_t result; + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value +*/ +#define __SSAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value +*/ +#define __USAT(ARG1,ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value +*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + The CMSIS functions have been implemented as intrinsics in the compiler. + Please use "carm -?i" to get an up to date list of all intrinsics, + Including the CMSIS ones. +*/ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/ota_boot/source/misc/bb_rom_sym_m0.gcc b/ota_boot/source/misc/bb_rom_sym_m0.gcc new file mode 100644 index 0000000..1c560c2 --- /dev/null +++ b/ota_boot/source/misc/bb_rom_sym_m0.gcc @@ -0,0 +1,1023 @@ +bx_to_application = 0x000000d5; +P256_mul64 = 0x000001f9; +P256_mul128 = 0x0000029d; +P256_mulmod = 0x0000032d; +P256_sqr64 = 0x00000567; +P256_sqr128 = 0x000005c5; +P256_sqrmod = 0x00000641; +P256_addmod = 0x00000735; +P256_submod = 0x00000791; +P256_load_1 = 0x000007c3; +P256_to_montgomery = 0x000007d7; +P256_from_montgomery = 0x00000801; +P256_point_is_on_curve = 0x0000081b; +P256_greater_or_equal_than = 0x0000086d; +P256_negate_mod_m_if = 0x00000887; +P256_copy32 = 0x000008a9; +P256_copy32_unaligned = 0x000008b5; +P256_select = 0x000008c7; +P256_double_j = 0x00000927; +P256_add_j = 0x0000092b; +P256_div2mod = 0x00000983; +P256_interpreter = 0x000009e9; +P256_sqrmod_many_and_mulmod = 0x00000a4d; +P256_modinv = 0x00000a6d; +P256_jacobian_to_affine = 0x00000af7; +P256_abs_int = 0x00000b33; +P256_pointmult = 0x00000b41; +P256_ecdh_keygen = 0x00000d03; +P256_ecdh_shared_secret = 0x00000d0b; +__aeabi_uidiv = 0x00000e09; +__aeabi_uidivmod = 0x00000e09; +__aeabi_idiv = 0x00000e35; +__aeabi_idivmod = 0x00000e35; +__aeabi_memcpy = 0x00000e81; +__aeabi_memcpy4 = 0x00000e81; +__aeabi_memcpy8 = 0x00000e81; +memcpy = 0x00000e81; +__aeabi_memset = 0x00000ea5; +__aeabi_memset4 = 0x00000ea5; +__aeabi_memset8 = 0x00000ea5; +__aeabi_memclr = 0x00000eb3; +__aeabi_memclr4 = 0x00000eb3; +__aeabi_memclr8 = 0x00000eb3; +memset = 0x00000eb7; +strlen = 0x00000ec9; +strcmp = 0x00000ed7; +memcmp = 0x00000ef3; +strncmp = 0x00000f0d; +strtok = 0x00000f2d; +__aeabi_uread4 = 0x00000f75; +__rt_uread4 = 0x00000f75; +_uread4 = 0x00000f75; +strtoul = 0x00000f89; +__rt_ctype_table = 0x00001001; +_strtoul = 0x00001009; +GPIO_IRQHandler = 0x0000112d; +HCI_CommandCompleteEvent = 0x00001175; +HCI_CommandStatusEvent = 0x000011fd; +HCI_DataBufferOverflowEvent = 0x00001251; +HCI_DisconnectCmd = 0x0000128d; +HCI_EXT_AdvEventNoticeCmd = 0x000012a1; +HCI_EXT_BuildRevisionCmd = 0x000012a9; +HCI_EXT_ClkDivOnHaltCmd = 0x000012e5; +HCI_EXT_ConnEventNoticeCmd = 0x0000130d; +HCI_EXT_DeclareNvUsageCmd = 0x00001315; +HCI_EXT_DecryptCmd = 0x00001339; +HCI_EXT_DelaySleepCmd = 0x0000137d; +HCI_EXT_DisconnectImmedCmd = 0x000013a5; +HCI_EXT_EnablePTMCmd = 0x000013cd; +HCI_EXT_EndModemTestCmd = 0x000013e1; +HCI_EXT_HaltDuringRfCmd = 0x00001409; +HCI_EXT_ModemHopTestTxCmd = 0x00001431; +HCI_EXT_ModemTestRxCmd = 0x00001459; +HCI_EXT_ModemTestTxCmd = 0x00001481; +HCI_EXT_NumComplPktsLimitCmd = 0x000014a5; +HCI_EXT_OnePktPerEvtCmd = 0x000014c9; +HCI_EXT_OverlappedProcessingCmd = 0x000014f5; +HCI_EXT_PERbyChanCmd = 0x0000151d; +HCI_EXT_PacketErrorRateCmd = 0x00001541; +HCI_EXT_ResetSystemCmd = 0x00001575; +HCI_EXT_SaveFreqTuneCmd = 0x0000159d; +HCI_EXT_SetBDADDRCmd = 0x000015c5; +HCI_EXT_SetFastTxResponseTimeCmd = 0x00001601; +HCI_EXT_SetFreqTuneCmd = 0x00001629; +HCI_EXT_SetLocalSupportedFeaturesCmd = 0x00001651; +HCI_EXT_SetMaxDtmTxPowerCmd = 0x00001679; +HCI_EXT_SetRxGainCmd = 0x000016a1; +HCI_EXT_SetSCACmd = 0x000016d1; +HCI_EXT_SetSlaveLatencyOverrideCmd = 0x000016f9; +HCI_EXT_SetTxPowerCmd = 0x00001721; +HCI_ExtTaskRegister = 0x00001751; +HCI_GAPTaskRegister = 0x0000175d; +HCI_HardwareErrorEvent = 0x00001769; +HCI_HostBufferSizeCmd = 0x000017b1; +HCI_HostNumCompletedPktCmd = 0x000017e1; +HCI_Init = 0x0000183d; +HCI_L2CAPTaskRegister = 0x00001879; +HCI_LE_AddDevToResolvingListCmd = 0x000018a1; +HCI_LE_AddWhiteListCmd = 0x000018bd; +HCI_LE_ClearAdvSetsCmd = 0x000018e1; +HCI_LE_ClearResolvingListCmd = 0x00001919; +HCI_LE_ClearWhiteListCmd = 0x00001935; +HCI_LE_Connection_CTE_Request_EnableCmd = 0x0000196d; +HCI_LE_Connection_CTE_Response_EnableCmd = 0x00001999; +HCI_LE_ConnectionlessCTE_TransmitEnableCmd = 0x000019c1; +HCI_LE_ConnectionlessCTE_TransmitParamCmd = 0x000019dd; +HCI_LE_ConnectionlessIQ_SampleEnableCmd = 0x00001a01; +HCI_LE_CreateConnCancelCmd = 0x00001a31; +HCI_LE_CreateConnCmd = 0x00001a4d; +HCI_LE_EncryptCmd = 0x00001a89; +HCI_LE_ExtendedCreateConnectionCmd = 0x00001ac1; +HCI_LE_LtkReqNegReplyCmd = 0x00001b09; +HCI_LE_LtkReqReplyCmd = 0x00001b31; +HCI_LE_PeriodicAdvertisingCreateSyncCancelCmd = 0x00001b59; +HCI_LE_PeriodicAdvertisingCreateSyncCmd = 0x00001b75; +HCI_LE_PeriodicAdvertisingTerminateSyncCmd = 0x00001b9d; +HCI_LE_READ_Anatenna_InfoCmd = 0x00001bb9; +HCI_LE_RandCmd = 0x00001bd9; +HCI_LE_ReadAdvChanTxPowerCmd = 0x00001c09; +HCI_LE_ReadBufSizeCmd = 0x00001c29; +HCI_LE_ReadChannelMapCmd = 0x00001c4d; +HCI_LE_ReadLocalSupportedFeaturesCmd = 0x00001c99; +HCI_LE_ReadMaxDataLengthCmd = 0x00001cb9; +HCI_LE_ReadMaximumAdvDataLengthCmd = 0x00001ce9; +HCI_LE_ReadNumberOfSupportAdvSetCmd = 0x00001d11; +HCI_LE_ReadPhyMode = 0x00001d71; +HCI_LE_ReadRemoteUsedFeaturesCmd = 0x00001db1; +HCI_LE_ReadResolvingListSizeCmd = 0x00001dc5; +HCI_LE_ReadSuggestedDefaultDataLengthCmd = 0x00001de5; +HCI_LE_ReadSupportedStatesCmd = 0x00001e15; +HCI_LE_ReadWhiteListSizeCmd = 0x00001e3d; +HCI_LE_ReceiverTestCmd = 0x00001e9d; +HCI_LE_RemoveAdvSetCmd = 0x00001eb1; +HCI_LE_RemoveResolvingListCmd = 0x00001ee9; +HCI_LE_RemoveWhiteListCmd = 0x00001f0d; +HCI_LE_SetAddressResolutionEnableCmd = 0x00001f31; +HCI_LE_SetAdvDataCmd = 0x00001f4d; +HCI_LE_SetAdvEnableCmd = 0x00001f69; +HCI_LE_SetAdvParamCmd = 0x00001f85; +HCI_LE_SetDataLengthCmd = 0x00001fb1; +HCI_LE_SetDefaultPhyMode = 0x00001fd9; +HCI_LE_SetEventMaskCmd = 0x00001ff5; +HCI_LE_SetExtAdvDataCmd = 0x0000202d; +HCI_LE_SetExtAdvEnableCmd = 0x0000204d; +HCI_LE_SetExtAdvParamCmd = 0x0000206d; +HCI_LE_SetExtAdvSetRandomAddressCmd = 0x000020c1; +HCI_LE_SetExtScanRspDataCmd = 0x000020dd; +HCI_LE_SetExtendedScanEnableCmd = 0x000020fd; +HCI_LE_SetExtendedScanParametersCmd = 0x00002119; +HCI_LE_SetHostChanClassificationCmd = 0x0000213d; +HCI_LE_SetPeriodicAdvDataCmd = 0x00002159; +HCI_LE_SetPeriodicAdvEnableCmd = 0x00002175; +HCI_LE_SetPeriodicAdvParameterCmd = 0x00002191; +HCI_LE_SetPhyMode = 0x000021ad; +HCI_LE_SetRandomAddressCmd = 0x000021c5; +HCI_LE_SetResolvablePrivateAddressTimeoutCmd = 0x000021e9; +HCI_LE_SetScanEnableCmd = 0x00002219; +HCI_LE_SetScanParamCmd = 0x00002235; +HCI_LE_SetScanRspDataCmd = 0x00002255; +HCI_LE_Set_ConnectionCTE_ReceiveParamCmd = 0x00002271; +HCI_LE_Set_ConnectionCTE_TransmitParamCmd = 0x0000229d; +HCI_LE_StartEncyptCmd = 0x000022e1; +HCI_LE_TestEndCmd = 0x000022f5; +HCI_LE_TransmitterTestCmd = 0x0000231d; +HCI_LE_WriteSuggestedDefaultDataLengthCmd = 0x00002339; +HCI_NumOfCompletedPacketsEvent = 0x00002371; +HCI_PPLUS_AdvEventDoneNoticeCmd = 0x00002401; +HCI_PPLUS_ConnEventDoneNoticeCmd = 0x00002421; +HCI_PPLUS_DateLengthChangedNoticeCmd = 0x00002461; +HCI_PPLUS_ExtendTRXCmd = 0x000024a1; +HCI_PPLUS_PhyUpdateNoticeCmd = 0x000024bd; +HCI_ProcessEvent = 0x000024fd; +HCI_ReadBDADDRCmd = 0x00002551; +HCI_ReadLocalSupportedCommandsCmd = 0x00002571; +HCI_ReadLocalSupportedFeaturesCmd = 0x00002589; +HCI_ReadLocalVersionInfoCmd = 0x000025ad; +HCI_ReadRemoteVersionInfoCmd = 0x000025f5; +HCI_ReadRssiCmd = 0x00002625; +HCI_ReadTransmitPowerLevelCmd = 0x00002651; +HCI_ResetCmd = 0x0000267d; +HCI_ReverseBytes = 0x000026a9; +HCI_SMPTaskRegister = 0x000026c9; +HCI_SendCommandCompleteEvent = 0x000026d5; +HCI_SendCommandStatusEvent = 0x0000277d; +HCI_SendControllerToHostEvent = 0x0000279d; +HCI_SendDataPkt = 0x000027e9; +HCI_SetControllerToHostFlowCtrlCmd = 0x00002819; +HCI_SetEventMaskCmd = 0x0000285d; +HCI_TestAppTaskRegister = 0x0000288d; +HCI_ValidConnTimeParams = 0x00002899; +HCI_VendorSpecifcCommandCompleteEvent = 0x000028d9; +HCI_bm_alloc = 0x000028e9; +HardFault_Handler = 0x000028f1; +HardFault_IRQHandler = 0x00002909; +LL_AddResolvingListLDevice = 0x000029dd; +LL_AddWhiteListDevice = 0x00002a95; +LL_AdvReportCback = 0x00002b11; +LL_CTE_Report_FailedCback = 0x00002ca1; +LL_ChanMapUpdate = 0x00002d0d; +LL_ClearAdvSets = 0x00002e2d; +LL_ClearResolvingList = 0x00002f41; +LL_ClearWhiteList = 0x00002fbd; +LL_ConnActive = 0x00003011; +LL_ConnParamUpdateCback = 0x00003039; +LL_ConnUpdate = 0x000030e5; +LL_ConnectionCompleteCback = 0x000031b9; +LL_ConnectionIQReportCback = 0x000032d5; +LL_Connection_CTE_Request_Enable = 0x000033e5; +LL_Connection_CTE_Response_Enable = 0x00003499; +LL_ConnectionlessCTE_TransmitEnable = 0x00003505; +LL_ConnectionlessCTE_TransmitParam = 0x000035e5; +LL_ConnectionlessIQReportCback = 0x000036c1; +LL_ConnectionlessIQ_SampleEnable = 0x000037c5; +LL_CreateConn = 0x00003901; +LL_CreateConn0 = 0x00003949; +LL_CreateConnCancel = 0x00003c91; +LL_CtrlToHostFlowControl = 0x00003d59; +LL_DataLengthChangeCback = 0x00003d71; +LL_DirectTestEnd = 0x00003e3d; +LL_DirectTestTxTest = 0x00003e95; +LL_Disconnect = 0x00003eb1; +LL_DisconnectCback = 0x00003f41; +LL_ENC_AES128_Encrypt = 0x00003fc5; +LL_ENC_AES128_Encrypt0 = 0x00003fdd; +LL_ENC_Decrypt = 0x000040ed; +LL_ENC_Decrypt0 = 0x00004105; +LL_ENC_Encrypt = 0x00004261; +LL_ENC_Encrypt0 = 0x00004278; +LL_ENC_GenDeviceIV = 0x000043c1; +LL_ENC_GenDeviceSKD = 0x000043f1; +LL_ENC_GenerateNonce = 0x00004421; +LL_ENC_GeneratePseudoRandNum = 0x00004459; +LL_ENC_GenerateTrueRandNum = 0x00004469; +LL_ENC_LoadKey = 0x00004489; +LL_ENC_ReverseBytes = 0x000044e1; +LL_ENC_sm_ah = 0x00004501; +LL_EXT_AdvEventNotice = 0x00004543; +LL_EXT_BuildRevision = 0x00004547; +LL_EXT_ClkDivOnHalt = 0x0000454b; +LL_EXT_ConnEventNotice = 0x0000454f; +LL_EXT_DeclareNvUsage = 0x00004553; +LL_EXT_Decrypt = 0x00004557; +LL_EXT_DelaySleep = 0x0000455b; +LL_EXT_DisconnectImmed = 0x0000455f; +LL_EXT_EndModemTest = 0x00004563; +LL_EXT_HaltDuringRf = 0x00004567; +LL_EXT_Init_IQ_pBuff = 0x0000456d; +LL_EXT_MapPmIoPort = 0x00004581; +LL_EXT_ModemHopTestTx = 0x00004585; +LL_EXT_ModemTestRx = 0x00004589; +LL_EXT_ModemTestTx = 0x0000458d; +LL_EXT_NumComplPktsLimit = 0x00004591; +LL_EXT_OnePacketPerEvent = 0x000045ad; +LL_EXT_OverlappedProcessing = 0x000045b1; +LL_EXT_PERbyChan = 0x000045b5; +LL_EXT_PacketErrorRate = 0x000045b9; +LL_EXT_PacketErrorRateCback = 0x000045bd; +LL_EXT_ResetSystem = 0x000045f9; +LL_EXT_SaveFreqTune = 0x000045fd; +LL_EXT_SetBDADDR = 0x00004601; +LL_EXT_SetFastTxResponseTime = 0x00004605; +LL_EXT_SetFreqTune = 0x00004609; +LL_EXT_SetLocalSupportedFeatures = 0x0000460d; +LL_EXT_SetMaxDtmTxPower = 0x00004611; +LL_EXT_SetRxGain = 0x00004615; +LL_EXT_SetRxGainCback = 0x00004619; +LL_EXT_SetSCA = 0x00004635; +LL_EXT_SetSlaveLatencyOverride = 0x00004639; +LL_EXT_SetTxPower = 0x0000463d; +LL_EXT_SetTxPowerCback = 0x00004679; +LL_EncChangeCback = 0x00004699; +LL_EncKeyRefreshCback = 0x00004715; +LL_EncLtkNegReply = 0x0000478d; +LL_EncLtkReply = 0x000047d9; +LL_EncLtkReqCback = 0x00004831; +LL_Encrypt = 0x000048e5; +LL_ExtAdvReportCback = 0x00004a8d; +LL_ExtendedCreateConnection = 0x00004bfd; +LL_IRQHandler = 0x00004e25; +LL_Init = 0x00004eb1; +LL_InitConnectContext = 0x00005045; +LL_InitExtendedAdv = 0x0000511d; +LL_InitExtendedScan = 0x000051b5; +LL_InitPeriodicAdv = 0x000051c5; +LL_NumEmptyWlEntries = 0x00005291; +LL_PLUS_DisableSlaveLatency = 0x000052a5; +LL_PLUS_EnableSlaveLatency = 0x00005435; +LL_PLUS_GetAdvDataExtendData = 0x0000548d; +LL_PLUS_GetScanRequestExtendData = 0x00005495; +LL_PLUS_GetScanerAddr = 0x000054bd; +LL_PLUS_PerStasReadByChn = 0x000054d5; +LL_PLUS_PerStatsReset = 0x00005519; +LL_PLUS_PerStats_Init = 0x00005535; +LL_PLUS_SetAdvDataFilterCB = 0x00005545; +LL_PLUS_SetScanRequestData = 0x00005551; +LL_PLUS_SetScanRequestFilterCB = 0x00005579; +LL_PLUS_SetScanRsqData = 0x00005585; +LL_PLUS_SetScanRsqDataByIndex = 0x000055b1; +LL_PeriodicAdvertisingCreateSync = 0x000055bd; +LL_PeriodicAdvertisingCreateSyncCancel = 0x0000560d; +LL_PeriodicAdvertisingTerminateSync = 0x00005635; +LL_PhyUpdate = 0x00005655; +LL_PhyUpdate0 = 0x0000566d; +LL_PhyUpdateCompleteCback = 0x00005725; +LL_PrdAdvReportCback = 0x000057c9; +LL_PrdAdvSyncEstablishedCback = 0x000058b5; +LL_PrdAdvSyncLostCback = 0x00005989; +LL_ProcessEvent = 0x000059f1; +LL_PseudoRand = 0x00005dd9; +LL_READ_Anatenna_Info = 0x00005ddd; +LL_RX_bm_alloc = 0x00005df1; +LL_Rand = 0x00005e05; +LL_RandCback = 0x00005e65; +LL_ReadAdvChanTxPower = 0x00005e89; +LL_ReadBDADDR = 0x00005eb9; +LL_ReadCarrSens = 0x00005edd; +LL_ReadChanMap = 0x00005ef9; +LL_ReadFoff = 0x00005f31; +LL_ReadLocalSupportedFeatures = 0x00005f71; +LL_ReadLocalVersionInfo = 0x00005f8d; +LL_ReadMaximumAdvDataLength = 0x00005fa5; +LL_ReadNumberOfSupportAdvSet = 0x00005fc5; +LL_ReadRemoteUsedFeatures = 0x00006021; +LL_ReadRemoteUsedFeaturesCompleteCback = 0x00006061; +LL_ReadRemoteVersionInfo = 0x000060d5; +LL_ReadRemoteVersionInfoCback = 0x00006131; +LL_ReadResolvingListSize = 0x000061a9; +LL_ReadRssi = 0x000061b1; +LL_ReadSupportedStates = 0x000061e5; +LL_ReadTxPowerLevel = 0x00006269; +LL_ReadWlSize = 0x000062e5; +LL_RemoveAdvSet = 0x00006335; +LL_RemoveResolvingListDevice = 0x000064a5; +LL_RemoveWhiteListDevice = 0x00006561; +LL_Reset = 0x000065f1; +LL_RxDataCompleteCback = 0x00006791; +LL_SetAddressResolutionEnable = 0x00006831; +LL_SetAdvControl = 0x00006881; +LL_SetAdvControl0 = 0x00006899; +LL_SetAdvData = 0x00006a05; +LL_SetAdvParam = 0x00006a6d; +LL_SetAdvParam0 = 0x00006a9d; +LL_SetDataLengh = 0x00006df9; +LL_SetDataLengh0 = 0x00006e11; +LL_SetDefaultPhyMode = 0x00006ead; +LL_SetExtAdvData = 0x00006edd; +LL_SetExtAdvEnable = 0x00006fc5; +LL_SetExtAdvParam = 0x00007205; +LL_SetExtAdvSetRandomAddress = 0x000073a9; +LL_SetExtScanRspData = 0x000073f5; +LL_SetExtendedScanEnable = 0x00007471; +LL_SetExtendedScanParameters = 0x000074b5; +LL_SetPeriodicAdvData = 0x0000751d; +LL_SetPeriodicAdvEnable = 0x000075cd; +LL_SetPeriodicAdvParameter = 0x00007715; +LL_SetPhyMode = 0x000077e1; +LL_SetPhyMode0 = 0x000077fd; +LL_SetRandomAddress = 0x000078c9; +LL_SetResolvablePrivateAddressTimeout = 0x00007929; +LL_SetScanControl = 0x00007935; +LL_SetScanControl0 = 0x0000794d; +LL_SetScanParam = 0x00007a59; +LL_SetScanParam0 = 0x00007a75; +LL_SetScanRspData = 0x00007b15; +LL_SetTxPowerLevel = 0x00007b65; +LL_Set_ConnectionCTE_ReceiveParam = 0x00007b91; +LL_Set_ConnectionCTE_TransmitParam = 0x00007c99; +LL_StartEncrypt = 0x00007e01; +LL_TX_bm_alloc = 0x00007f01; +LL_TxData = 0x00007f1d; +LL_WriteSuggestedDefaultDataLength = 0x00007fb9; +LL_evt_schedule = 0x00007ff9; +LL_extAdvTimerExpProcess = 0x000080b5; +LL_extInitTimerExpProcess = 0x000080b9; +LL_extScanTimerExpProcess = 0x000080bb; +LL_master_conn_event = 0x000080bd; +LL_prdAdvTimerExpProcess = 0x0000826d; +LL_prdScanTimerExpProcess = 0x00008271; +LL_set_default_conn_params = 0x00008275; +LL_set_default_conn_params0 = 0x0000828d; +LL_slave_conn_event = 0x000082b9; +NMI_Handler = 0x00008481; +PendSV_Handler = 0x000084cd; +TIM1_IRQHandler = 0x00008545; +WaitRTCCount = 0x00008901; +__ARM_common_switch8 = 0x00008961; +_spif_read_status_reg = 0x0000961d; +_spif_wait_nobusy = 0x00009645; +app_sleep_process = 0x00009769; +app_wakeup_process = 0x00009779; +ate_fun_test = 0x00009789; +ate_sleep_process = 0x00009d11; +ate_wakeup_process = 0x0000a121; +bit_to_byte = 0x0000a1e9; +ble_crc24_gen = 0x0000a201; +boot_init = 0x0000a361; +boot_init0 = 0x0000a379; +boot_m0 = 0x0000a3c1; +byte_to_bit = 0x0000a535; +calculate_whiten_seed = 0x0000a549; +clear_timer = 0x0000a5c1; +clear_timer_int = 0x0000a5cb; +clk_get_pclk = 0x0000a5d1; +clk_init = 0x0000a5ed; +clk_set_pclk_div = 0x0000a681; +clk_spif_ref_clk = 0x0000a6a1; +config_RTC = 0x0000a6f9; +config_RTC0 = 0x0000a711; +rom_crc16 = 0x0000a755; +debug_print = 0x0000a791; +disableSleep = 0x0000a921; +drv_disable_irq = 0x0000a975; +drv_enable_irq = 0x0000a99d; +drv_irq_init = 0x0000a9c9; +dwc_connect = 0x0000a9fd; +dwc_data_process = 0x0000aa35; +dwc_loop = 0x0000abd1; +efuse_read = 0x0000ace1; +enableSleep = 0x0000aead; +enterSleepProcess = 0x0000aeb9; +enterSleepProcess0 = 0x0000aed1; +enter_sleep_off_mode = 0x0000afa1; +enter_sleep_off_mode0 = 0x0000afb9; +getMcuPrecisionCount = 0x0000afe9; +getPN23RandNumber = 0x0000aff5; +getRxBufferFree = 0x0000b01d; +getRxBufferSize = 0x0000b031; +getSleepMode = 0x0000b051; +getTxBufferFree = 0x0000b05d; +getTxBufferSize = 0x0000b071; +get_rx_read_ptr = 0x0000b0b1; +get_rx_write_ptr = 0x0000b0b9; +get_sleep_flag = 0x0000b0c1; +get_timer_count = 0x0000b0cd; +get_timer_int = 0x0000b0d1; +get_tx_read_ptr = 0x0000b0d9; +get_tx_write_ptr = 0x0000b0e1; +gpio_cfg_analog_io = 0x0000b0e9; +gpio_dir = 0x0000b119; +gpio_fmux_control = 0x0000b15d; +gpio_fmux_set = 0x0000b179; +gpio_in_trigger = 0x0000b1b1; +gpio_init = 0x0000b219; +gpio_interrupt_set = 0x0000b22d; +gpio_pull_set = 0x0000b249; +gpio_read = 0x0000b291; +gpio_wakeup_set = 0x0000b2b5; +gpio_write = 0x0000b319; +hciInitEventMasks = 0x0000b52d; +isSleepAllow = 0x0000b555; +isTimer1Running = 0x0000b561; +isTimer4Running = 0x0000b571; +jump_area_init = 0x0000b581; +ll24BitTimeCompare = 0x0000b5a9; +llAdjSlaveLatencyValue = 0x0000b609; +llAllocConnId = 0x0000b629; +llAllocateSyncHandle = 0x0000b679; +llAtLeastTwoChans = 0x0000b6a9; +llCalcMaxScanTime = 0x0000b6ed; +llCalcScaFactor = 0x0000b745; +llCalcTimerDrift = 0x0000b76d; +llCheckForLstoDuringSL = 0x0000b7b1; +llCheckWhiteListUsage = 0x0000b7ed; +llConnCleanup = 0x0000b809; +llConnTerminate = 0x0000b839; +llConnTerminate0 = 0x0000b851; +llConvertCtrlProcTimeoutToEvent = 0x0000b87d; +llConvertLstoToEvent = 0x0000b899; +llDeleteSyncHandle = 0x0000b8bd; +llDequeueCtrlPkt = 0x0000b8ed; +llDequeueDataQ = 0x0000b929; +llEnqueueCtrlPkt = 0x0000b953; +llEnqueueDataQ = 0x0000b98b; +llEqAlreadyValidAddr = 0x0000b9b1; +llEqSynchWord = 0x0000b9b5; +llEqualBytes = 0x0000b9c9; +llEventDelta = 0x0000b9e9; +llEventInRange = 0x0000b9fd; +llGenerateCRC = 0x0000ba1b; +llGenerateValidAccessAddr = 0x0000ba3d; +llGetNextAdvChn = 0x0000ba6d; +llGetNextAuxAdvChn = 0x0000bac1; +llGetNextDataChan = 0x0000bae5; +llGetNextDataChanCSA2 = 0x0000bb23; +llGtSixConsecZerosOrOnes = 0x0000bb81; +llGtTwentyFourTransitions = 0x0000bbb3; +llInitFeatureSet = 0x0000bbe5; +llInitFeatureSet2MPHY = 0x0000bc1d; +llInitFeatureSetCodedPHY = 0x0000bc45; +llInitFeatureSetDLE = 0x0000bc6d; +llLtTwoChangesInLastSixBits = 0x0000bc89; +llMasterEvt_TaskEndOk = 0x0000bcb9; +llMemCopyDst = 0x0000be05; +llMemCopySrc = 0x0000be1b; +llOneBitSynchWordDiffer = 0x0000be35; +llPduLengthManagmentReset = 0x0000be4d; +llPduLengthUpdate = 0x0000bf01; +llPendingUpdateParam = 0x0000c00d; +llPhyModeCtrlReset = 0x0000c051; +llPhyModeCtrlUpdateNotify = 0x0000c0b9; +llProcessChanMap = 0x0000c185; +llProcessMasterControlPacket = 0x0000c1d1; +llProcessMasterControlProcedures = 0x0000c5b9; +llProcessRxData = 0x0000ca85; +llProcessSlaveControlPacket = 0x0000cc31; +llProcessSlaveControlProcedures = 0x0000d169; +llProcessTxData = 0x0000d4d1; +llProcessTxData0 = 0x0000d4e9; +llReleaseAllConnId = 0x0000d55d; +llReleaseConnId = 0x0000d561; +llReplaceCtrlPkt = 0x0000d5f5; +llResetConnId = 0x0000d60d; +llResetRfCounters = 0x0000d6ed; +llSecAdvAllow = 0x0000d701; +llSetNextDataChan = 0x0000d769; +llSetNextPhyMode = 0x0000d839; +llSetupAdv = 0x0000d8a9; +llSetupAdvExtIndPDU = 0x0000d949; +llSetupAuxAdvIndPDU = 0x0000db4d; +llSetupAuxChainIndPDU = 0x0000dda1; +llSetupAuxConnectReqPDU = 0x0000df91; +llSetupAuxConnectRspPDU = 0x0000e025; +llSetupAuxScanRspPDU = 0x0000e09d; +llSetupAuxSyncIndPDU = 0x0000e109; +llSetupCTEReq = 0x0000e2c1; +llSetupCTERsp = 0x0000e38d; +llSetupConn = 0x0000e457; +llSetupDataLenghtReq = 0x0000e459; +llSetupDataLenghtRsp = 0x0000e4d5; +llSetupDirectedAdvEvt = 0x0000e551; +llSetupEncReq = 0x0000e6a1; +llSetupEncRsp = 0x0000e725; +llSetupExtAdvEvent = 0x0000e7b1; +llSetupExtInit = 0x0000eb09; +llSetupExtScan = 0x0000eb81; +llSetupFeatureSetReq = 0x0000ec01; +llSetupFeatureSetRsp = 0x0000ec63; +llSetupInit = 0x0000ecc1; +llSetupNextMasterEvent = 0x0000ed39; +llSetupNextSlaveEvent = 0x0000ede1; +llSetupNextSlaveEvent0 = 0x0000edf9; +llSetupNonConnectableAdvEvt = 0x0000ef65; +llSetupPauseEncReq = 0x0000f075; +llSetupPauseEncRsp = 0x0000f0c5; +llSetupPhyReq = 0x0000f121; +llSetupPhyRsp = 0x0000f177; +llSetupPhyUpdateInd = 0x0000f1cd; +llSetupPrdAdvEvent = 0x0000f239; +llSetupPrdScan = 0x0000f3b9; +llSetupRejectExtInd = 0x0000f44d; +llSetupRejectInd = 0x0000f479; +llSetupScan = 0x0000f4a5; +llSetupScanInit = 0x0000f54d; +llSetupScannableAdvEvt = 0x0000f55d; +llSetupSecAdvEvt = 0x0000f66d; +llSetupSecConnectableAdvEvt = 0x0000f6e9; +llSetupSecInit = 0x0000f7c1; +llSetupSecNonConnectableAdvEvt = 0x0000f875; +llSetupSecScan = 0x0000f94d; +llSetupSecScannableAdvEvt = 0x0000fa19; +llSetupStartEncReq = 0x0000faf1; +llSetupStartEncRsp = 0x0000fb15; +llSetupSyncInfo = 0x0000fb59; +llSetupTermInd = 0x0000fc2d; +llSetupUndirectedAdvEvt = 0x0000fc91; +llSetupUnknownRsp = 0x0000fda5; +llSetupUpdateChanReq = 0x0000fdf9; +llSetupUpdateParamReq = 0x0000fe6d; +llSetupVersionIndReq = 0x0000ff05; +llSlaveEvt_TaskAbort = 0x0000ff79; +llSlaveEvt_TaskEndOk = 0x0000ff95; +llTrxNumAdaptiveConfig = 0x00010181; +llValidAccessAddr = 0x0001019b; +llWaitUs = 0x000101e1; +llWriteTxData = 0x00010209; +ll_CalcRandomAddr = 0x0001028f; +ll_ResolveRandomAddrs = 0x000102cd; +ll_addTask = 0x00010315; +ll_add_adv_task = 0x00010445; +ll_add_adv_task_periodic = 0x00010461; +ll_adptive_adj_next_time = 0x0001047d; +ll_adptive_smart_window = 0x000104fd; +ll_adv_scheduler = 0x000105ad; +ll_adv_scheduler_periodic = 0x000105c9; +ll_allocAuxAdvTimeSlot = 0x000105e5; +ll_allocAuxAdvTimeSlot_prd = 0x00010679; +_ll_debug_output = 0x00010719; +ll_deleteTask = 0x00010731; +ll_delete_adv_task = 0x00010765; +ll_delete_adv_task_periodic = 0x00010781; +ll_ext_adv_schedule_next_event = 0x0001079d; +ll_ext_init_schedule_next_event = 0x000107c1; +ll_ext_scan_schedule_next_event = 0x000107dd; +ll_generateExtAdvDid = 0x000107f9; +ll_generateTxBuffer = 0x00010801; +ll_getFirstAdvChn = 0x000109c1; +ll_getRPAListEntry = 0x000109cd; +ll_get_next_active_conn = 0x00010a39; +ll_get_next_timer = 0x00010aa1; +ll_hw_clr_irq = 0x00010add; +ll_hw_config = 0x00010aed; +ll_hw_get_anchor = 0x00010b6d; +ll_hw_get_fsm_status = 0x00010b79; +ll_hw_get_iq_RawSample = 0x00010b89; +ll_hw_get_irq_status = 0x00010bbd; +ll_hw_get_last_ack = 0x00010bcd; +ll_hw_get_loop_cycle = 0x00010be9; +ll_hw_get_loop_time = 0x00010bf5; +ll_hw_get_nAck = 0x00010c01; +ll_hw_get_rfifo_depth = 0x00010c11; +ll_hw_get_rfifo_info = 0x00010c25; +ll_hw_get_rxPkt_CrcErr_num = 0x00010c45; +ll_hw_get_rxPkt_CrcOk_num = 0x00010c55; +ll_hw_get_rxPkt_Total_num = 0x00010c69; +ll_hw_get_rxPkt_num = 0x00010c79; +ll_hw_get_rxPkt_stats = 0x00010c85; +ll_hw_get_snNesn = 0x00010c9d; +ll_hw_get_tfifo_info = 0x00010cad; +ll_hw_get_tfifo_wrptr = 0x00010ccd; +ll_hw_get_tr_mode = 0x00010cdd; +ll_hw_get_txAck = 0x00010ced; +ll_hw_go = 0x00010cf9; +ll_hw_ign_rfifo = 0x00010df9; +ll_hw_process_RTO = 0x00010e05; +ll_hw_read_rfifo = 0x00010e6d; +ll_hw_read_rfifo_pplus = 0x00010ee9; +ll_hw_read_rfifo_zb = 0x00010f51; +ll_hw_read_tfifo_packet = 0x00010fad; +ll_hw_read_tfifo_rtlp = 0x00010ff5; +ll_hw_rst_rfifo = 0x000110b1; +ll_hw_rst_tfifo = 0x000110e9; +ll_hw_set_ant_pattern = 0x000110f5; +ll_hw_set_ant_switch_mode = 0x00011101; +ll_hw_set_ant_switch_timing = 0x00011115; +ll_hw_set_crc_fmt = 0x0001112d; +ll_hw_set_cte_rxSupp = 0x0001113d; +ll_hw_set_cte_txSupp = 0x00011155; +ll_hw_set_empty_head = 0x00011169; +ll_hw_set_irq = 0x00011175; +ll_hw_set_loop_nack_num = 0x00011181; +ll_hw_set_loop_timeout = 0x0001118d; +ll_hw_set_pplus_pktfmt = 0x000111a1; +ll_hw_set_rtlp = 0x000111cd; +ll_hw_set_rtlp_1st = 0x0001121d; +ll_hw_set_rtx = 0x00011265; +ll_hw_set_rx_timeout = 0x00011279; +ll_hw_set_rx_timeout_1st = 0x00011285; +ll_hw_set_rx_tx_interval = 0x00011291; +ll_hw_set_srx = 0x000112a5; +ll_hw_set_stx = 0x000112b9; +ll_hw_set_tfifo_space = 0x000112cd; +ll_hw_set_timing = 0x000112e5; +ll_hw_set_trlp = 0x00011381; +ll_hw_set_trx = 0x000113c9; +ll_hw_set_trx_settle = 0x000113dd; +ll_hw_set_tx_rx_interval = 0x000113f1; +ll_hw_set_tx_rx_release = 0x00011405; +ll_hw_trigger = 0x00011421; +ll_hw_trx_settle_config = 0x00011445; +ll_hw_tx2rx_timing_config = 0x00011489; +ll_hw_update = 0x000114dd; +ll_hw_update_rtlp_mode = 0x00011539; +ll_hw_update_trlp_mode = 0x00011579; +ll_hw_write_tfifo = 0x000115c1; +ll_isAddrInWhiteList = 0x00011649; +ll_isFirstAdvChn = 0x000116a9; +ll_isIrkAllZero = 0x000116c7; +ll_isLegacyAdv = 0x000116dd; +ll_parseExtHeader = 0x000116ed; +ll_prd_adv_schedule_next_event = 0x000117a9; +ll_prd_scan_schedule_next_event = 0x000117cd; +ll_processBasicIRQ = 0x000117e9; +ll_processExtAdvIRQ = 0x00013401; +ll_processExtInitIRQ = 0x00013405; +ll_processExtScanIRQ = 0x00013409; +ll_processMissMasterEvt = 0x0001340d; +ll_processMissSlaveEvt = 0x000134ed; +ll_processPrdAdvIRQ = 0x000135f5; +ll_processPrdScanIRQ = 0x000135f9; +ll_readLocalIRK = 0x000135fd; +ll_read_rxfifo = 0x000136c5; +ll_schedule_next_event = 0x00013761; +ll_scheduler = 0x00013771; +ll_scheduler0 = 0x00013789; +ll_updateAuxAdvTimeSlot = 0x00013a11; +ll_updateExtAdvRemainderTime = 0x00013a39; +log_clr_putc = 0x00013ab9; +log_debug_level = 0x00013ac5; +log_get_debug_level = 0x00013ad9; +log_printf = 0x00013ae5; +log_set_putc = 0x00013b05; +log_vsprintf = 0x00013b11; +move_to_master_function = 0x00013f09; +move_to_slave_function = 0x0001406d; +osalAddTimer = 0x00014439; +osalDeleteTimer = 0x000144a9; +osalFindTimer = 0x000144b5; +osalTimeUpdate = 0x000144d5; +osalTimeUpdate1 = 0x00014541; +osalTimerInit = 0x0001457d; +osalTimerUpdate = 0x00014589; +osal_CbTimerInit = 0x00014621; +osal_CbTimerProcessEvent = 0x00014641; +osal_CbTimerStart = 0x000146a9; +osal_CbTimerStop = 0x00014711; +osal_CbTimerUpdate = 0x00014751; +osal_ConvertUTCSecs = 0x000147a1; +osal_ConvertUTCTime = 0x00014841; +osal_GetSystemClock = 0x00014949; +osal_bm_adjust_header = 0x00014955; +osal_bm_adjust_tail = 0x0001497d; +osal_bm_alloc = 0x000149a9; +osal_bm_free = 0x000149d9; +osal_buffer_uint24 = 0x00014a21; +osal_buffer_uint32 = 0x00014a2f; +osal_build_uint16 = 0x00014a41; +osal_build_uint32 = 0x00014a4d; +osal_clear_event = 0x00014a89; +osal_getClock = 0x00014abd; +osal_get_timeoutEx = 0x00014ac9; +osal_init_system = 0x00014aed; +osal_isbufset = 0x00014b1d; +osal_mem_alloc = 0x00014b3d; +osal_mem_free = 0x00014c01; +osal_mem_init = 0x00014c25; +osal_mem_kick = 0x00014c8d; +osal_mem_set_heap = 0x00014cb5; +osal_memcmp = 0x00014ccd; +osal_memcpy = 0x00014ce9; +osal_memdup = 0x00014cf9; +osal_memset = 0x00014d15; +osal_msg_allocate = 0x00014d1d; +osal_msg_deallocate = 0x00014d43; +osal_msg_dequeue = 0x00014d65; +osal_msg_enqueue = 0x00014d91; +osal_msg_enqueue_max = 0x00014dc3; +osal_msg_extract = 0x00014e6d; +osal_msg_find = 0x00014e9d; +osal_msg_push = 0x00014ed1; +osal_msg_push_front = 0x00014eeb; +osal_msg_receive = 0x00014ef5; +osal_msg_send = 0x00014f59; +osal_next_timeout = 0x00014f7d; +osal_pwrmgr_device = 0x00014fa5; +osal_pwrmgr_init = 0x00014fb1; +osal_pwrmgr_powerconserve = 0x00014fc1; +osal_pwrmgr_powerconserve0 = 0x00014fd9; +osal_pwrmgr_task_state = 0x000150f9; +osal_rand = 0x00015129; +osal_revmemcpy = 0x00015145; +osal_run_system = 0x00015159; +osal_self = 0x000151f5; +osal_setClock = 0x00015201; +osal_set_event = 0x0001520d; +osal_start_reload_timer = 0x00015259; +osal_start_system = 0x00015285; +osal_start_timerEx = 0x0001528b; +osal_stop_timerEx = 0x000152b3; +osal_strlen = 0x000152dd; +osal_timer_num_active = 0x000152e5; +phy_sec_app_key = 0x00015315; +phy_sec_decrypt = 0x0001531d; +phy_sec_efuse_lock = 0x0001532d; +phy_sec_encrypt = 0x00015339; +phy_sec_init = 0x00015349; +phy_sec_key_valid = 0x0001540d; +prog_process_data = 0x00015b19; +prog_uart_command = 0x00015c51; +prog_uart_fct_command = 0x00015c71; +prog_uart_handle = 0x00015c8d; +read_LL_remainder_time = 0x00015cbd; +read_current_fine_time = 0x00015cc9; +read_ll_adv_remainder_time = 0x00015cf1; +reset_conn_buf = 0x00015cfd; +rf_calibrate = 0x00015d75; +rf_init = 0x00015ded; +rf_phy_ana_cfg = 0x00015dfd; +rf_phy_bb_cfg = 0x00015f0d; +rf_phy_change_cfg = 0x00016085; +rf_phy_direct_test_ate = 0x00016129; +rf_phy_get_pktFoot = 0x00016669; +rf_phy_ini = 0x000166c1; +rf_phy_set_txPower = 0x000166dd; +rf_rxDcoc_cfg = 0x00016701; +rf_tpCal_cfg = 0x00016811; +rf_tpCal_cfg_avg = 0x0001683d; +rf_tpCal_gen_cap_arrary = 0x000168ed; +rf_tp_cal = 0x00016929; +rom_board_init = 0x00016a09; +rtc_clear = 0x00016ab5; +rtc_config_prescale = 0x00016ad1; +rtc_get_counter = 0x00016b15; +rtc_start = 0x00016b25; +rtc_stop = 0x00016b35; +setSleepMode = 0x00016b45; +set_access_address = 0x00016b51; +set_channel = 0x00016b5d; +set_crc_seed = 0x00016b9d; +set_gpio_pull_down_ate = 0x00016bb5; +set_gpio_pull_up_ate = 0x00016bcb; +set_int = 0x00016be1; +set_max_length = 0x00016bed; +set_sleep_flag = 0x00016c01; +set_timer = 0x00016c2d; +set_whiten_seed = 0x00016cc9; +spif_cmd = 0x00016d49; +spif_config = 0x00016dc5; +spif_erase_all = 0x00016ea1; +spif_erase_block64 = 0x00016ed1; +spif_erase_chip = 0x00016f55; +spif_erase_sector = 0x00016fa9; +spif_flash_size = 0x00017029; +spif_flash_status_reg_0 = 0x0001703d; +spif_flash_status_reg_1 = 0x00017047; +spif_init = 0x00017051; +spif_rddata = 0x0001713d; +spif_read = 0x00017165; +spif_read_dma = 0x0001717d; +spif_release_deep_sleep = 0x000172cd; +spif_set_deep_sleep = 0x00017349; +spif_wrdata = 0x0001736d; +spif_write = 0x00017395; +spif_write_dma = 0x0001744d; +spif_write_protect = 0x000174f9; +sram_ret_patch = 0x00017591; +update_rx_read_ptr = 0x00017609; +update_rx_write_ptr = 0x00017635; +update_tx_read_ptr = 0x00017659; +update_tx_write_ptr = 0x00017685; +wakeupProcess = 0x000176a9; +wakeupProcess0 = 0x000176c5; +wakeup_init = 0x000178a5; +wakeup_init0 = 0x000178bd; +zigbee_crc16_gen = 0x0001798d; +supportedCmdsTable = 0x00017c00; +hciCmdTable = 0x00017c44; +SCA = 0x00017c4c; +hclk_per_us = 0x1fff0818; +hclk_per_us_shift = 0x1fff081c; +s_prog_time_save = 0x1fff0828; +s_prog_timeout = 0x1fff082c; +DFL_ENTRY_BASE = 0x1fff0830; +receive_timeout_flag = 0x1fff0850; +osal_sys_tick = 0x1fff0860; +g_timer4_irq_pending_time = 0x1fff0864; +g_hclk = 0x1fff0874; +m_in_critical_region = 0x1fff0878; +s_rom_debug_level = 0x1fff0888; +s_spif_ctx = 0x1fff0894; +osal_qHead = 0x1fff08b8; +baseTaskID = 0x1fff08c0; +OSAL_timeSeconds = 0x1fff08cc; +ll_remain_time = 0x1fff08e4; +pwrmgr_attribute = 0x1fff08e8; +timerHead = 0x1fff08f0; +hciPTMenabled = 0x1fff08f8; +ctrlToHostEnable = 0x1fff08f9; +numHostBufs = 0x1fff08fa; +hciCtrlCmdToken = 0x1fff08fc; +bleEvtMask = 0x1fff0900; +pHciEvtMask = 0x1fff0904; +hciTaskID = 0x1fff090c; +hciTestTaskID = 0x1fff090d; +hciGapTaskID = 0x1fff090e; +hciL2capTaskID = 0x1fff090f; +hciSmpTaskID = 0x1fff0910; +hciExtTaskID = 0x1fff0911; +g_maxConnNum = 0x1fff0914; +g_maxPktPerEventTx = 0x1fff0915; +g_maxPktPerEventRx = 0x1fff0916; +g_blePktVersion = 0x1fff0917; +g_llRlEnable = 0x1fff0918; +g_llScanMode = 0x1fff0919; +g_llAdvMode = 0x1fff091a; +LL_TaskID = 0x1fff091b; +llState = 0x1fff091c; +numComplPkts = 0x1fff091d; +numComplPktsLimit = 0x1fff091e; +fastTxRespTime = 0x1fff091f; +g_llWlDeviceNum = 0x1fff0920; +g_llRlDeviceNum = 0x1fff0921; +rxFifoFlowCtrl = 0x1fff0922; +llSecondaryState = 0x1fff0923; +g_extAdvNumber = 0x1fff0924; +g_perioAdvNumber = 0x1fff0925; +g_schExtAdvNum = 0x1fff0926; +g_currentExtAdv = 0x1fff0927; +g_schExtAdvNum_periodic = 0x1fff0928; +g_currentExtAdv_periodic = 0x1fff0929; +g_llRlTimeout = 0x1fff092c; +g_advSetMaximumLen = 0x1fff0930; +conn_param = 0x1fff0934; +g_pExtendedAdvInfo = 0x1fff0938; +g_pPeriodicAdvInfo = 0x1fff093c; +g_pLLcteISample = 0x1fff0940; +g_pLLcteQSample = 0x1fff0944; +g_llHdcDirAdvTime = 0x1fff0948; +g_pAdvSchInfo = 0x1fff094c; +g_advPerSlotTick = 0x1fff0950; +g_advSlotPeriodic = 0x1fff0954; +g_pAdvSchInfo_periodic = 0x1fff0958; +g_timerExpiryTick = 0x1fff095c; +chanMapUpdate = 0x1fff0960; +ownPublicAddr = 0x1fff0965; +ownRandomAddr = 0x1fff096b; +verInfo = 0x1fff0972; +peerInfo = 0x1fff0978; +g_currentAdvTimer = 0x1fff0980; +g_currentTimerTask = 0x1fff0984; +g_adv_taskID = 0x1fff0988; +g_conn_taskID = 0x1fff0989; +g_smartWindowRTOCnt = 0x1fff098a; +isPeerRpaStore = 0x1fff098b; +g_same_rf_channel_flag = 0x1fff098c; +g_currentPeerAddrType = 0x1fff098d; +g_currentLocalAddrType = 0x1fff098e; +storeRpaListIndex = 0x1fff098f; +llTaskState = 0x1fff0990; +g_adv_taskEvent = 0x1fff0992; +g_conn_taskEvent = 0x1fff0994; +llWaitingIrq = 0x1fff0998; +ISR_entry_time = 0x1fff099c; +slave_conn_event_recv_delay = 0x1fff09a0; +g_smartWindowLater = 0x1fff09a4; +g_smartWindowActiveCnt = 0x1fff09a8; +g_smartWindowPreAnchPoint = 0x1fff09ac; +g_getPn23_cnt = 0x1fff09b0; +g_getPn23_seed = 0x1fff09b4; +llScanTime = 0x1fff09b8; +p_perStatsByChan = 0x1fff09bc; +LL_PLUS_AdvDataFilterCBack = 0x1fff09c0; +LL_PLUS_ScanRequestFilterCBack = 0x1fff09c4; +g_new_master_delta = 0x1fff09c8; +llScanT1 = 0x1fff09cc; +llCurrentScanChn = 0x1fff09d0; +g_currentLocalRpa = 0x1fff09d4; +g_currentPeerRpa = 0x1fff09da; +currentPeerRpa = 0x1fff09e0; +g_dle_taskID = 0x1fff09e6; +g_dle_taskEvent = 0x1fff09e8; +g_phyChg_taskID = 0x1fff09ea; +g_phyChg_taskEvent = 0x1fff09ec; +g_smartWindowSize = 0x1fff09f0; +g_smartWindowSizeNew = 0x1fff09f4; +g_smartWindowActive = 0x1fff09f8; +g_interAuxPduDuration = 0x1fff09fc; +connUpdateTimer = 0x1fff0a04; +sleep_flag = 0x1fff0a0c; +g_wakeup_rtc_tick = 0x1fff0a10; +g_counter_traking_avg = 0x1fff0a14; +g_TIM2_IRQ_TIM3_CurrCount = 0x1fff0a18; +g_TIM2_IRQ_to_Sleep_DeltTick = 0x1fff0a1c; +g_TIM2_IRQ_PendingTick = 0x1fff0a20; +g_osal_tick_trim = 0x1fff0a24; +g_osalTickTrim_mod = 0x1fff0a28; +rtc_mod_value = 0x1fff0a2c; +g_counter_traking_cnt = 0x1fff0a30; +sleep_tick = 0x1fff0a34; +counter_tracking = 0x1fff0a38; +forever_write = 0x1fff0a3c; +g_TIM2_wakeup_delay = 0x1fff0a40; +g_rfPhyTpCal0 = 0x1fff0a44; +g_rfPhyTpCal1 = 0x1fff0a45; +g_rfPhyTpCal0_2Mbps = 0x1fff0a46; +g_rfPhyTpCal1_2Mbps = 0x1fff0a47; +g_rfPhyTxPower = 0x1fff0a48; +g_rfPhyPktFmt = 0x1fff0a49; +g_system_clk = 0x1fff0a4a; +g_rfPhyClkSel = 0x1fff0a4b; +g_rxAdcClkSel = 0x1fff0a4c; +g_dtmModeType = 0x1fff0a4d; +g_dtmLength = 0x1fff0a4e; +g_dtmExtLen = 0x1fff0a4f; +g_dtmPKT = 0x1fff0a50; +g_dtmTxPower = 0x1fff0a51; +g_dtmRssi = 0x1fff0a52; +g_dtmCarrSens = 0x1fff0a53; +g_dtmPktIntv = 0x1fff0a54; +g_dtmPktCount = 0x1fff0a56; +g_dtmRxCrcNum = 0x1fff0a58; +g_dtmRxTONum = 0x1fff0a5a; +g_dtmRsp = 0x1fff0a5c; +g_dtmFoff = 0x1fff0a5e; +g_rfPhyRxDcIQ = 0x1fff0a60; +g_dtmTick = 0x1fff0a64; +g_rfPhyFreqOffSet = 0x1fff0a68; +g_rfPhyDtmCmd = 0x1fff0a69; +g_rfPhyDtmEvt = 0x1fff0a6b; +g_dtmCmd = 0x1fff0a6d; +g_dtmFreq = 0x1fff0a6e; +g_dtmCtrl = 0x1fff0a6f; +g_dtmPara = 0x1fff0a70; +g_dtmEvt = 0x1fff0a71; +g_dtmStatus = 0x1fff0a72; +g_dtmTpCalEnable = 0x1fff0a73; +g_dtmPerAutoIntv = 0x1fff0a74; +g_dtmAccessCode = 0x1fff0a78; +g_system_reset_cause = 0x1fff0a80; +cbTimers = 0x1fff0afc; +g_llSleepContext = 0x1fff0b74; +syncInfo = 0x1fff0b84; +scanSyncInfo = 0x1fff0b96; +adv_param = 0x1fff0ba6; +scanInfo = 0x1fff0bbc; +initInfo = 0x1fff0bd4; +extScanInfo = 0x1fff0be8; +extInitInfo = 0x1fff0c10; +g_llPeriodAdvSyncInfo = 0x1fff0c50; +g_ll_conn_ctx = 0x1fff0d30; +deviceFeatureSet = 0x1fff0e48; +g_llWhitelist = 0x1fff0e51; +g_llResolvinglist = 0x1fff0e89; +g_pmCounters = 0x1fff0ffc; +g_llPduLen = 0x1fff1084; +rfCounters = 0x1fff10e0; +ext_adv_hdr = 0x1fff10ec; +dataPkt = 0x1fff1118; +cachedTRNGdata = 0x1fff1138; +whiten_seed = 0x1fff1144; +g_tx_adv_buf = 0x1fff116c; +g_tx_ext_adv_buf = 0x1fff1278; +tx_scanRsp_desc = 0x1fff1384; +g_rx_adv_buf = 0x1fff1490; diff --git a/ota_boot/source/misc/ota_upboot.ld b/ota_boot/source/misc/ota_upboot.ld new file mode 100644 index 0000000..2d3a0ee --- /dev/null +++ b/ota_boot/source/misc/ota_upboot.ld @@ -0,0 +1,133 @@ +/* SRAM + XIP linker script */ +/* https://docs.oracle.com/cd/E19120-01/open.solaris/819-0690/6n33n7fds/index.html */ +PHDRS +{ + romdata PT_LOAD FLAGS(6); + text PT_LOAD FLAGS(5); + data PT_LOAD FLAGS(6); + xip PT_LOAD FLAGS(5); + rodata PT_LOAD FLAGS(4); +} + +MEMORY +{ + jumptbl (rw) : ORIGIN = 0x1fff0000, LENGTH = 0x00400 + gcfgtbl (rw) : ORIGIN = 0x1fff0400, LENGTH = 0x00400 + sram (rwx) : ORIGIN = 0x1fff1838, LENGTH = 0x0E7C8 + flash (rx) : ORIGIN = 0x11010100, LENGTH = 0x1ff00 + sram2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x10000 + sram3 (rwx) : ORIGIN = 0x20010000, LENGTH = 0x02000 + sram4 (rwx) : ORIGIN = 0x20012000, LENGTH = 0x00800 +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(__start) + +SECTIONS +{ + .jumptbl : { + *(jump_table_mem_area) + } > jumptbl : romdata + + .gcfgtbl (NOLOAD) : { + *(global_config_area) + } > gcfgtbl + + .textentry : { + *(*.isr_vector) + } > sram : text + + _sdata = ABSOLUTE(.); + .text : { + _stextram = ABSOLUTE(.); + + *phy6222_start.o(.text) + *phy6222_cstart.o(.text) + *main.o(.text.*) + *.o(_section_standby_code_) + *.o(_section_sram_code_) + + _etextram = ABSOLUTE(.); + } > sram : text + + .data : { + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + } > sram : data + . = ALIGN(4); + _edata = ABSOLUTE(.); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + .irq_stack : { + *(g_irqstack_base) + } > sram + + g_stack = ORIGIN(sram) + LENGTH(sram); + + .xip : { + _stext = ABSOLUTE(.); + *.o(_func_xip_code_) + *.o(_section_xip_code_) + *(.text .text.*) + + _etext = ABSOLUTE(.); + } > flash : xip + + .rodata : { + *(.rodata .rodata.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + } > flash : rodata + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash : rodata + + .ARM.extab : { + *(.ARM.extab*) + } > flash : rodata + + .ARM.exidx : { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash : rodata + + ._sjtblsstore : { + _sjtblss = ABSOLUTE(.); + } > flash : rodata + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } + +} diff --git a/ota_boot/source/misc/rom_sym_def.h b/ota_boot/source/misc/rom_sym_def.h new file mode 100644 index 0000000..30d419e --- /dev/null +++ b/ota_boot/source/misc/rom_sym_def.h @@ -0,0 +1,903 @@ +/************* + rom_sym_def.h + SDK_LICENSE +***************/ +#ifndef __ROM_SYM_H__ +#define __ROM_SYM_H__ +#ifdef USE_ROMSYM_ALIAS + + #define m_in_critical_region _symrom_m_in_critical_region + #define _spif_read_status_reg _symrom__spif_read_status_reg + #define _spif_wait_nobusy _symrom__spif_wait_nobusy + #define adv_param _symrom_adv_param + #define app_sleep_process _symrom_app_sleep_process + #define app_wakeup_process _symrom_app_wakeup_process + #define ate_fun_test _symrom_ate_fun_test + #define ate_sleep_process _symrom_ate_sleep_process + #define ate_wakeup_process _symrom_ate_wakeup_process + #define baseTaskID _symrom_baseTaskID + #define bit_to_byte _symrom_bit_to_byte + #define ble_crc24_gen _symrom_ble_crc24_gen + #define bleEvtMask _symrom_bleEvtMask + #define boot_init _symrom_boot_init + #define boot_init0 _symrom_boot_init0 + #define boot_m0 _symrom_boot_m0 + #define bx_to_application _symrom_bx_to_application + #define byte_to_bit _symrom_byte_to_bit + #define cachedTRNGdata _symrom_cachedTRNGdata + #define calculate_whiten_seed _symrom_calculate_whiten_seed + #define cbTimers _symrom_cbTimers + #define chanMapUpdate _symrom_chanMapUpdate + #define clear_timer _symrom_clear_timer + #define clear_timer_int _symrom_clear_timer_int + #define clk_get_pclk _symrom_clk_get_pclk + #define clk_init _symrom_clk_init + #define clk_set_pclk_div _symrom_clk_set_pclk_div + #define clk_spif_ref_clk _symrom_clk_spif_ref_clk + #define config_RTC _symrom_config_RTC + #define conn_param _symrom_conn_param + #define connUpdateTimer _symrom_connUpdateTimer + #define counter_tracking _symrom_counter_tracking + #define rom_crc16 _symrom_crc16 + #define ctrlToHostEnable _symrom_ctrlToHostEnable + #define dataPkt _symrom_dataPkt + #define debug_print _symrom_debug_print + #define deviceFeatureSet _symrom_deviceFeatureSet + #define disableSleep _symrom_disableSleep + #define drv_disable_irq _symrom_drv_disable_irq + #define drv_enable_irq _symrom_drv_enable_irq + #define drv_irq_init _symrom_drv_irq_init + #define dwc_connect _symrom_dwc_connect + #define dwc_data_process _symrom_dwc_data_process + #define dwc_loop _symrom_dwc_loop + #define efuse_read _symrom_efuse_read + #define enableSleep _symrom_enableSleep + #define enter_sleep_off_mode _symrom_enter_sleep_off_mode + #define enterSleepProcess _symrom_enterSleepProcess + #define ext_adv_hdr _symrom_ext_adv_hdr + #define extInitInfo _symrom_extInitInfo + #define extScanInfo _symrom_extScanInfo + #define fastTxRespTime _symrom_fastTxRespTime + #define forever_write _symrom_forever_write + #define g_adv_taskEvent _symrom_g_adv_taskEvent + #define g_adv_taskID _symrom_g_adv_taskID + #define g_advPerSlotTick _symrom_g_advPerSlotTick + #define g_advSetMaximumLen _symrom_g_advSetMaximumLen + #define g_advSlotPeriodic _symrom_g_advSlotPeriodic + #define g_blePktVersion _symrom_g_blePktVersion + #define g_conn_taskEvent _symrom_g_conn_taskEvent + #define g_conn_taskID _symrom_g_conn_taskID + #define g_counter_traking_avg _symrom_g_counter_traking_avg + #define g_counter_traking_cnt _symrom_g_counter_traking_cnt + #define g_currentAdvTimer _symrom_g_currentAdvTimer + #define g_currentExtAdv _symrom_g_currentExtAdv + #define g_currentExtAdv_periodic _symrom_g_currentExtAdv_periodic + #define g_currentTimerTask _symrom_g_currentTimerTask + #define g_dle_taskEvent _symrom_g_dle_taskEvent + #define g_dle_taskID _symrom_g_dle_taskID + //#define g_dtmAccessCode _symrom_g_dtmAccessCode + //#define g_dtmCarrSens _symrom_g_dtmCarrSens + //#define g_dtmCmd _symrom_g_dtmCmd + //#define g_dtmCtrl _symrom_g_dtmCtrl + //#define g_dtmEvt _symrom_g_dtmEvt + //#define g_dtmExtLen _symrom_g_dtmExtLen + //#define g_dtmFoff _symrom_g_dtmFoff + //#define g_dtmFreq _symrom_g_dtmFreq + //#define g_dtmLength _symrom_g_dtmLength + //#define g_dtmModeType _symrom_g_dtmModeType + //#define g_dtmPara _symrom_g_dtmPara + //#define g_dtmPerAutoIntv _symrom_g_dtmPerAutoIntv + //#define g_dtmPKT _symrom_g_dtmPKT + //#define g_dtmPktCount _symrom_g_dtmPktCount + //#define g_dtmPktIntv _symrom_g_dtmPktIntv + //#define g_dtmRsp _symrom_g_dtmRsp + //#define g_dtmRssi _symrom_g_dtmRssi + //#define g_dtmRxCrcNum _symrom_g_dtmRxCrcNum + //#define g_dtmRxTONum _symrom_g_dtmRxTONum + //#define g_dtmStatus _symrom_g_dtmStatus + //#define g_dtmTick _symrom_g_dtmTick + //#define g_dtmTpCalEnable _symrom_g_dtmTpCalEnable + //#define g_dtmTxPower _symrom_g_dtmTxPower + #define g_extAdvNumber _symrom_g_extAdvNumber + #define g_getPn23_cnt _symrom_g_getPn23_cnt + #define g_getPn23_seed _symrom_g_getPn23_seed + #define g_hclk _symrom_g_hclk + #define g_interAuxPduDuration _symrom_g_interAuxPduDuration + #define g_ll_conn_ctx _symrom_g_ll_conn_ctx + #define g_llHdcDirAdvTime _symrom_g_llHdcDirAdvTime + #define g_llPduLen _symrom_g_llPduLen + #define g_llPeriodAdvSyncInfo _symrom_g_llPeriodAdvSyncInfo + #define g_llResolvinglist _symrom_g_llResolvinglist + #define g_llRlDeviceNum _symrom_g_llRlDeviceNum + #define g_llRlEnable _symrom_g_llRlEnable + #define g_llRlTimeout _symrom_g_llRlTimeout + #define g_llSleepContext _symrom_g_llSleepContext + #define g_llWhitelist _symrom_g_llWhitelist + #define g_llWlDeviceNum _symrom_g_llWlDeviceNum + #define g_maxConnNum _symrom_g_maxConnNum + #define g_maxPktPerEventRx _symrom_g_maxPktPerEventRx + #define g_maxPktPerEventTx _symrom_g_maxPktPerEventTx + #define g_new_master_delta _symrom_g_new_master_delta + #define g_osal_tick_trim _symrom_g_osal_tick_trim + #define g_osalTickTrim_mod _symrom_g_osalTickTrim_mod + #define g_pAdvSchInfo _symrom_g_pAdvSchInfo + #define g_pAdvSchInfo_periodic _symrom_g_pAdvSchInfo_periodic + #define g_perioAdvNumber _symrom_g_perioAdvNumber + #define g_pExtendedAdvInfo _symrom_g_pExtendedAdvInfo + #define g_phyChg_taskEvent _symrom_g_phyChg_taskEvent + #define g_phyChg_taskID _symrom_g_phyChg_taskID + #define g_pLLcteISample _symrom_g_pLLcteISample + #define g_pLLcteQSample _symrom_g_pLLcteQSample + #define g_pmCounters _symrom_g_pmCounters + #define g_pPeriodicAdvInfo _symrom_g_pPeriodicAdvInfo + //#define g_rfPhyClkSel _symrom_g_rfPhyClkSel + //#define g_rfPhyDtmCmd _symrom_g_rfPhyDtmCmd + //#define g_rfPhyDtmEvt _symrom_g_rfPhyDtmEvt + //#define g_rfPhyFreqOffSet _symrom_g_rfPhyFreqOffSet + //#define g_rfPhyPktFmt _symrom_g_rfPhyPktFmt + //#define g_rfPhyRxDcIQ _symrom_g_rfPhyRxDcIQ + //#define g_rfPhyTpCal0 _symrom_g_rfPhyTpCal0 + //#define g_rfPhyTpCal0_2Mbps _symrom_g_rfPhyTpCal0_2Mbps + //#define g_rfPhyTpCal1 _symrom_g_rfPhyTpCal1 + //#define g_rfPhyTpCal1_2Mbps _symrom_g_rfPhyTpCal1_2Mbps + //#define g_rfPhyTxPower _symrom_g_rfPhyTxPower + #define g_rx_adv_buf _symrom_g_rx_adv_buf + //#define g_rxAdcClkSel _symrom_g_rxAdcClkSel + #define g_same_rf_channel_flag _symrom_g_same_rf_channel_flag + #define g_schExtAdvNum _symrom_g_schExtAdvNum + #define g_schExtAdvNum_periodic _symrom_g_schExtAdvNum_periodic + #define g_smartWindowActive _symrom_g_smartWindowActive + #define g_smartWindowActiveCnt _symrom_g_smartWindowActiveCnt + #define g_smartWindowLater _symrom_g_smartWindowLater + #define g_smartWindowPreAnchPoint _symrom_g_smartWindowPreAnchPoint + #define g_smartWindowRTOCnt _symrom_g_smartWindowRTOCnt + #define g_smartWindowSize _symrom_g_smartWindowSize + #define g_smartWindowSizeNew _symrom_g_smartWindowSizeNew + #define g_system_clk _symrom_g_system_clk + #define g_TIM2_IRQ_PendingTick _symrom_g_TIM2_IRQ_PendingTick + #define g_TIM2_IRQ_TIM3_CurrCount _symrom_g_TIM2_IRQ_TIM3_CurrCount + #define g_TIM2_IRQ_to_Sleep_DeltTick _symrom_g_TIM2_IRQ_to_Sleep_DeltTick + #define g_TIM2_wakeup_delay _symrom_g_TIM2_wakeup_delay + #define g_timerExpiryTick _symrom_g_timerExpiryTick + #define g_tx_adv_buf _symrom_g_tx_adv_buf + #define g_tx_ext_adv_buf _symrom_g_tx_ext_adv_buf + #define g_wakeup_rtc_tick _symrom_g_wakeup_rtc_tick + #define get_rx_read_ptr _symrom_get_rx_read_ptr + #define get_rx_write_ptr _symrom_get_rx_write_ptr + #define get_sleep_flag _symrom_get_sleep_flag + #define get_timer_count _symrom_get_timer_count + #define get_timer_int _symrom_get_timer_int + #define get_tx_read_ptr _symrom_get_tx_read_ptr + #define get_tx_write_ptr _symrom_get_tx_write_ptr + #define getMcuPrecisionCount _symrom_getMcuPrecisionCount + #define getPN23RandNumber _symrom_getPN23RandNumber + #define getRxBufferFree _symrom_getRxBufferFree + #define getRxBufferSize _symrom_getRxBufferSize + #define getSleepMode _symrom_getSleepMode + #define getTxBufferFree _symrom_getTxBufferFree + #define getTxBufferSize _symrom_getTxBufferSize + #define gpio_cfg_analog_io _symrom_gpio_cfg_analog_io + #define gpio_dir _symrom_gpio_dir + #define gpio_fmux_control _symrom_gpio_fmux_control + #define gpio_fmux_set _symrom_gpio_fmux_set + #define gpio_in_trigger _symrom_gpio_in_trigger + #define gpio_init _symrom_gpio_init + #define gpio_interrupt_set _symrom_gpio_interrupt_set + #define GPIO_IRQHandler _symrom_GPIO_IRQHandler + #define gpio_pull_set _symrom_gpio_pull_set + #define gpio_read _symrom_gpio_read + #define gpio_wakeup_set _symrom_gpio_wakeup_set + #define gpio_write _symrom_gpio_write + #define HardFault_Handler _symrom_HardFault_Handler + #define HardFault_IRQHandler _symrom_HardFault_IRQHandler + #define HCI_bm_alloc _symrom_HCI_bm_alloc + #define HCI_CommandCompleteEvent _symrom_HCI_CommandCompleteEvent + #define HCI_CommandStatusEvent _symrom_HCI_CommandStatusEvent + #define HCI_DataBufferOverflowEvent _symrom_HCI_DataBufferOverflowEvent + #define HCI_DisconnectCmd _symrom_HCI_DisconnectCmd + #define HCI_ExtTaskRegister _symrom_HCI_ExtTaskRegister + #define HCI_GAPTaskRegister _symrom_HCI_GAPTaskRegister + #define HCI_HardwareErrorEvent _symrom_HCI_HardwareErrorEvent + #define HCI_HostBufferSizeCmd _symrom_HCI_HostBufferSizeCmd + #define HCI_HostNumCompletedPktCmd _symrom_HCI_HostNumCompletedPktCmd + #define HCI_Init _symrom_HCI_Init + #define HCI_L2CAPTaskRegister _symrom_HCI_L2CAPTaskRegister + #define HCI_LE_AddDevToResolvingListCmd _symrom_HCI_LE_AddDevToResolvingListCmd + #define HCI_LE_AddWhiteListCmd _symrom_HCI_LE_AddWhiteListCmd + #define HCI_LE_ClearAdvSetsCmd _symrom_HCI_LE_ClearAdvSetsCmd + #define HCI_LE_ClearResolvingListCmd _symrom_HCI_LE_ClearResolvingListCmd + #define HCI_LE_ClearWhiteListCmd _symrom_HCI_LE_ClearWhiteListCmd + #define HCI_LE_Connection_CTE_Request_EnableCmd _symrom_HCI_LE_Connection_CTE_Request_EnableCmd + #define HCI_LE_Connection_CTE_Response_EnableCmd _symrom_HCI_LE_Connection_CTE_Response_EnableCmd + #define HCI_LE_ConnectionlessCTE_TransmitEnableCmd _symrom_HCI_LE_ConnectionlessCTE_TransmitEnableCmd + #define HCI_LE_ConnectionlessCTE_TransmitParamCmd _symrom_HCI_LE_ConnectionlessCTE_TransmitParamCmd + #define HCI_LE_ConnectionlessIQ_SampleEnableCmd _symrom_HCI_LE_ConnectionlessIQ_SampleEnableCmd + #define HCI_LE_ConnUpdateCmd _symrom_HCI_LE_ConnUpdateCmd + #define HCI_LE_CreateConnCancelCmd _symrom_HCI_LE_CreateConnCancelCmd + #define HCI_LE_CreateConnCmd _symrom_HCI_LE_CreateConnCmd + #define HCI_LE_EncryptCmd _symrom_HCI_LE_EncryptCmd + #define HCI_LE_ExtendedCreateConnectionCmd _symrom_HCI_LE_ExtendedCreateConnectionCmd + #define HCI_LE_LtkReqNegReplyCmd _symrom_HCI_LE_LtkReqNegReplyCmd + #define HCI_LE_LtkReqReplyCmd _symrom_HCI_LE_LtkReqReplyCmd + #define HCI_LE_PeriodicAdvertisingCreateSyncCancelCmd _symrom_HCI_LE_PeriodicAdvertisingCreateSyncCancelCmd + #define HCI_LE_PeriodicAdvertisingCreateSyncCmd _symrom_HCI_LE_PeriodicAdvertisingCreateSyncCmd + #define HCI_LE_PeriodicAdvertisingTerminateSyncCmd _symrom_HCI_LE_PeriodicAdvertisingTerminateSyncCmd + #define HCI_LE_RandCmd _symrom_HCI_LE_RandCmd + #define HCI_LE_READ_Anatenna_InfoCmd _symrom_HCI_LE_READ_Anatenna_InfoCmd + #define HCI_LE_ReadAdvChanTxPowerCmd _symrom_HCI_LE_ReadAdvChanTxPowerCmd + #define HCI_LE_ReadBufSizeCmd _symrom_HCI_LE_ReadBufSizeCmd + #define HCI_LE_ReadChannelMapCmd _symrom_HCI_LE_ReadChannelMapCmd + #define HCI_LE_ReadLocalSupportedFeaturesCmd _symrom_HCI_LE_ReadLocalSupportedFeaturesCmd + #define HCI_LE_ReadMaxDataLengthCmd _symrom_HCI_LE_ReadMaxDataLengthCmd + #define HCI_LE_ReadMaximumAdvDataLengthCmd _symrom_HCI_LE_ReadMaximumAdvDataLengthCmd + #define HCI_LE_ReadNumberOfSupportAdvSetCmd _symrom_HCI_LE_ReadNumberOfSupportAdvSetCmd + #define HCI_LE_ReadPhyMode _symrom_HCI_LE_ReadPhyMode + #define HCI_LE_ReadRemoteUsedFeaturesCmd _symrom_HCI_LE_ReadRemoteUsedFeaturesCmd + #define HCI_LE_ReadResolvingListSizeCmd _symrom_HCI_LE_ReadResolvingListSizeCmd + #define HCI_LE_ReadSuggestedDefaultDataLengthCmd _symrom_HCI_LE_ReadSuggestedDefaultDataLengthCmd + #define HCI_LE_ReadSupportedStatesCmd _symrom_HCI_LE_ReadSupportedStatesCmd + #define HCI_LE_ReadWhiteListSizeCmd _symrom_HCI_LE_ReadWhiteListSizeCmd + #define HCI_LE_ReceiverTestCmd _symrom_HCI_LE_ReceiverTestCmd + #define HCI_LE_RemoveAdvSetCmd _symrom_HCI_LE_RemoveAdvSetCmd + #define HCI_LE_RemoveResolvingListCmd _symrom_HCI_LE_RemoveResolvingListCmd + #define HCI_LE_RemoveWhiteListCmd _symrom_HCI_LE_RemoveWhiteListCmd + #define HCI_LE_Set_ConnectionCTE_ReceiveParamCmd _symrom_HCI_LE_Set_ConnectionCTE_ReceiveParamCmd + #define HCI_LE_Set_ConnectionCTE_TransmitParamCmd _symrom_HCI_LE_Set_ConnectionCTE_TransmitParamCmd + #define HCI_LE_SetAddressResolutionEnableCmd _symrom_HCI_LE_SetAddressResolutionEnableCmd + #define HCI_LE_SetAdvDataCmd _symrom_HCI_LE_SetAdvDataCmd + #define HCI_LE_SetAdvEnableCmd _symrom_HCI_LE_SetAdvEnableCmd + #define HCI_LE_SetAdvParamCmd _symrom_HCI_LE_SetAdvParamCmd + #define HCI_LE_SetDataLengthCmd _symrom_HCI_LE_SetDataLengthCmd + #define HCI_LE_SetDefaultPhyMode _symrom_HCI_LE_SetDefaultPhyMode + #define HCI_LE_SetEventMaskCmd _symrom_HCI_LE_SetEventMaskCmd + #define HCI_LE_SetExtAdvDataCmd _symrom_HCI_LE_SetExtAdvDataCmd + #define HCI_LE_SetExtAdvEnableCmd _symrom_HCI_LE_SetExtAdvEnableCmd + #define HCI_LE_SetExtAdvParamCmd _symrom_HCI_LE_SetExtAdvParamCmd + #define HCI_LE_SetExtAdvSetRandomAddressCmd _symrom_HCI_LE_SetExtAdvSetRandomAddressCmd + #define HCI_LE_SetExtendedScanEnableCmd _symrom_HCI_LE_SetExtendedScanEnableCmd + #define HCI_LE_SetExtendedScanParametersCmd _symrom_HCI_LE_SetExtendedScanParametersCmd + #define HCI_LE_SetExtScanRspDataCmd _symrom_HCI_LE_SetExtScanRspDataCmd + #define HCI_LE_SetHostChanClassificationCmd _symrom_HCI_LE_SetHostChanClassificationCmd + #define HCI_LE_SetPeriodicAdvDataCmd _symrom_HCI_LE_SetPeriodicAdvDataCmd + #define HCI_LE_SetPeriodicAdvEnableCmd _symrom_HCI_LE_SetPeriodicAdvEnableCmd + #define HCI_LE_SetPeriodicAdvParameterCmd _symrom_HCI_LE_SetPeriodicAdvParameterCmd + #define HCI_LE_SetPhyMode _symrom_HCI_LE_SetPhyMode + #define HCI_LE_SetRandomAddressCmd _symrom_HCI_LE_SetRandomAddressCmd + #define HCI_LE_SetResolvablePrivateAddressTimeoutCmd _symrom_HCI_LE_SetResolvablePrivateAddressTimeoutCmd + #define HCI_LE_SetScanEnableCmd _symrom_HCI_LE_SetScanEnableCmd + #define HCI_LE_SetScanParamCmd _symrom_HCI_LE_SetScanParamCmd + #define HCI_LE_SetScanRspDataCmd _symrom_HCI_LE_SetScanRspDataCmd + #define HCI_LE_StartEncyptCmd _symrom_HCI_LE_StartEncyptCmd + #define HCI_LE_TestEndCmd _symrom_HCI_LE_TestEndCmd + #define HCI_LE_TransmitterTestCmd _symrom_HCI_LE_TransmitterTestCmd + #define HCI_LE_WriteSuggestedDefaultDataLengthCmd _symrom_HCI_LE_WriteSuggestedDefaultDataLengthCmd + #define HCI_NumOfCompletedPacketsEvent _symrom_HCI_NumOfCompletedPacketsEvent + #define HCI_ProcessEvent _symrom_HCI_ProcessEvent + #define HCI_ReadBDADDRCmd _symrom_HCI_ReadBDADDRCmd + #define HCI_ReadLocalSupportedCommandsCmd _symrom_HCI_ReadLocalSupportedCommandsCmd + #define HCI_ReadLocalSupportedFeaturesCmd _symrom_HCI_ReadLocalSupportedFeaturesCmd + #define HCI_ReadLocalVersionInfoCmd _symrom_HCI_ReadLocalVersionInfoCmd + #define HCI_ReadRemoteVersionInfoCmd _symrom_HCI_ReadRemoteVersionInfoCmd + #define HCI_ReadRssiCmd _symrom_HCI_ReadRssiCmd + #define HCI_ReadTransmitPowerLevelCmd _symrom_HCI_ReadTransmitPowerLevelCmd + #define HCI_ResetCmd _symrom_HCI_ResetCmd + #define HCI_ReverseBytes _symrom_HCI_ReverseBytes + #define HCI_SendCommandCompleteEvent _symrom_HCI_SendCommandCompleteEvent + #define HCI_SendCommandStatusEvent _symrom_HCI_SendCommandStatusEvent + #define HCI_SendControllerToHostEvent _symrom_HCI_SendControllerToHostEvent + #define HCI_SendDataPkt _symrom_HCI_SendDataPkt + #define HCI_SetControllerToHostFlowCtrlCmd _symrom_HCI_SetControllerToHostFlowCtrlCmd + #define HCI_SetEventMaskCmd _symrom_HCI_SetEventMaskCmd + #define HCI_SMPTaskRegister _symrom_HCI_SMPTaskRegister + #define HCI_TestAppTaskRegister _symrom_HCI_TestAppTaskRegister + #define HCI_ValidConnTimeParams _symrom_HCI_ValidConnTimeParams + #define HCI_VendorSpecifcCommandCompleteEvent _symrom_HCI_VendorSpecifcCommandCompleteEvent + #define hciCmdTable _symrom_hciCmdTable + #define hciCtrlCmdToken _symrom_hciCtrlCmdToken + #define hciExtTaskID _symrom_hciExtTaskID + #define hciGapTaskID _symrom_hciGapTaskID + #define hciInitEventMasks _symrom_hciInitEventMasks + #define hciL2capTaskID _symrom_hciL2capTaskID + #define hciPTMenabled _symrom_hciPTMenabled + #define hciSmpTaskID _symrom_hciSmpTaskID + #define hciTaskID _symrom_hciTaskID + #define hciTestTaskID _symrom_hciTestTaskID + #define hclk_per_us _symrom_hclk_per_us + #define hclk_per_us_shift _symrom_hclk_per_us_shift + #define initInfo _symrom_initInfo + #define ISR_entry_time _symrom_ISR_entry_time + #define isSleepAllow _symrom_isSleepAllow + #define isTimer1Running _symrom_isTimer1Running + #define isTimer4Running _symrom_isTimer4Running + #define jump_area_init _symrom_jump_area_init + #define ll_add_adv_task _symrom_ll_add_adv_task + #define ll_add_adv_task_periodic _symrom_ll_add_adv_task_periodic + #define LL_AddResolvingListLDevice _symrom_LL_AddResolvingListLDevice + #define ll_addTask _symrom_ll_addTask + #define LL_AddWhiteListDevice _symrom_LL_AddWhiteListDevice + #define ll_adptive_adj_next_time _symrom_ll_adptive_adj_next_time + #define ll_adptive_smart_window _symrom_ll_adptive_smart_window + #define ll_adv_scheduler _symrom_ll_adv_scheduler + #define ll_adv_scheduler_periodic _symrom_ll_adv_scheduler_periodic + #define LL_AdvReportCback _symrom_LL_AdvReportCback + #define ll_allocAuxAdvTimeSlot _symrom_ll_allocAuxAdvTimeSlot + #define ll_allocAuxAdvTimeSlot_prd _symrom_ll_allocAuxAdvTimeSlot_prd + #define ll_CalcRandomAddr _symrom_ll_CalcRandomAddr + #define LL_ChanMapUpdate _symrom_LL_ChanMapUpdate + #define LL_ClearAdvSets _symrom_LL_ClearAdvSets + #define LL_ClearResolvingList _symrom_LL_ClearResolvingList + #define LL_ClearWhiteList _symrom_LL_ClearWhiteList + #define LL_ConnActive _symrom_LL_ConnActive + #define LL_Connection_CTE_Request_Enable _symrom_LL_Connection_CTE_Request_Enable + #define LL_Connection_CTE_Response_Enable _symrom_LL_Connection_CTE_Response_Enable + #define LL_ConnectionCompleteCback _symrom_LL_ConnectionCompleteCback + #define LL_ConnectionIQReportCback _symrom_LL_ConnectionIQReportCback + #define LL_ConnectionlessCTE_TransmitEnable _symrom_LL_ConnectionlessCTE_TransmitEnable + #define LL_ConnectionlessCTE_TransmitParam _symrom_LL_ConnectionlessCTE_TransmitParam + #define LL_ConnectionlessIQ_SampleEnable _symrom_LL_ConnectionlessIQ_SampleEnable + #define LL_ConnectionlessIQReportCback _symrom_LL_ConnectionlessIQReportCback + #define LL_ConnParamUpdateCback _symrom_LL_ConnParamUpdateCback + #define LL_ConnUpdate _symrom_LL_ConnUpdate + #define LL_CreateConn _symrom_LL_CreateConn + #define LL_CreateConnCancel _symrom_LL_CreateConnCancel + #define LL_CTE_Report_FailedCback _symrom_LL_CTE_Report_FailedCback + #define LL_CtrlToHostFlowControl _symrom_LL_CtrlToHostFlowControl + #define LL_DataLengthChangeCback _symrom_LL_DataLengthChangeCback + #define ll_debug_output _symrom_ll_debug_output + #define ll_delete_adv_task _symrom_ll_delete_adv_task + #define ll_delete_adv_task_periodic _symrom_ll_delete_adv_task_periodic + #define ll_deleteTask _symrom_ll_deleteTask + #define LL_DirectTestEnd _symrom_LL_DirectTestEnd + #define LL_DirectTestTxTest _symrom_LL_DirectTestTxTest + #define LL_Disconnect _symrom_LL_Disconnect + #define LL_DisconnectCback _symrom_LL_DisconnectCback + #define LL_ENC_AES128_Encrypt _symrom_LL_ENC_AES128_Encrypt + #define LL_ENC_Decrypt _symrom_LL_ENC_Decrypt + #define LL_ENC_Encrypt _symrom_LL_ENC_Encrypt + #define LL_ENC_GenDeviceIV _symrom_LL_ENC_GenDeviceIV + #define LL_ENC_GenDeviceSKD _symrom_LL_ENC_GenDeviceSKD + #define LL_ENC_GenerateNonce _symrom_LL_ENC_GenerateNonce + #define LL_ENC_GeneratePseudoRandNum _symrom_LL_ENC_GeneratePseudoRandNum + #define LL_ENC_GenerateTrueRandNum _symrom_LL_ENC_GenerateTrueRandNum + #define LL_ENC_LoadKey _symrom_LL_ENC_LoadKey + #define LL_ENC_ReverseBytes _symrom_LL_ENC_ReverseBytes + #define LL_ENC_sm_ah _symrom_LL_ENC_sm_ah + #define LL_EncChangeCback _symrom_LL_EncChangeCback + #define LL_EncKeyRefreshCback _symrom_LL_EncKeyRefreshCback + #define LL_EncLtkNegReply _symrom_LL_EncLtkNegReply + #define LL_EncLtkReply _symrom_LL_EncLtkReply + #define LL_EncLtkReqCback _symrom_LL_EncLtkReqCback + #define LL_Encrypt _symrom_LL_Encrypt + #define LL_evt_schedule _symrom_LL_evt_schedule + #define ll_ext_adv_schedule_next_event _symrom_ll_ext_adv_schedule_next_event + #define LL_EXT_AdvEventNotice _symrom_LL_EXT_AdvEventNotice + #define LL_EXT_BuildRevision _symrom_LL_EXT_BuildRevision + #define LL_EXT_ClkDivOnHalt _symrom_LL_EXT_ClkDivOnHalt + #define LL_EXT_ConnEventNotice _symrom_LL_EXT_ConnEventNotice + #define LL_EXT_DeclareNvUsage _symrom_LL_EXT_DeclareNvUsage + #define LL_EXT_Decrypt _symrom_LL_EXT_Decrypt + #define LL_EXT_DelaySleep _symrom_LL_EXT_DelaySleep + #define LL_EXT_DisconnectImmed _symrom_LL_EXT_DisconnectImmed + #define LL_EXT_EndModemTest _symrom_LL_EXT_EndModemTest + #define LL_EXT_HaltDuringRf _symrom_LL_EXT_HaltDuringRf + #define LL_EXT_Init_IQ_pBuff _symrom_LL_EXT_Init_IQ_pBuff + #define ll_ext_init_schedule_next_event _symrom_ll_ext_init_schedule_next_event + #define LL_EXT_MapPmIoPort _symrom_LL_EXT_MapPmIoPort + #define LL_EXT_ModemHopTestTx _symrom_LL_EXT_ModemHopTestTx + #define LL_EXT_ModemTestRx _symrom_LL_EXT_ModemTestRx + #define LL_EXT_ModemTestTx _symrom_LL_EXT_ModemTestTx + #define LL_EXT_NumComplPktsLimit _symrom_LL_EXT_NumComplPktsLimit + #define LL_EXT_OnePacketPerEvent _symrom_LL_EXT_OnePacketPerEvent + #define LL_EXT_OverlappedProcessing _symrom_LL_EXT_OverlappedProcessing + #define LL_EXT_PacketErrorRate _symrom_LL_EXT_PacketErrorRate + #define LL_EXT_PERbyChan _symrom_LL_EXT_PERbyChan + #define LL_EXT_ResetSystem _symrom_LL_EXT_ResetSystem + #define LL_EXT_SaveFreqTune _symrom_LL_EXT_SaveFreqTune + #define ll_ext_scan_schedule_next_event _symrom_ll_ext_scan_schedule_next_event + #define LL_EXT_SetBDADDR _symrom_LL_EXT_SetBDADDR + #define LL_EXT_SetFastTxResponseTime _symrom_LL_EXT_SetFastTxResponseTime + #define LL_EXT_SetFreqTune _symrom_LL_EXT_SetFreqTune + #define LL_EXT_SetLocalSupportedFeatures _symrom_LL_EXT_SetLocalSupportedFeatures + #define LL_EXT_SetMaxDtmTxPower _symrom_LL_EXT_SetMaxDtmTxPower + #define LL_EXT_SetRxGain _symrom_LL_EXT_SetRxGain + #define LL_EXT_SetSCA _symrom_LL_EXT_SetSCA + #define LL_EXT_SetSlaveLatencyOverride _symrom_LL_EXT_SetSlaveLatencyOverride + #define LL_EXT_SetTxPower _symrom_LL_EXT_SetTxPower + #define LL_ExtAdvReportCback _symrom_LL_ExtAdvReportCback + #define LL_extAdvTimerExpProcess _symrom_LL_extAdvTimerExpProcess + #define LL_ExtendedCreateConnection _symrom_LL_ExtendedCreateConnection + #define LL_extInitTimerExpProcess _symrom_LL_extInitTimerExpProcess + #define LL_extScanTimerExpProcess _symrom_LL_extScanTimerExpProcess + #define ll_generateExtAdvDid _symrom_ll_generateExtAdvDid + #define ll_generateTxBuffer _symrom_ll_generateTxBuffer + #define ll_get_next_active_conn _symrom_ll_get_next_active_conn + #define ll_get_next_timer _symrom_ll_get_next_timer + #define ll_getFirstAdvChn _symrom_ll_getFirstAdvChn + #define ll_getRPAListEntry _symrom_ll_getRPAListEntry + #define ll_hw_clr_irq _symrom_ll_hw_clr_irq + #define ll_hw_config _symrom_ll_hw_config + #define ll_hw_get_anchor _symrom_ll_hw_get_anchor + #define ll_hw_get_fsm_status _symrom_ll_hw_get_fsm_status + #define ll_hw_get_iq_RawSample _symrom_ll_hw_get_iq_RawSample + #define ll_hw_get_irq_status _symrom_ll_hw_get_irq_status + #define ll_hw_get_last_ack _symrom_ll_hw_get_last_ack + #define ll_hw_get_loop_cycle _symrom_ll_hw_get_loop_cycle + #define ll_hw_get_loop_time _symrom_ll_hw_get_loop_time + #define ll_hw_get_nAck _symrom_ll_hw_get_nAck + #define ll_hw_get_rfifo_depth _symrom_ll_hw_get_rfifo_depth + #define ll_hw_get_rfifo_info _symrom_ll_hw_get_rfifo_info + #define ll_hw_get_rxPkt_CrcErr_num _symrom_ll_hw_get_rxPkt_CrcErr_num + #define ll_hw_get_rxPkt_CrcOk_num _symrom_ll_hw_get_rxPkt_CrcOk_num + #define ll_hw_get_rxPkt_num _symrom_ll_hw_get_rxPkt_num + #define ll_hw_get_rxPkt_stats _symrom_ll_hw_get_rxPkt_stats + #define ll_hw_get_rxPkt_Total_num _symrom_ll_hw_get_rxPkt_Total_num + #define ll_hw_get_snNesn _symrom_ll_hw_get_snNesn + #define ll_hw_get_tfifo_info _symrom_ll_hw_get_tfifo_info + #define ll_hw_get_tfifo_wrptr _symrom_ll_hw_get_tfifo_wrptr + #define ll_hw_get_tr_mode _symrom_ll_hw_get_tr_mode + #define ll_hw_get_txAck _symrom_ll_hw_get_txAck + #define ll_hw_go _symrom_ll_hw_go + #define ll_hw_ign_rfifo _symrom_ll_hw_ign_rfifo + #define ll_hw_process_RTO _symrom_ll_hw_process_RTO + #define ll_hw_read_rfifo _symrom_ll_hw_read_rfifo + #define ll_hw_read_rfifo_pplus _symrom_ll_hw_read_rfifo_pplus + #define ll_hw_read_rfifo_zb _symrom_ll_hw_read_rfifo_zb + #define ll_hw_read_tfifo_packet _symrom_ll_hw_read_tfifo_packet + #define ll_hw_read_tfifo_rtlp _symrom_ll_hw_read_tfifo_rtlp + #define ll_hw_rst_rfifo _symrom_ll_hw_rst_rfifo + #define ll_hw_rst_tfifo _symrom_ll_hw_rst_tfifo + #define ll_hw_set_ant_pattern _symrom_ll_hw_set_ant_pattern + #define ll_hw_set_ant_switch_mode _symrom_ll_hw_set_ant_switch_mode + #define ll_hw_set_ant_switch_timing _symrom_ll_hw_set_ant_switch_timing + #define ll_hw_set_crc_fmt _symrom_ll_hw_set_crc_fmt + #define ll_hw_set_cte_rxSupp _symrom_ll_hw_set_cte_rxSupp + #define ll_hw_set_cte_txSupp _symrom_ll_hw_set_cte_txSupp + #define ll_hw_set_empty_head _symrom_ll_hw_set_empty_head + #define ll_hw_set_irq _symrom_ll_hw_set_irq + #define ll_hw_set_loop_nack_num _symrom_ll_hw_set_loop_nack_num + #define ll_hw_set_loop_timeout _symrom_ll_hw_set_loop_timeout + #define ll_hw_set_pplus_pktfmt _symrom_ll_hw_set_pplus_pktfmt + #define ll_hw_set_rtlp _symrom_ll_hw_set_rtlp + #define ll_hw_set_rtlp_1st _symrom_ll_hw_set_rtlp_1st + #define ll_hw_set_rtx _symrom_ll_hw_set_rtx + #define ll_hw_set_rx_timeout _symrom_ll_hw_set_rx_timeout + #define ll_hw_set_rx_timeout_1st _symrom_ll_hw_set_rx_timeout_1st + #define ll_hw_set_rx_tx_interval _symrom_ll_hw_set_rx_tx_interval + #define ll_hw_set_srx _symrom_ll_hw_set_srx + #define ll_hw_set_stx _symrom_ll_hw_set_stx + #define ll_hw_set_tfifo_space _symrom_ll_hw_set_tfifo_space + #define ll_hw_set_timing _symrom_ll_hw_set_timing + #define ll_hw_set_trlp _symrom_ll_hw_set_trlp + #define ll_hw_set_trx _symrom_ll_hw_set_trx + #define ll_hw_set_trx_settle _symrom_ll_hw_set_trx_settle + #define ll_hw_set_tx_rx_interval _symrom_ll_hw_set_tx_rx_interval + #define ll_hw_set_tx_rx_release _symrom_ll_hw_set_tx_rx_release + #define ll_hw_trigger _symrom_ll_hw_trigger + #define ll_hw_trx_settle_config _symrom_ll_hw_trx_settle_config + #define ll_hw_tx2rx_timing_config _symrom_ll_hw_tx2rx_timing_config + #define ll_hw_update _symrom_ll_hw_update + #define ll_hw_update_rtlp_mode _symrom_ll_hw_update_rtlp_mode + #define ll_hw_update_trlp_mode _symrom_ll_hw_update_trlp_mode + #define ll_hw_write_tfifo _symrom_ll_hw_write_tfifo + #define LL_Init _symrom_LL_Init + #define LL_InitConnectContext _symrom_LL_InitConnectContext + #define LL_InitExtendedAdv _symrom_LL_InitExtendedAdv + #define LL_InitExtendedScan _symrom_LL_InitExtendedScan + #define LL_InitPeriodicAdv _symrom_LL_InitPeriodicAdv + #define LL_IRQHandler _symrom_LL_IRQHandler + #define ll_isAddrInWhiteList _symrom_ll_isAddrInWhiteList + #define ll_isFirstAdvChn _symrom_ll_isFirstAdvChn + #define LL_master_conn_event _symrom_LL_master_conn_event + #define LL_NumEmptyWlEntries _symrom_LL_NumEmptyWlEntries + #define ll_parseExtHeader _symrom_ll_parseExtHeader + #define LL_PeriodicAdvertisingCreateSync _symrom_LL_PeriodicAdvertisingCreateSync + #define LL_PeriodicAdvertisingCreateSyncCancel _symrom_LL_PeriodicAdvertisingCreateSyncCancel + #define LL_PeriodicAdvertisingTerminateSync _symrom_LL_PeriodicAdvertisingTerminateSync + #define LL_PhyUpdate _symrom_LL_PhyUpdate + #define LL_PhyUpdateCompleteCback _symrom_LL_PhyUpdateCompleteCback + #define LL_PLUS_AdvDataFilterCBack _symrom_LL_PLUS_AdvDataFilterCBack + #define LL_PLUS_DisableSlaveLatency _symrom_LL_PLUS_DisableSlaveLatency + #define LL_PLUS_EnableSlaveLatency _symrom_LL_PLUS_EnableSlaveLatency + #define LL_PLUS_GetAdvDataExtendData _symrom_LL_PLUS_GetAdvDataExtendData + #define LL_PLUS_GetScanerAddr _symrom_LL_PLUS_GetScanerAddr + #define LL_PLUS_GetScanRequestExtendData _symrom_LL_PLUS_GetScanRequestExtendData + #define LL_PLUS_PerStasReadByChn _symrom_LL_PLUS_PerStasReadByChn + #define LL_PLUS_PerStats_Init _symrom_LL_PLUS_PerStats_Init + #define LL_PLUS_PerStatsReset _symrom_LL_PLUS_PerStatsReset + #define LL_PLUS_ScanRequestFilterCBack _symrom_LL_PLUS_ScanRequestFilterCBack + #define LL_PLUS_SetAdvDataFilterCB _symrom_LL_PLUS_SetAdvDataFilterCB + #define LL_PLUS_SetScanRequestData _symrom_LL_PLUS_SetScanRequestData + #define LL_PLUS_SetScanRequestFilterCB _symrom_LL_PLUS_SetScanRequestFilterCB + #define LL_PLUS_SetScanRsqData _symrom_LL_PLUS_SetScanRsqData + #define LL_PLUS_SetScanRsqDataByIndex _symrom_LL_PLUS_SetScanRsqDataByIndex + #define ll_prd_adv_schedule_next_event _symrom_ll_prd_adv_schedule_next_event + #define ll_prd_scan_schedule_next_event _symrom_ll_prd_scan_schedule_next_event + #define LL_PrdAdvReportCback _symrom_LL_PrdAdvReportCback + #define LL_PrdAdvSyncEstablishedCback _symrom_LL_PrdAdvSyncEstablishedCback + #define LL_PrdAdvSyncLostCback _symrom_LL_PrdAdvSyncLostCback + #define LL_prdAdvTimerExpProcess _symrom_LL_prdAdvTimerExpProcess + #define LL_prdScanTimerExpProcess _symrom_LL_prdScanTimerExpProcess + #define ll_processBasicIRQ _symrom_ll_processBasicIRQ + #define LL_ProcessEvent _symrom_LL_ProcessEvent + #define ll_processExtAdvIRQ _symrom_ll_processExtAdvIRQ + #define ll_processExtInitIRQ _symrom_ll_processExtInitIRQ + #define ll_processExtScanIRQ _symrom_ll_processExtScanIRQ + #define ll_processMissMasterEvt _symrom_ll_processMissMasterEvt + #define ll_processMissSlaveEvt _symrom_ll_processMissSlaveEvt + #define ll_processPrdAdvIRQ _symrom_ll_processPrdAdvIRQ + #define ll_processPrdScanIRQ _symrom_ll_processPrdScanIRQ + #define LL_PseudoRand _symrom_LL_PseudoRand + #define LL_Rand _symrom_LL_Rand + #define LL_RandCback _symrom_LL_RandCback + #define LL_READ_Anatenna_Info _symrom_LL_READ_Anatenna_Info + #define ll_read_rxfifo _symrom_ll_read_rxfifo + #define LL_ReadAdvChanTxPower _symrom_LL_ReadAdvChanTxPower + #define LL_ReadBDADDR _symrom_LL_ReadBDADDR + #define LL_ReadCarrSens _symrom_LL_ReadCarrSens + #define LL_ReadChanMap _symrom_LL_ReadChanMap + #define LL_ReadFoff _symrom_LL_ReadFoff + #define ll_readLocalIRK _symrom_ll_readLocalIRK + #define LL_ReadLocalSupportedFeatures _symrom_LL_ReadLocalSupportedFeatures + #define LL_ReadLocalVersionInfo _symrom_LL_ReadLocalVersionInfo + #define LL_ReadMaximumAdvDataLength _symrom_LL_ReadMaximumAdvDataLength + #define LL_ReadNumberOfSupportAdvSet _symrom_LL_ReadNumberOfSupportAdvSet + #define LL_ReadRemoteUsedFeatures _symrom_LL_ReadRemoteUsedFeatures + #define LL_ReadRemoteUsedFeaturesCompleteCback _symrom_LL_ReadRemoteUsedFeaturesCompleteCback + #define LL_ReadRemoteVersionInfo _symrom_LL_ReadRemoteVersionInfo + #define LL_ReadRemoteVersionInfoCback _symrom_LL_ReadRemoteVersionInfoCback + #define LL_ReadResolvingListSize _symrom_LL_ReadResolvingListSize + #define LL_ReadRssi _symrom_LL_ReadRssi + #define LL_ReadSupportedStates _symrom_LL_ReadSupportedStates + #define LL_ReadTxPowerLevel _symrom_LL_ReadTxPowerLevel + #define LL_ReadWlSize _symrom_LL_ReadWlSize + #define ll_remain_time _symrom_ll_remain_time + #define LL_RemoveAdvSet _symrom_LL_RemoveAdvSet + #define LL_RemoveResolvingListDevice _symrom_LL_RemoveResolvingListDevice + #define LL_RemoveWhiteListDevice _symrom_LL_RemoveWhiteListDevice + #define LL_Reset _symrom_LL_Reset + #define ll_ResolveRandomAddrs _symrom_ll_ResolveRandomAddrs + #define LL_RX_bm_alloc _symrom_LL_RX_bm_alloc + #define LL_RxDataCompleteCback _symrom_LL_RxDataCompleteCback + #define ll_schedule_next_event _symrom_ll_schedule_next_event + #define ll_scheduler _symrom_ll_scheduler + #define LL_Set_ConnectionCTE_ReceiveParam _symrom_LL_Set_ConnectionCTE_ReceiveParam + #define LL_Set_ConnectionCTE_TransmitParam _symrom_LL_Set_ConnectionCTE_TransmitParam + #define LL_set_default_conn_params _symrom_LL_set_default_conn_params + #define LL_SetAddressResolutionEnable _symrom_LL_SetAddressResolutionEnable + #define LL_SetAdvControl _symrom_LL_SetAdvControl + #define LL_SetAdvData _symrom_LL_SetAdvData + #define LL_SetAdvParam _symrom_LL_SetAdvParam + #define LL_SetDataLengh _symrom_LL_SetDataLengh + #define LL_SetDefaultPhyMode _symrom_LL_SetDefaultPhyMode + #define LL_SetExtAdvData _symrom_LL_SetExtAdvData + #define LL_SetExtAdvEnable _symrom_LL_SetExtAdvEnable + #define LL_SetExtAdvParam _symrom_LL_SetExtAdvParam + #define LL_SetExtAdvSetRandomAddress _symrom_LL_SetExtAdvSetRandomAddress + #define LL_SetExtendedScanEnable _symrom_LL_SetExtendedScanEnable + #define LL_SetExtendedScanParameters _symrom_LL_SetExtendedScanParameters + #define LL_SetExtScanRspData _symrom_LL_SetExtScanRspData + #define LL_SetPeriodicAdvData _symrom_LL_SetPeriodicAdvData + #define LL_SetPeriodicAdvEnable _symrom_LL_SetPeriodicAdvEnable + #define LL_SetPeriodicAdvParameter _symrom_LL_SetPeriodicAdvParameter + #define LL_SetPhyMode _symrom_LL_SetPhyMode + #define LL_SetRandomAddress _symrom_LL_SetRandomAddress + #define LL_SetResolvablePrivateAddressTimeout _symrom_LL_SetResolvablePrivateAddressTimeout + #define LL_SetScanControl _symrom_LL_SetScanControl + #define LL_SetScanParam _symrom_LL_SetScanParam + #define LL_SetScanRspData _symrom_LL_SetScanRspData + #define LL_SetTxPowerLevel _symrom_LL_SetTxPowerLevel + #define LL_slave_conn_event _symrom_LL_slave_conn_event + #define LL_StartEncrypt _symrom_LL_StartEncrypt + #define LL_TaskID _symrom_LL_TaskID + #define LL_TX_bm_alloc _symrom_LL_TX_bm_alloc + #define LL_TxData _symrom_LL_TxData + #define ll_updateAuxAdvTimeSlot _symrom_ll_updateAuxAdvTimeSlot + #define ll_updateExtAdvRemainderTime _symrom_ll_updateExtAdvRemainderTime + #define LL_WriteSuggestedDefaultDataLength _symrom_LL_WriteSuggestedDefaultDataLength + #define ll24BitTimeCompare _symrom_ll24BitTimeCompare + #define llAdjSlaveLatencyValue _symrom_llAdjSlaveLatencyValue + #define llAllocateSyncHandle _symrom_llAllocateSyncHandle + #define llAllocConnId _symrom_llAllocConnId + #define llAtLeastTwoChans _symrom_llAtLeastTwoChans + #define llCalcMaxScanTime _symrom_llCalcMaxScanTime + #define llCalcScaFactor _symrom_llCalcScaFactor + #define llCalcTimerDrift _symrom_llCalcTimerDrift + #define llCheckForLstoDuringSL _symrom_llCheckForLstoDuringSL + #define llCheckWhiteListUsage _symrom_llCheckWhiteListUsage + #define llConnCleanup _symrom_llConnCleanup + #define llConnTerminate _symrom_llConnTerminate + #define llConvertCtrlProcTimeoutToEvent _symrom_llConvertCtrlProcTimeoutToEvent + #define llConvertLstoToEvent _symrom_llConvertLstoToEvent + #define llCurrentScanChn _symrom_llCurrentScanChn + #define llDeleteSyncHandle _symrom_llDeleteSyncHandle + #define llDequeueCtrlPkt _symrom_llDequeueCtrlPkt + #define llDequeueDataQ _symrom_llDequeueDataQ + #define llEnqueueCtrlPkt _symrom_llEnqueueCtrlPkt + #define llEnqueueDataQ _symrom_llEnqueueDataQ + #define llEqAlreadyValidAddr _symrom_llEqAlreadyValidAddr + #define llEqSynchWord _symrom_llEqSynchWord + #define llEqualBytes _symrom_llEqualBytes + #define llEventDelta _symrom_llEventDelta + #define llEventInRange _symrom_llEventInRange + #define llGenerateCRC _symrom_llGenerateCRC + #define llGenerateValidAccessAddr _symrom_llGenerateValidAccessAddr + #define llGetNextAdvChn _symrom_llGetNextAdvChn + #define llGetNextAuxAdvChn _symrom_llGetNextAuxAdvChn + #define llGetNextDataChan _symrom_llGetNextDataChan + #define llGetNextDataChanCSA2 _symrom_llGetNextDataChanCSA2 + #define llGtSixConsecZerosOrOnes _symrom_llGtSixConsecZerosOrOnes + #define llGtTwentyFourTransitions _symrom_llGtTwentyFourTransitions + #define llInitFeatureSet _symrom_llInitFeatureSet + #define llInitFeatureSet2MPHY _symrom_llInitFeatureSet2MPHY + #define llInitFeatureSetCodedPHY _symrom_llInitFeatureSetCodedPHY + #define llInitFeatureSetDLE _symrom_llInitFeatureSetDLE + #define llLtTwoChangesInLastSixBits _symrom_llLtTwoChangesInLastSixBits + #define llMasterEvt_TaskEndOk _symrom_llMasterEvt_TaskEndOk + #define llMemCopyDst _symrom_llMemCopyDst + #define llMemCopySrc _symrom_llMemCopySrc + #define llOneBitSynchWordDiffer _symrom_llOneBitSynchWordDiffer + #define llPduLengthManagmentReset _symrom_llPduLengthManagmentReset + #define llPduLengthUpdate _symrom_llPduLengthUpdate + #define llPendingUpdateParam _symrom_llPendingUpdateParam + #define llPhyModeCtrlReset _symrom_llPhyModeCtrlReset + #define llPhyModeCtrlUpdateNotify _symrom_llPhyModeCtrlUpdateNotify + #define llProcessChanMap _symrom_llProcessChanMap + #define llProcessMasterControlPacket _symrom_llProcessMasterControlPacket + #define llProcessMasterControlProcedures _symrom_llProcessMasterControlProcedures + #define llProcessRxData _symrom_llProcessRxData + #define llProcessSlaveControlPacket _symrom_llProcessSlaveControlPacket + #define llProcessSlaveControlProcedures _symrom_llProcessSlaveControlProcedures + #define llProcessTxData _symrom_llProcessTxData + #define llReleaseAllConnId _symrom_llReleaseAllConnId + #define llReleaseConnId _symrom_llReleaseConnId + #define llReplaceCtrlPkt _symrom_llReplaceCtrlPkt + #define llResetConnId _symrom_llResetConnId + #define llResetRfCounters _symrom_llResetRfCounters + #define llScanT1 _symrom_llScanT1 + #define llScanTime _symrom_llScanTime + #define llSecAdvAllow _symrom_llSecAdvAllow + #define llSecondaryState _symrom_llSecondaryState + #define llSetNextDataChan _symrom_llSetNextDataChan + #define llSetNextPhyMode _symrom_llSetNextPhyMode + #define llSetupAdv _symrom_llSetupAdv + #define llSetupAdvExtIndPDU _symrom_llSetupAdvExtIndPDU + #define llSetupAuxAdvIndPDU _symrom_llSetupAuxAdvIndPDU + #define llSetupAuxChainIndPDU _symrom_llSetupAuxChainIndPDU + #define llSetupAuxConnectReqPDU _symrom_llSetupAuxConnectReqPDU + #define llSetupAuxConnectRspPDU _symrom_llSetupAuxConnectRspPDU + #define llSetupAuxScanRspPDU _symrom_llSetupAuxScanRspPDU + #define llSetupAuxSyncIndPDU _symrom_llSetupAuxSyncIndPDU + #define llSetupConn _symrom_llSetupConn + #define llSetupCTEReq _symrom_llSetupCTEReq + #define llSetupCTERsp _symrom_llSetupCTERsp + #define llSetupDataLenghtReq _symrom_llSetupDataLenghtReq + #define llSetupDataLenghtRsp _symrom_llSetupDataLenghtRsp + #define llSetupDirectedAdvEvt _symrom_llSetupDirectedAdvEvt + #define llSetupEncReq _symrom_llSetupEncReq + #define llSetupEncRsp _symrom_llSetupEncRsp + #define llSetupExtAdvEvent _symrom_llSetupExtAdvEvent + #define llSetupExtInit _symrom_llSetupExtInit + #define llSetupExtScan _symrom_llSetupExtScan + #define llSetupFeatureSetReq _symrom_llSetupFeatureSetReq + #define llSetupFeatureSetRsp _symrom_llSetupFeatureSetRsp + #define llSetupInit _symrom_llSetupInit + #define llSetupNextMasterEvent _symrom_llSetupNextMasterEvent + #define llSetupNextSlaveEvent _symrom_llSetupNextSlaveEvent + #define llSetupNonConnectableAdvEvt _symrom_llSetupNonConnectableAdvEvt + #define llSetupPauseEncReq _symrom_llSetupPauseEncReq + #define llSetupPauseEncRsp _symrom_llSetupPauseEncRsp + #define llSetupPhyReq _symrom_llSetupPhyReq + #define llSetupPhyRsp _symrom_llSetupPhyRsp + #define llSetupPhyUpdateInd _symrom_llSetupPhyUpdateInd + #define llSetupPrdAdvEvent _symrom_llSetupPrdAdvEvent + #define llSetupPrdScan _symrom_llSetupPrdScan + #define llSetupRejectExtInd _symrom_llSetupRejectExtInd + #define llSetupRejectInd _symrom_llSetupRejectInd + #define llSetupScan _symrom_llSetupScan + #define llSetupScanInit _symrom_llSetupScanInit + #define llSetupScannableAdvEvt _symrom_llSetupScannableAdvEvt + #define llSetupSecAdvEvt _symrom_llSetupSecAdvEvt + #define llSetupSecConnectableAdvEvt _symrom_llSetupSecConnectableAdvEvt + #define llSetupSecInit _symrom_llSetupSecInit + #define llSetupSecNonConnectableAdvEvt _symrom_llSetupSecNonConnectableAdvEvt + #define llSetupSecScan _symrom_llSetupSecScan + #define llSetupSecScannableAdvEvt _symrom_llSetupSecScannableAdvEvt + #define llSetupStartEncReq _symrom_llSetupStartEncReq + #define llSetupStartEncRsp _symrom_llSetupStartEncRsp + #define llSetupSyncInfo _symrom_llSetupSyncInfo + #define llSetupTermInd _symrom_llSetupTermInd + #define llSetupUndirectedAdvEvt _symrom_llSetupUndirectedAdvEvt + #define llSetupUnknownRsp _symrom_llSetupUnknownRsp + #define llSetupUpdateChanReq _symrom_llSetupUpdateChanReq + #define llSetupUpdateParamReq _symrom_llSetupUpdateParamReq + #define llSetupVersionIndReq _symrom_llSetupVersionIndReq + #define llSlaveEvt_TaskAbort _symrom_llSlaveEvt_TaskAbort + #define llSlaveEvt_TaskEndOk _symrom_llSlaveEvt_TaskEndOk + #define llState _symrom_llState + #define llTaskState _symrom_llTaskState + #define llTrxNumAdaptiveConfig _symrom_llTrxNumAdaptiveConfig + #define llValidAccessAddr _symrom_llValidAccessAddr + #define llWaitingIrq _symrom_llWaitingIrq + #define llWaitUs _symrom_llWaitUs + #define llWriteTxData _symrom_llWriteTxData + #define log_clr_putc _symrom_log_clr_putc + #define log_debug_level _symrom_log_debug_level + #define log_get_debug_level _symrom_log_get_debug_level + #define log_printf _symrom_log_printf + #define log_set_putc _symrom_log_set_putc + #define log_vsprintf _symrom_log_vsprintf + #define move_to_master_function _symrom_move_to_master_function + #define move_to_slave_function _symrom_move_to_slave_function + #define NMI_Handler _symrom_NMI_Handler + #define numComplPkts _symrom_numComplPkts + #define numComplPktsLimit _symrom_numComplPktsLimit + #define numHostBufs _symrom_numHostBufs + #define osal_bm_adjust_header _symrom_osal_bm_adjust_header + #define osal_bm_adjust_tail _symrom_osal_bm_adjust_tail + #define osal_bm_alloc _symrom_osal_bm_alloc + #define osal_bm_free _symrom_osal_bm_free + #define osal_buffer_uint24 _symrom_osal_buffer_uint24 + #define osal_buffer_uint32 _symrom_osal_buffer_uint32 + #define osal_build_uint16 _symrom_osal_build_uint16 + #define osal_build_uint32 _symrom_osal_build_uint32 + #define osal_CbTimerInit _symrom_osal_CbTimerInit + #define osal_CbTimerProcessEvent _symrom_osal_CbTimerProcessEvent + #define osal_CbTimerStart _symrom_osal_CbTimerStart + #define osal_CbTimerStop _symrom_osal_CbTimerStop + #define osal_CbTimerUpdate _symrom_osal_CbTimerUpdate + #define osal_clear_event _symrom_osal_clear_event + #define osal_ConvertUTCSecs _symrom_osal_ConvertUTCSecs + #define osal_ConvertUTCTime _symrom_osal_ConvertUTCTime + #define osal_get_timeoutEx _symrom_osal_get_timeoutEx + #define osal_getClock _symrom_osal_getClock + #define osal_GetSystemClock _symrom_osal_GetSystemClock + #define osal_init_system _symrom_osal_init_system + #define osal_isbufset _symrom_osal_isbufset + #define osal_mem_alloc _symrom_osal_mem_alloc + #define osal_mem_free _symrom_osal_mem_free + #define osal_mem_init _symrom_osal_mem_init + #define osal_mem_kick _symrom_osal_mem_kick + #define osal_mem_set_heap _symrom_osal_mem_set_heap + #define osal_memcmp _symrom_osal_memcmp + #define osal_memcpy _symrom_osal_memcpy + #define osal_memdup _symrom_osal_memdup + #define osal_memset _symrom_osal_memset + #define osal_msg_allocate _symrom_osal_msg_allocate + #define osal_msg_deallocate _symrom_osal_msg_deallocate + #define osal_msg_dequeue _symrom_osal_msg_dequeue + #define osal_msg_enqueue _symrom_osal_msg_enqueue + #define osal_msg_enqueue_max _symrom_osal_msg_enqueue_max + #define osal_msg_extract _symrom_osal_msg_extract + #define osal_msg_find _symrom_osal_msg_find + #define osal_msg_push _symrom_osal_msg_push + #define osal_msg_push_front _symrom_osal_msg_push_front + #define osal_msg_receive _symrom_osal_msg_receive + #define osal_msg_send _symrom_osal_msg_send + #define osal_next_timeout _symrom_osal_next_timeout + #define osal_pwrmgr_device _symrom_osal_pwrmgr_device + #define osal_pwrmgr_init _symrom_osal_pwrmgr_init + #define osal_pwrmgr_powerconserve _symrom_osal_pwrmgr_powerconserve + #define osal_pwrmgr_task_state _symrom_osal_pwrmgr_task_state + #define osal_qHead _symrom_osal_qHead + #define osal_rand _symrom_osal_rand + #define osal_revmemcpy _symrom_osal_revmemcpy + #define osal_run_system _symrom_osal_run_system + #define osal_self _symrom_osal_self + #define osal_set_event _symrom_osal_set_event + #define osal_setClock _symrom_osal_setClock + #define osal_start_reload_timer _symrom_osal_start_reload_timer + #define osal_start_system _symrom_osal_start_system + #define osal_start_timerEx _symrom_osal_start_timerEx + #define osal_stop_timerEx _symrom_osal_stop_timerEx + #define osal_strlen _symrom_osal_strlen + #define osal_sys_tick _symrom_osal_sys_tick + #define osal_timer_num_active _symrom_osal_timer_num_active + #define OSAL_timeSeconds _symrom_OSAL_timeSeconds + #define osalAddTimer _symrom_osalAddTimer + #define osalDeleteTimer _symrom_osalDeleteTimer + #define osalFindTimer _symrom_osalFindTimer + #define osalTimerInit _symrom_osalTimerInit + #define osalTimerUpdate _symrom_osalTimerUpdate + #define osalTimeUpdate _symrom_osalTimeUpdate + #define osalTimeUpdate1 _symrom_osalTimeUpdate1 + #define ownPublicAddr _symrom_ownPublicAddr + #define p_perStatsByChan _symrom_p_perStatsByChan + #define peerInfo _symrom_peerInfo + #define PendSV_Handler _symrom_PendSV_Handler + #define pHciEvtMask _symrom_pHciEvtMask + #define phy_sec_app_key _symrom_phy_sec_app_key + #define phy_sec_decrypt _symrom_phy_sec_decrypt + #define phy_sec_efuse_lock _symrom_phy_sec_efuse_lock + #define phy_sec_encrypt _symrom_phy_sec_encrypt + #define phy_sec_init _symrom_phy_sec_init + #define phy_sec_key_valid _symrom_phy_sec_key_valid + #define prog_process_data _symrom_prog_process_data + #define prog_uart_command _symrom_prog_uart_command + #define prog_uart_fct_command _symrom_prog_uart_fct_command + #define prog_uart_handle _symrom_prog_uart_handle + #define pwrmgr_attribute _symrom_pwrmgr_attribute + #define read_current_fine_time _symrom_read_current_fine_time + #define read_ll_adv_remainder_time _symrom_read_ll_adv_remainder_time + #define read_LL_remainder_time _symrom_read_LL_remainder_time + #define receive_timeout_flag _symrom_receive_timeout_flag + #define reset_conn_buf _symrom_reset_conn_buf + //#define rf_calibrate _symrom_rf_calibrate + //#define rf_init _symrom_rf_init + //#define rf_phy_ana_cfg _symrom_rf_phy_ana_cfg + //#define rf_phy_bb_cfg _symrom_rf_phy_bb_cfg + //#define rf_phy_change_cfg _symrom_rf_phy_change_cfg + //#define rf_phy_direct_test_ate _symrom_rf_phy_direct_test_ate + //#define rf_phy_get_pktFoot _symrom_rf_phy_get_pktFoot + //#define rf_phy_ini _symrom_rf_phy_ini + //#define rf_phy_set_txPower _symrom_rf_phy_set_txPower + //#define rf_rxDcoc_cfg _symrom_rf_rxDcoc_cfg + //#define rf_tp_cal _symrom_rf_tp_cal + //#define rf_tpCal_cfg _symrom_rf_tpCal_cfg + //#define rf_tpCal_cfg_avg _symrom_rf_tpCal_cfg_avg + //#define rf_tpCal_gen_cap_arrary _symrom_rf_tpCal_gen_cap_arrary + #define rfCounters _symrom_rfCounters + #define rom_board_init _symrom_rom_board_init + #define rtc_clear _symrom_rtc_clear + #define rtc_config_prescale _symrom_rtc_config_prescale + #define rtc_get_counter _symrom_rtc_get_counter + #define rtc_mod_value _symrom_rtc_mod_value + #define rtc_start _symrom_rtc_start + #define rtc_stop _symrom_rtc_stop + #define rxFifoFlowCtrl _symrom_rxFifoFlowCtrl + #define s_prog_time_save _symrom_s_prog_time_save + #define s_prog_timeout _symrom_s_prog_timeout + #define s_rom_debug_level _symrom_s_rom_debug_level + #define s_spif_ctx _symrom_s_spif_ctx + #define SCA _symrom_SCA + #define scanInfo _symrom_scanInfo + #define scanSyncInfo _symrom_scanSyncInfo + #define set_access_address _symrom_set_access_address + #define set_channel _symrom_set_channel + #define set_crc_seed _symrom_set_crc_seed + #define set_gpio_pull_down_ate _symrom_set_gpio_pull_down_ate + #define set_gpio_pull_up_ate _symrom_set_gpio_pull_up_ate + #define set_int _symrom_set_int + #define set_max_length _symrom_set_max_length + #define set_sleep_flag _symrom_set_sleep_flag + #define set_timer _symrom_set_timer + #define set_whiten_seed _symrom_set_whiten_seed + #define setSleepMode _symrom_setSleepMode + #define slave_conn_event_recv_delay _symrom_slave_conn_event_recv_delay + #define sleep_flag _symrom_sleep_flag + #define spif_cmd _symrom_spif_cmd + #define spif_erase_all _symrom_spif_erase_all + #define spif_erase_block64 _symrom_spif_erase_block64 + #define spif_erase_chip _symrom_spif_erase_chip + #define spif_erase_sector _symrom_spif_erase_sector + #define spif_flash_size _symrom_spif_flash_size + #define spif_flash_status_reg_0 _symrom_spif_flash_status_reg_0 + #define spif_flash_status_reg_1 _symrom_spif_flash_status_reg_1 + #define spif_init _symrom_spif_init + #define spif_rddata _symrom_spif_rddata + #define spif_read _symrom_spif_read + #define spif_release_deep_sleep _symrom_spif_release_deep_sleep + #define spif_set_deep_sleep _symrom_spif_set_deep_sleep + #define spif_wrdata _symrom_spif_wrdata + #define spif_write _symrom_spif_write + #define spif_write_protect _symrom_spif_write_protect + #define sram_ret_patch _symrom_sram_ret_patch + #define supportedCmdsTable _symrom_supportedCmdsTable + #define syncInfo _symrom_syncInfo + #define timerHead _symrom_timerHead + #define tx_scanRsp_desc _symrom_tx_scanRsp_desc + #define update_rx_read_ptr _symrom_update_rx_read_ptr + #define update_rx_write_ptr _symrom_update_rx_write_ptr + #define update_tx_read_ptr _symrom_update_tx_read_ptr + #define update_tx_write_ptr _symrom_update_tx_write_ptr + #define verInfo _symrom_verInfo + #define WaitRTCCount _symrom_WaitRTCCount + #define wakeup_init _symrom_wakeup_init + #define wakeup_init0 _symrom_wakeup_init0 + #define wakeupProcess _symrom_wakeupProcess + #define whiten_seed _symrom_whiten_seed + #define zigbee_crc16_gen _symrom_zigbee_crc16_gen + #define WaitUs _symrom_WaitUs + +#endif +#endif + diff --git a/ota_boot/source/ota_boot.h b/ota_boot/source/ota_boot.h new file mode 100644 index 0000000..1d2792f --- /dev/null +++ b/ota_boot/source/ota_boot.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * @file ota_boot.h + * + ******************************************************************************/ + +#ifndef OTA_BOOT_H_ +#define OTA_BOOT_H_ + +/* FLASH */ +#ifndef FLASH_SIZE +#define FLASH_SIZE 0x80000 // 512k (512*1024) +#endif +#define FLASH_MAX_SIZE 0x200000 // 2M (2048*1024) +#ifndef FLASH_SECTOR_SIZE +#define FLASH_SECTOR_SIZE 0x01000 // 4k (4*1024) +#endif +#define FADDR_START_ADDR (0x11000000) +#define FADDR_BOOT_ROM_INFO (FADDR_START_ADDR + 0x02000) // 4k +#define FADDR_OTA_SEC (FADDR_START_ADDR + 0x03000) // 52k +#define FADDR_APP_SEC (FADDR_START_ADDR + 0x10000) // 176k (for 256k Flash) + +#define START_UP_FLAG 0x36594850 // "PHY6" + +#define OTA_MODE_SELECT_REG 0x4000f034 +//#define OTA_MODE_SELECT_REG (AP_AON->RTCCC2) // [0x4000f034] == 0x55 -> OTA +#define BOOT_FLG_OTA 0x55 // перезагрузка в FW Boot для OTA (ожидание соединения 80 сек) +#define BOOT_FLG_FW0 0x33 // перезагрузка в FW Boot + +typedef enum _SYSCLK_SEL +{ + SYS_CLK_RC_32M = 0, + SYS_CLK_DBL_32M = 1, + SYS_CLK_XTAL_16M = 2, + SYS_CLK_DLL_48M = 3, + SYS_CLK_DLL_64M = 4, + SYS_CLK_DLL_96M = 5, + SYS_CLK_8M = 6, + SYS_CLK_4M = 7, + SYS_CLK_NUM = 8, +} sysclk_t; + +extern sysclk_t g_system_clk; + +int _spif_wait_nobusy(uint8_t flg, uint32_t tout_ns); +int spif_write(uint32_t addr, uint8_t* data, uint32_t size); +int spif_write_dma(uint32_t addr, uint8_t* data, uint32_t size); +int spif_read(uint32_t addr, uint8_t* data, uint32_t size); +int spif_read_dma(uint32_t addr, uint8_t* data, uint32_t size); +int spif_erase_sector(unsigned int addr); +int spif_erase_block64(unsigned int addr); +int spif_erase_all(void); +uint8_t spif_flash_status_reg_0(void); +int spif_write_protect(bool en); +void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy); +void spif_rddata(uint8_t* data, uint8_t len); +int spif_config(sysclk_t ref_clk, uint8_t div, uint32_t rd_instr, uint8_t mode_bit, uint8_t QE); + + +#endif /* OTA_BOOT_H_ */ diff --git a/rdwr_phy62x2.py b/rdwr_phy62x2.py index 99e2124..b7898ca 100644 --- a/rdwr_phy62x2.py +++ b/rdwr_phy62x2.py @@ -459,7 +459,7 @@ class phyflasher: def HexfHeader(self, hp, start = DEF_START_RUN_APP_ADDR, raddr = DEF_START_WR_FLASH_ADDR): if len(hp) > 1: hexf = bytearray(b'\xff')*(0x100) - hexf[0:4] = int.to_bytes(len(hp), 4, byteorder='little') + hexf[0:4] = int.to_bytes(len(hp)-1, 4, byteorder='little') hexf[8:12] = int.to_bytes(start, 4, byteorder='little') #sections = 0 faddr_min = MAX_FLASH_SIZE-1 @@ -592,8 +592,6 @@ def main(): print ('Error Flash read Unique ID!') sys.exit(3) print ('Flash Serial Number:', rb.hex()) # Unique ID - - exit(0) if args.operation == 'rc': #filename = "r%08x-%08x.bin" % (addr, length) if args.size == 0: diff --git a/update_boot/BOOT_BTH01_v14.bin b/update_boot/BOOT_BTH01_v14.bin new file mode 100644 index 0000000..9db19d5 Binary files /dev/null and b/update_boot/BOOT_BTH01_v14.bin differ diff --git a/update_boot/BOOT_TH05D_v14.bin b/update_boot/BOOT_TH05D_v14.bin new file mode 100644 index 0000000..7cc5cbc Binary files /dev/null and b/update_boot/BOOT_TH05D_v14.bin differ diff --git a/update_boot/BOOT_TH05F_v14.bin b/update_boot/BOOT_TH05F_v14.bin new file mode 100644 index 0000000..e45d99f Binary files /dev/null and b/update_boot/BOOT_TH05F_v14.bin differ diff --git a/update_boot/BOOT_TH05_v14.bin b/update_boot/BOOT_TH05_v14.bin new file mode 100644 index 0000000..a3bf8cd Binary files /dev/null and b/update_boot/BOOT_TH05_v14.bin differ diff --git a/update_boot/BOOT_THB1_v14.bin b/update_boot/BOOT_THB1_v14.bin new file mode 100644 index 0000000..8396996 Binary files /dev/null and b/update_boot/BOOT_THB1_v14.bin differ diff --git a/update_boot/BOOT_THB2_v14.bin b/update_boot/BOOT_THB2_v14.bin new file mode 100644 index 0000000..0bbfc77 Binary files /dev/null and b/update_boot/BOOT_THB2_v14.bin differ