205 lines
7.2 KiB
C
205 lines
7.2 KiB
C
/**
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****************************************************************************************
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@file global_config.h
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@brief This file contains the definitions of index of global configuration which
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will be configured in APP project.
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$Rev: $
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SDK_LICENSE
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****************************************************************************************
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*/
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#ifndef _GLOBAL_CONFIG_H_
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#define _GLOBAL_CONFIG_H_
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#include "types.h"
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/*******************************************************************************
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software configuration parameters definition
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*/
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#define CONFIG_BASE_ADDR 0x1fff0400
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#define SOFT_PARAMETER_NUM 256
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// parameter index of configuration array
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#define ADV_CHANNEL_INTERVAL 0 // interval between adv channel in the same adv event
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#define SCAN_RSP_DELAY 1 // to adjust scan req -> scan rsp delay
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#define CONN_REQ_TO_SLAVE_DELAY 2 // to calibrate the delay between conn req & 1st slave conn event
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#define SLAVE_CONN_DELAY 3 // to adjust the delay between 2 slave connection events
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#define SLAVE_CONN_DELAY_BEFORE_SYNC 4 // to adjust the delay between 2 slave connection events before 1st anchor is acquired
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#define MAX_SLEEP_TIME 5 // maximum sleep time in us
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#define MIN_SLEEP_TIME 6 // minimum sleep time in us
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#define WAKEUP_ADVANCE 7 // wakeup advance time, to cover HW delay, crystal settle time, sw delay, ... etc.
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#define WAKEUP_DELAY 8 // cycles of SW delay to wait crystal settle
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#define HDC_DIRECT_ADV_INTERVAL 9
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#define LDC_DIRECT_ADV_INTERVAL 10
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#define LL_SWITCH 11 // Link Layer switch, 1 enable, 0 disable
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#define NON_ADV_CHANNEL_INTERVAL 12 // interval between non-adv channel in the same adv event
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#define CLOCK_SETTING 14 // HCLK
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#define LL_HW_BB_DELAY 15
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#define LL_HW_AFE_DELAY 16
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#define LL_HW_PLL_DELAY 17
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#define LL_HW_RTLP_LOOP_TIMEOUT 18
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#define LL_HW_RTLP_1ST_TIMEOUT 19
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#define MIN_TIME_TO_STABLE_32KHZ_XOSC 20
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#define LL_TX_PKTS_PER_CONN_EVT 21
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#define LL_RX_PKTS_PER_CONN_EVT 22
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// ============= A1 ROM metal change add
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#define DIR_ADV_DELAY 23
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#define LL_TX_PWR_TO_REG_BIAS 24
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#define LL_SMART_WINDOW_COEF_ALPHA 25
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#define LL_SMART_WINDOW_TARGET 26
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#define LL_SMART_WINDOW_INCREMENT 27
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#define LL_SMART_WINDOW_LIMIT 28
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#define LL_SMART_WINDOW_ACTIVE_THD 29
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#define LL_SMART_WINDOW_ACTIVE_RANGE 30
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#define LL_SMART_WINDOW_FIRST_WINDOW 31
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#define LL_HW_Tx_TO_RX_INTV 32
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#define LL_HW_Rx_TO_TX_INTV 33
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#define INITIAL_STACK_PTR 34
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#define ALLOW_TO_SLEEP_TICK_RC32K 35
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#define LL_HW_BB_DELAY_ADV 36
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#define LL_HW_AFE_DELAY_ADV 37
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#define LL_HW_PLL_DELAY_ADV 38
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// For scan & master, add 2018-6-15
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#define LL_ADV_TO_SCAN_REQ_DELAY 39
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#define LL_ADV_TO_CONN_REQ_DELAY 40
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#define LL_MOVE_TO_MASTER_DELAY 41
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#define LL_HW_TRLP_LOOP_TIMEOUT 42
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#define LL_CONN_REQ_WIN_SIZE 43
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#define LL_CONN_REQ_WIN_OFFSET 44
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#define LL_MASTER_PROCESS_TARGET 45
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#define LL_MASTER_TIRQ_DELAY 46
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#define LL_HW_BB_DELAY_2MPHY 47
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#define LL_HW_AFE_DELAY_2MPHY 48
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#define LL_HW_PLL_DELAY_2MPHY 49
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#define LL_HW_Tx_TO_RX_INTV_2MPHY 50
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#define LL_HW_Rx_TO_TX_INTV_2MPHY 51
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#define LL_HW_BB_DELAY_500KPHY 52
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#define LL_HW_AFE_DELAY_500KPHY 53
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#define LL_HW_PLL_DELAY_500KPHY 54
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#define LL_HW_Tx_TO_RX_INTV_500KPHY 55
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#define LL_HW_Rx_TO_TX_INTV_500KPHY 56
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#define LL_HW_BB_DELAY_125KPHY 57
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#define LL_HW_AFE_DELAY_125KPHY 58
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#define LL_HW_PLL_DELAY_125KPHY 59
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#define LL_HW_Tx_TO_RX_INTV_125KPHY 60
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#define LL_HW_Rx_TO_TX_INTV_125KPHY 61
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#define LL_HW_TRLP_TO_GAP 62
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#define LL_HW_RTLP_TO_GAP 63
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#define LL_TRX_NUM_ADAPTIVE_CONFIG 64
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#define OSAL_SYS_TICK_WAKEUP_TRIM 65
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// ==== A2 add, for secondary adv/scan
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#define LL_NOCONN_ADV_EST_TIME 70
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#define LL_NOCONN_ADV_MARGIN 71
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#define LL_SEC_SCAN_MARGIN 72
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#define LL_MIN_SCAN_TIME 73
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// Bumblebee ROM code
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#define LL_CONN_ADV_EST_TIME 74
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#define LL_SCANABLE_ADV_EST_TIME 75
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#define MAC_ADDRESS_LOC 80
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// ==== For Extended Adv & Periodic adv
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#define LL_EXT_ADV_INTER_PRI_CHN_INT 81
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#define LL_EXT_ADV_INTER_AUX_CHN_INT 82
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#define LL_EXT_ADV_RSC_POOL_PERIOD 83
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#define LL_EXT_ADV_RSC_POOL_UNIT 84
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#define LL_EXT_ADV_TASK_DURATION 86
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#define LL_PRD_ADV_TASK_DURATION 87
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#define LL_CONN_TASK_DURATION 88
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#define TIMER_ISR_ENTRY_TIME 90 // time from HW timer expiry to ISR entry, unit: us
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#define LL_MULTICONN_MASTER_PREEMP 91
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#define LL_MULTICONN_SLAVE_PREEMP 92
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#define LL_EXT_ADV_INTER_SEC_CHN_INT 93
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#define LL_EXT_ADV_PRI_2_SEC_CHN_INT 94
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#define LL_EXT_ADV_RSC_PERIOD 95
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#define LL_EXT_ADV_RSC_SLOT_DURATION 96
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#define LL_PRD_ADV_RSC_PERIOD 97
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#define LL_PRD_ADV_RSC_SLOT_DURATION 98
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#define LL_EXT_ADV_PROCESS_TARGET 99
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#define LL_PRD_ADV_PROCESS_TARGET 100
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// ==============
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#define RC32_TRACKINK_ALLOW 0x00000001 // enable tracking RC 32KHz clock with 16MHz hclk
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#define SLAVE_LATENCY_ALLOW 0x00000002 // slave latency allow switch
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#define LL_DEBUG_ALLOW 0x00000004 // enable invoke RAM project debug output fucntion
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#define LL_WHITELIST_ALLOW 0x00000008 // enable whitelist filter
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#define LL_RC32K_SEL 0x00000010 // select RC32K RTC, otherwise select crystal 32K RTC
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#define SIMUL_CONN_ADV_ALLOW 0x00000020 // allow send adv in connect state
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#define SIMUL_CONN_SCAN_ALLOW 0x00000040 // allow scan in connect state
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#define CONN_CSA2_ALLOW 0x00000080 // allow using CSA2 in connection state
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#define GAP_DUP_RPT_FILTER_DISALLOW 0x00000100 // duplicate report filter in GAP layer, allow default
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#define ENH_CONN_CMP_EVENT_ALLOW 0x00000200 // allow LL to send enhanced connection complete event.
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// delete 2018-7-17, should use enum H_SYSCLK_SEL
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//enum
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//{
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// CLOCK_16MHZ = 0,
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// CLOCK_32MHZ = 1,
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// CLOCK_48MHZ = 2,
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// CLOCK_64MHZ = 3,
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// CLOCK_96MHZ = 4,
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// CLOCK_32MHZ_DBL=5
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//};
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//extern uint32 global_config[SOFT_PARAMETER_NUM];
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extern uint32* pGlobal_config; // note: app project needn't this variable
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#endif // _GLOBAL_CONFIG_H_
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