607 lines
13 KiB
C
607 lines
13 KiB
C
/************
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pwrmgr.c
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SDK_LICENSE
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**************/
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#include "types.h"
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#include "rom_sym_def.h"
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#include "ll_sleep.h"
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#include "bus_dev.h"
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#include "string.h"
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#include "pwrmgr.h"
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#include "error.h"
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#include "gpio.h"
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#include "log.h"
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#include "clock.h"
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#include "jump_function.h"
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#include "flash.h"
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#include "rf_phy_driver.h"
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#if(CFG_SLEEP_MODE == PWR_MODE_NO_SLEEP)
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static uint8_t mPwrMode = PWR_MODE_NO_SLEEP;
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#elif(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
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static uint8_t mPwrMode = PWR_MODE_SLEEP;
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#elif(CFG_SLEEP_MODE == PWR_MODE_PWROFF_NO_SLEEP)
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static uint8_t mPwrMode = PWR_MODE_PWROFF_NO_SLEEP;
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#else
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#error "CFG_SLEEP_MODE define incorrect"
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#endif
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//#define CFG_FLASH_ENABLE_DEEP_SLEEP
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#ifdef CFG_FLASH_ENABLE_DEEP_SLEEP
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#warning "CONFIG FLASH ENABLE DEEP SLEEP !!!"
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#endif
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#define CFG_SRAM_RETENTION_LOW_CURRENT_LDO_ENABLE
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#ifdef CFG_SRAM_RETENTION_LOW_CURRENT_LDO_ENABLE
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// #warning "ENABLE LOW CURRENT LDO FOR SRAM RETENTION !!!"
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#endif
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//#define CFG_HCLK_DYNAMIC_CHANGE
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#if(CFG_HCLK_DYNAMIC_CHANGE)
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#warning "ENABLE CFG_HCLK_DYNAMIC_CHANGE !!!"
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#endif
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typedef struct _pwrmgr_Context_t
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{
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MODULE_e moudle_id;
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bool lock;
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pwrmgr_Hdl_t sleep_handler;
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pwrmgr_Hdl_t wakeup_handler;
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} pwrmgr_Ctx_t;
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static pwrmgr_Ctx_t mCtx[HAL_PWRMGR_TASK_MAX_NUM];
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static PWRMGR_CFG_BIT s_pwrmgr_cfg;
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static uint32_t s_config_swClk0 = DEF_CLKG_CONFIG_0;
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uint32_t s_config_swClk1 = DEF_CLKG_CONFIG_1;
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#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
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uint32_t s_gpio_wakeup_src_group1,s_gpio_wakeup_src_group2;
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#endif
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// /*
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// osal_idle_task will be call
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// */
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// extern void osal_pwrmgr_powerconserve1( void );
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// __ATTR_SECTION_SRAM__ void osal_idle_task (void)
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// {
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// AP_WDT_FEED;
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// osal_pwrmgr_powerconserve1();
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// }
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int hal_pwrmgr_init(void)
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{
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memset(&mCtx, 0, sizeof(mCtx));
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switch(mPwrMode)
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{
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case PWR_MODE_NO_SLEEP:
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case PWR_MODE_PWROFF_NO_SLEEP:
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disableSleep();
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break;
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case PWR_MODE_SLEEP:
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enableSleep();
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break;
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}
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// /*
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// if wdt enable, set osal idle task to feed wdt before powerconserve
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// */
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// if(AP_WDT_ENABLE_STATE)
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// JUMP_FUNCTION(OSAL_POWER_CONSERVE)=(uint32_t)&osal_idle_task;
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return PPlus_SUCCESS;
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}
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int hal_pwrmgr_clk_gate_config(MODULE_e module)
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{
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if (module < MOD_CP_CPU)
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{
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s_config_swClk0 |= BIT(module);
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}
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else if (module < MOD_PCLK_CACHE)
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{
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s_config_swClk1 |= BIT(module - MOD_CP_CPU);
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}
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return PPlus_SUCCESS;
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}
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bool hal_pwrmgr_is_lock(MODULE_e mod)
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{
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int i;
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int ret = FALSE;
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if(mPwrMode == PWR_MODE_NO_SLEEP || mPwrMode == PWR_MODE_PWROFF_NO_SLEEP )
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{
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return TRUE;
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}
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HAL_ENTER_CRITICAL_SECTION();
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for(i = 0; i< HAL_PWRMGR_TASK_MAX_NUM; i++)
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{
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if(mCtx[i].moudle_id == MOD_NONE)
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break;
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if(mCtx[i].moudle_id == mod)
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{
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if(mCtx[i].lock == TRUE)
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ret = TRUE;
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break;
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}
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}
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HAL_EXIT_CRITICAL_SECTION();
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return ret;
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}
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int hal_pwrmgr_lock(MODULE_e mod)
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{
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int i;
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int ret = PPlus_ERR_NOT_REGISTED;
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if(mPwrMode == PWR_MODE_NO_SLEEP || mPwrMode == PWR_MODE_PWROFF_NO_SLEEP )
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{
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disableSleep();
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return PPlus_SUCCESS;
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}
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HAL_ENTER_CRITICAL_SECTION();
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for(i = 0; i< HAL_PWRMGR_TASK_MAX_NUM; i++)
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{
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if(mCtx[i].moudle_id == MOD_NONE)
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break;
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if(mCtx[i].moudle_id == mod)
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{
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mCtx[i].lock = TRUE;
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disableSleep();
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//LOG("LOCK\n");
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ret = PPlus_SUCCESS;
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break;
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}
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}
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HAL_EXIT_CRITICAL_SECTION();
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return ret;
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}
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int hal_pwrmgr_unlock(MODULE_e mod)
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{
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int i, cnt = 0;
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if(mPwrMode == PWR_MODE_NO_SLEEP || mPwrMode == PWR_MODE_PWROFF_NO_SLEEP )
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{
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disableSleep();
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return PPlus_SUCCESS;
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}
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HAL_ENTER_CRITICAL_SECTION();
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for(i = 0; i< HAL_PWRMGR_TASK_MAX_NUM; i++)
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{
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if(mCtx[i].moudle_id == MOD_NONE)
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break;
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if(mCtx[i].moudle_id == mod)
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{
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mCtx[i].lock = FALSE;
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}
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if(mCtx[i].lock)
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cnt ++;
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}
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if(cnt == 0)
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enableSleep();
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else
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disableSleep();
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HAL_EXIT_CRITICAL_SECTION();
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//LOG("sleep mode:%d\n", isSleepAllow());
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return PPlus_SUCCESS;
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}
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int hal_pwrmgr_register(MODULE_e mod, pwrmgr_Hdl_t sleepHandle, pwrmgr_Hdl_t wakeupHandle)
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{
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int i;
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pwrmgr_Ctx_t* pctx = NULL;
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for(i = 0; i< HAL_PWRMGR_TASK_MAX_NUM; i++)
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{
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if(mCtx[i].moudle_id == mod)
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return PPlus_ERR_INVALID_STATE;
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if(mCtx[i].moudle_id == MOD_NONE)
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{
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pctx = &mCtx[i];
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s_pwrmgr_cfg.moudle_num++;
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break;
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}
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}
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if(pctx == NULL)
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return PPlus_ERR_NO_MEM;
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pctx->lock = FALSE;
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pctx->moudle_id = mod;
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pctx->sleep_handler = sleepHandle;
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pctx->wakeup_handler = wakeupHandle;
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return PPlus_SUCCESS;
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}
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int hal_pwrmgr_unregister(MODULE_e mod)
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{
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int i;
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pwrmgr_Ctx_t* pctx = NULL;
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for(i = 0; i< HAL_PWRMGR_TASK_MAX_NUM; i++)
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{
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if(mCtx[i].moudle_id == mod)
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{
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s_pwrmgr_cfg.moudle_num--;
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pctx = &mCtx[i];
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break;
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}
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if(mCtx[i].moudle_id == MOD_NONE)
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{
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return PPlus_ERR_NOT_REGISTED;
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}
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}
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if(pctx == NULL)
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return PPlus_ERR_NOT_REGISTED;
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HAL_ENTER_CRITICAL_SECTION();
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memcpy(pctx, pctx+1, sizeof(pwrmgr_Ctx_t)*(HAL_PWRMGR_TASK_MAX_NUM-i-1));
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HAL_EXIT_CRITICAL_SECTION();
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return PPlus_SUCCESS;
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}
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void clk_change_mod_restore(void)
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{
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int i;
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for(i = 0; i< HAL_PWRMGR_TASK_MAX_NUM; i++)
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{
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if(mCtx[i].moudle_id == MOD_NONE)
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{
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return ;
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}
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if(mCtx[i].wakeup_handler)
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mCtx[i].wakeup_handler();
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}
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return;
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}
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#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
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void peripheral_interrupt_restore_default(void)
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{
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NVIC_SetPriority((IRQn_Type)KSCAN_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)WDT_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)UART0_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)UART1_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)I2C0_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)I2C1_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)SPI0_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)SPI1_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)GPIO_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)DMAC_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)TIM5_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)TIM6_IRQn, IRQ_PRIO_HAL);
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NVIC_SetPriority((IRQn_Type)ADCC_IRQn, IRQ_PRIO_HAL);
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}
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int __attribute__((used)) hal_pwrmgr_wakeup_process(void)
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{
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int i;
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#ifdef CFG_FLASH_ENABLE_DEEP_SLEEP
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extern void spif_release_deep_sleep(void);
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spif_release_deep_sleep();
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WaitRTCCount(8);
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#endif
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AP_PCR->SW_CLK = s_config_swClk0;
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AP_PCR->SW_CLK1 = s_config_swClk1|0x01;//force set M0 CPU
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s_gpio_wakeup_src_group1 = AP_AON->GPIO_WAKEUP_SRC[0];
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s_gpio_wakeup_src_group2 = AP_AON->GPIO_WAKEUP_SRC[1];
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//restore BB TIMER IRQ_PRIO
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NVIC_SetPriority((IRQn_Type)BB_IRQn, IRQ_PRIO_REALTIME);
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NVIC_SetPriority((IRQn_Type)TIM1_IRQn, IRQ_PRIO_HIGH); //ll_EVT
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NVIC_SetPriority((IRQn_Type)TIM2_IRQn, IRQ_PRIO_HIGH); //OSAL_TICK
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NVIC_SetPriority((IRQn_Type)TIM4_IRQn, IRQ_PRIO_HIGH); //LL_EXA_ADV
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//peripheral_interrupt_restore_default();
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for(i = 0; i< s_pwrmgr_cfg.moudle_num; i++)
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{
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if(mCtx[i].moudle_id == MOD_NONE)
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{
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return PPlus_ERR_NOT_REGISTED;
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}
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if(mCtx[i].wakeup_handler)
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mCtx[i].wakeup_handler();
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}
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return PPlus_SUCCESS;
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}
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int __attribute__((used)) hal_pwrmgr_sleep_process(void)
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{
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int i;
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//20181013 ZQ :
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hal_pwrmgr_RAM_retention_set();
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//LOG("Sleep\n");
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for(i = s_pwrmgr_cfg.moudle_num-1; i >= 0; i--)
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{
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if(mCtx[i].moudle_id == MOD_NONE)
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{
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return PPlus_ERR_NOT_REGISTED;
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}
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if(mCtx[i].sleep_handler)
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mCtx[i].sleep_handler();
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}
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#if(CFG_HCLK_DYNAMIC_CHANGE==1)
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/*
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hclk will change to SYS_CLK_XTAL_16M in next wakeup_process
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*/
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hal_system_clock_change_req(SYS_CLK_XTAL_16M);
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#endif
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#ifdef CFG_FLASH_ENABLE_DEEP_SLEEP
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extern void spif_set_deep_sleep(void);
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spif_set_deep_sleep();
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#endif
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return PPlus_SUCCESS;
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}
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#else
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int __attribute__((used)) hal_pwrmgr_wakeup_process(void)
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{
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return PPlus_SUCCESS;
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}
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int __attribute__((used)) hal_pwrmgr_sleep_process(void)
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{
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return PPlus_SUCCESS;
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}
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#endif
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/**************************************************************************************
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@fn hal_pwrmgr_RAM_retention
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@brief This function process for enable retention sram
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input parameters
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@param uint32_t sram: sram bit map
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output parameters
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@param None.
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@return refer error.h.
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**************************************************************************************/
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int hal_pwrmgr_RAM_retention(uint32_t sram)
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{
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if(sram & 0xffffffe0)
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{
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s_pwrmgr_cfg.sramRet_config = 0x00;
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return PPlus_ERR_INVALID_PARAM;
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}
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s_pwrmgr_cfg.sramRet_config = sram;
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return PPlus_SUCCESS;
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}
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int hal_pwrmgr_RAM_retention_clr(void)
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{
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subWriteReg(0x4000f01c,21,17,0);
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return PPlus_SUCCESS;
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}
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int hal_pwrmgr_RAM_retention_set(void)
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{
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subWriteReg(0x4000f01c,21,17,s_pwrmgr_cfg.sramRet_config);
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return PPlus_SUCCESS;
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}
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int hal_pwrmgr_LowCurrentLdo_enable(void)
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{
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#ifdef CFG_SRAM_RETENTION_LOW_CURRENT_LDO_ENABLE
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uint32_t retention_flag;
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hal_flash_read(0x1100181c,(uint8_t*)&retention_flag,4);
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if(retention_flag == 0xffffffff)
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{
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subWriteReg(0x4000f014,26,26, 1);
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}
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return PPlus_SUCCESS;
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#else
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subWriteReg(0x4000f014,26,26, 0);
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return PPlus_ERR_FORBIDDEN;
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#endif
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}
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int hal_pwrmgr_LowCurrentLdo_disable(void)
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{
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subWriteReg(0x4000f014,26,26, 0);
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return PPlus_SUCCESS;
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}
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extern void gpio_wakeup_set(gpio_pin_e pin, gpio_polarity_e type);
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extern void gpio_pull_set(gpio_pin_e pin, gpio_pupd_e type);
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void hal_pwrmgr_poweroff(pwroff_cfg_t* pcfg, uint8_t wakeup_pin_num)
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{
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HAL_ENTER_CRITICAL_SECTION();
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subWriteReg(0x4000f01c,6,6,0x00); //disable software control
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//(void)(wakeup_pin_num);
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for(uint8_t i = 0; i < wakeup_pin_num; i++ )
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{
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if(pcfg[i].type==POL_FALLING)
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gpio_pull_set(pcfg[i].pin,GPIO_PULL_UP_S);
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else
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gpio_pull_set(pcfg[i].pin,GPIO_PULL_DOWN);
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gpio_wakeup_set(pcfg[i].pin, pcfg[i].type);
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}
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/**
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config reset casue as RSTC_OFF_MODE
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reset path walkaround dwc
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*/
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AON_CLEAR_XTAL_TRACKING_AND_CALIB;
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AP_AON->SLEEP_R[0] = 2;
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enter_sleep_off_mode(SYSTEM_OFF_MODE);
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while(1);
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}
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__ATTR_SECTION_SRAM__ void hal_pwrmgr_enter_sleep_rtc_reset(uint32_t sleepRtcTick)
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{
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HAL_ENTER_CRITICAL_SECTION();
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subWriteReg(0x4000f01c,6,6,0x00); //disable software control
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config_RTC(sleepRtcTick);
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// clear sram retention
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hal_pwrmgr_RAM_retention_clr();
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/**
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config reset casue as RSTC_WARM_NDWC
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reset path walkaround dwc
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*/
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AON_CLEAR_XTAL_TRACKING_AND_CALIB;
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AP_AON->SLEEP_R[0]=4;
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enter_sleep_off_mode(SYSTEM_SLEEP_MODE);
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while(1) {};
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}
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#define STANDBY_WAIT_MS(a) WaitRTCCount((a)<<5) // 32us * 32 around 1ms
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pwroff_cfg_t s_pwroff_cfg[WAKEUP_PIN_MAX];
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__attribute__((used)) uint8 pwroff_register_number=0;
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__attribute__((section("_section_standby_code_"))) void wakeupProcess_standby(void)
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{
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subWriteReg(0x4000f014,29,27,0x07);
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STANDBY_WAIT_MS(5);
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#ifdef CFG_FLASH_ENABLE_DEEP_SLEEP
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extern void spif_release_deep_sleep(void);
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spif_release_deep_sleep();
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STANDBY_WAIT_MS(15);
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#endif
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uint32_t volatile cnt=0;
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uint8_t volatile find_flag=0;
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uint8 pin_n=0;
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extern bool gpio_read(gpio_pin_e pin);
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for(pin_n=0; pin_n<pwroff_register_number; pin_n++)
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|
{
|
|
if((s_pwroff_cfg[pin_n].pin == P2) || (s_pwroff_cfg[pin_n].pin == P3))
|
|
{
|
|
hal_gpio_pin2pin3_control(s_pwroff_cfg[pin_n].pin,1);
|
|
}
|
|
}
|
|
|
|
for(pin_n=0; pin_n<pwroff_register_number; pin_n++)
|
|
{
|
|
if(gpio_read(s_pwroff_cfg[pin_n].pin)==s_pwroff_cfg[pin_n].type)
|
|
{
|
|
find_flag=1;
|
|
break;
|
|
}
|
|
}
|
|
|
|
while(1)
|
|
{
|
|
if(gpio_read(s_pwroff_cfg[pin_n].pin)==s_pwroff_cfg[pin_n].type&&find_flag==1)
|
|
{
|
|
cnt++;
|
|
STANDBY_WAIT_MS(32);
|
|
|
|
if(cnt>(s_pwroff_cfg[pin_n].on_time>>5))
|
|
{
|
|
write_reg(0x4000f030, 0x01);
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
hal_pwrmgr_enter_standby(&s_pwroff_cfg[0],pwroff_register_number);
|
|
}
|
|
|
|
set_sleep_flag(0);
|
|
AP_AON->SLEEP_R[0] = 4;
|
|
AON_CLEAR_XTAL_TRACKING_AND_CALIB;
|
|
HAL_ENTER_CRITICAL_SECTION();
|
|
AP_PCR->SW_RESET1 = 0;
|
|
|
|
while(1);
|
|
}
|
|
extern void gpio_wakeup_set(gpio_pin_e pin, gpio_polarity_e type);
|
|
extern void gpio_pull_set(gpio_pin_e pin, gpio_pupd_e type);
|
|
__attribute__((section("_section_standby_code_"))) void hal_pwrmgr_enter_standby(pwroff_cfg_t* pcfg,uint8_t wakeup_pin_num)
|
|
{
|
|
HAL_ENTER_CRITICAL_SECTION();
|
|
subWriteReg(0x4000f01c,6,6,0x00); //disable software control
|
|
uint8_t i = 0;
|
|
|
|
if(wakeup_pin_num>WAKEUP_PIN_MAX)
|
|
{
|
|
wakeup_pin_num=WAKEUP_PIN_MAX;
|
|
}
|
|
|
|
pwroff_register_number=wakeup_pin_num;
|
|
|
|
for(i = 0; i < wakeup_pin_num; i++)
|
|
{
|
|
if(pcfg[i].type==POL_FALLING)
|
|
gpio_pull_set(pcfg[i].pin,GPIO_PULL_UP_S);
|
|
else
|
|
gpio_pull_set(pcfg[i].pin,GPIO_PULL_DOWN);
|
|
|
|
gpio_wakeup_set(pcfg[i].pin, pcfg[i].type);
|
|
osal_memcpy(&s_pwroff_cfg[i],&(pcfg[i]),sizeof(pwroff_cfg_t));
|
|
}
|
|
|
|
JUMP_FUNCTION(WAKEUP_PROCESS)= (uint32_t)&wakeupProcess_standby;
|
|
#ifdef CFG_FLASH_ENABLE_DEEP_SLEEP
|
|
extern void spif_set_deep_sleep(void);
|
|
spif_set_deep_sleep();
|
|
WaitRTCCount(50);
|
|
#endif
|
|
subWriteReg(0x4000f014,29,27,0);
|
|
set_sleep_flag(1);
|
|
AP_AON->SLEEP_R[0] = 2;
|
|
subWriteReg(0x4000f01c,21,17,RET_SRAM0);
|
|
enter_sleep_off_mode(SYSTEM_SLEEP_MODE);
|
|
|
|
while(1);
|
|
}
|
|
|
|
__ATTR_SECTION_XIP__ int hal_pwrmgr_get_module_lock_status(void)
|
|
{
|
|
if (mPwrMode == PWR_MODE_NO_SLEEP || mPwrMode == PWR_MODE_PWROFF_NO_SLEEP)
|
|
{
|
|
disableSleep();
|
|
return FALSE;
|
|
}
|
|
|
|
for (int i = 0; i < HAL_PWRMGR_TASK_MAX_NUM; i++)
|
|
{
|
|
if (mCtx[i].lock == TRUE)
|
|
{
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
return TRUE;
|
|
}
|