685 lines
16 KiB
C
685 lines
16 KiB
C
/*******************************************************************************
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@file gpio.c
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@brief Contains all functions support for gpio and iomux driver
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@version 0.0
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@date 19. Oct. 2017
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@author qing.han
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SDK_LICENSE
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*******************************************************************************/
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#include "types.h"
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#include "string.h"
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#include "mcu.h"
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#include "clock.h"
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#include "gpio.h"
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#include "pwrmgr.h"
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#include "error.h"
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#include "jump_function.h"
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#include "log.h"
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#include "global_config.h"
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extern uint32_t s_gpio_wakeup_src_group1,s_gpio_wakeup_src_group2;
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enum
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{
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GPIO_PIN_ASSI_NONE = 0,
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GPIO_PIN_ASSI_OUT,
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GPIO_PIN_ASSI_IN,
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};
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typedef struct
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{
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bool enable;
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uint8_t pin_state;
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gpioin_Hdl_t posedgeHdl;
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gpioin_Hdl_t negedgeHdl;
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} gpioin_Ctx_t;
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typedef struct
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{
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bool state;
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uint8_t pin_assignments[NUMBER_OF_PINS];
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uint32_t pin_retention_status;
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gpioin_Ctx_t irq_ctx[NUMBER_OF_PINS];
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} gpio_Ctx_t;
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typedef struct
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{
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uint8_t reg_i;
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uint8_t bit_h;
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uint8_t bit_l;
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} PULL_TypeDef;
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static gpio_Ctx_t m_gpioCtx =
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{
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.state = FALSE,
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.pin_assignments = {0,},
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.pin_retention_status = 0
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};
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const uint8_t c_gpio_index[GPIO_NUM] = {0,1,2,3,7,9,10,11,14,15,16,17,18,20,23,24,25,26,27,31,32,33,34};
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const PULL_TypeDef c_gpio_pull[GPIO_NUM]=
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{
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{0,2,1}, //p0
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{0,5,4}, //p1
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{0,8,7}, //p2
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{0,11,10},//p3
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{0,23,22},//p7
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{0,29,28},//p9
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{1,2,1}, //p10
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{1,5,4}, //p11
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{1,14,13},//p14
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{1,17,16},//p15
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{1,20,19},//p16
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{1,23,22},//p17
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{1,26,25},//p18
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{2,2,1}, //p20
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{2,11,10},//p23
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{2,14,13},//p24
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{2,17,16},//p25
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{2,20,19},//p26
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{2,23,22},//p27
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{3,5,4}, //p31
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{3,8,7}, //p32
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{3,11,10},//p33
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{3,14,13},//p34
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};
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const signed char retention_reg[GPIO_NUM][2]=
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{
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{0,13},//p0
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{0,14},//p1
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{0,16},//p2
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{0,17},//p3
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{0,19},//p7
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{0,20},//p9
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{1,7},//p10
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{1,8},//p11
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{1,10},//p14
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{1,11},//p15
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{1,28},//p16
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{1,29},//p17
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{2,4},//p18
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{2,5},//p20
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{2,7},//p23
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{2,8},//p24
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{2,25},//p25
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{2,26},//p26
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{2,28},//p27
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{2,29},//p31
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{3,1},//p32
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{3,2},//p33
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{3,23},//p34
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};
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static int hal_gpio_interrupt_disable(gpio_pin_e pin)
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{
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subWriteReg(&(AP_GPIO->intmask),pin,pin,1);
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subWriteReg(&(AP_GPIO->inten),pin,pin,0);
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return PPlus_SUCCESS;
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}
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void hal_gpio_write(gpio_pin_e pin, uint8_t en)
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{
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// hal_gpio_pin_init(pin,GPIO_OUTPUT);
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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if(en)
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AP_GPIO->swporta_dr |= BIT(pin);
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else
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AP_GPIO->swporta_dr &= ~BIT(pin);
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hal_gpio_pin_init(pin,GPIO_OUTPUT);
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}
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void hal_gpio_fast_write(gpio_pin_e pin, uint8_t en)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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if(en)
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AP_GPIO->swporta_dr |= BIT(pin);
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else
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AP_GPIO->swporta_dr &= ~BIT(pin);
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}
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bool hal_gpio_read(gpio_pin_e pin)
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{
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uint32_t r;
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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if(AP_GPIO->swporta_ddr & BIT(pin))
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r = AP_GPIO->swporta_dr;
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else
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r = AP_GPIO->ext_porta;
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return (int)((r>> pin) &1);
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}
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void hal_gpio_fmux(gpio_pin_e pin, bit_action_e value)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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if(value)
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{
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// if((pin == P2) || (pin == P3))
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// hal_gpio_pin2pin3_control(pin,1);
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AP_IOMUX->full_mux0_en |= BIT(pin);
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}
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else
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AP_IOMUX->full_mux0_en &= ~BIT(pin);
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}
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void hal_gpio_fmux_set(gpio_pin_e pin, gpio_fmux_e type)
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{
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uint8_t h = 0,l = 0;
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uint32_t reg_index;
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uint32_t bit_index;
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if(pin != GPIO_DUMMY)
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{
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reg_index = pin >> 2;
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bit_index = pin & 0x03;
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l = 8 * bit_index;
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h = l + 5;
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hal_gpioin_disable(pin);
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subWriteReg(&(AP_IOMUX->gpio_sel[reg_index]),h,l,type);
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hal_gpio_fmux(pin, Bit_ENABLE);
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}
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}
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int hal_gpio_pin_init(gpio_pin_e pin, gpio_dir_t type)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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// if((m_gpioCtx.pin_assignments[pin] == GPIO_PIN_ASSI_OUT) &&
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// (m_gpioCtx.pin_retention_status & BIT(pin)) && (type == GPIO_INPUT))
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// return PPlus_ERR_INVALID_PARAM;
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hal_gpio_fmux(pin,Bit_DISABLE);
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if((pin == P2) || (pin == P3))
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hal_gpio_pin2pin3_control(pin,1);
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hal_gpio_cfg_analog_io(pin,Bit_DISABLE);
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if(type == GPIO_OUTPUT)
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{
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AP_GPIO->swporta_ddr |= BIT(pin);
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m_gpioCtx.pin_assignments[pin] = GPIO_PIN_ASSI_OUT;
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}
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else
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{
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AP_GPIO->swporta_ddr &= ~BIT(pin);
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m_gpioCtx.pin_assignments[pin] = GPIO_PIN_ASSI_IN;
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m_gpioCtx.pin_retention_status &= ~BIT(pin);
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}
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return PPlus_SUCCESS;
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}
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static void hal_gpio_wakeup_control(gpio_pin_e pin, bit_action_e value)
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{
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if(pin < P32)
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{
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if (value)
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AP_AON->REG_S9 |= BIT(c_gpio_index[pin]);
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else
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AP_AON->REG_S9 &= ~BIT(c_gpio_index[pin]);
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}
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else
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{
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if (value)
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AP_AON->REG_S10 |= BIT(c_gpio_index[pin] - 32);
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else
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AP_AON->REG_S10 &= ~BIT(c_gpio_index[pin] - 32);
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}
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}
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void hal_gpio_ds_control(gpio_pin_e pin, bit_action_e value)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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if(value)
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AP_IOMUX->pad_ps0 |= BIT(pin);
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else
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AP_IOMUX->pad_ps0 &= ~BIT(pin);
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}
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int hal_gpioretention_unregister(gpio_pin_e pin)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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if(m_gpioCtx.pin_assignments[pin] != GPIO_PIN_ASSI_OUT)
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return PPlus_ERR_INVALID_PARAM;
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m_gpioCtx.pin_retention_status &= ~BIT(pin);
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return PPlus_SUCCESS;
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}
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int hal_gpioin_unregister(gpio_pin_e pin)
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{
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gpioin_Ctx_t* p_irq_ctx = &(m_gpioCtx.irq_ctx[0]);
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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hal_gpioin_disable(pin);
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p_irq_ctx[pin].negedgeHdl = NULL;
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p_irq_ctx[pin].posedgeHdl = NULL;
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return PPlus_SUCCESS;
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}
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int hal_gpio_cfg_analog_io(gpio_pin_e pin, bit_action_e value)
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{
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if((pin < P11) || (pin > P25))
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return PPlus_ERR_INVALID_PARAM;
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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if(value)
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{
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hal_gpio_pull_set(pin,GPIO_FLOATING);
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AP_IOMUX->Analog_IO_en |= BIT(pin - P11);
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}
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else
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{
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AP_IOMUX->Analog_IO_en &= ~BIT(pin - P11);
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}
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return PPlus_SUCCESS;
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}
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void hal_gpio_pull_set(gpio_pin_e pin, gpio_pupd_e type)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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uint8_t i = c_gpio_pull[pin].reg_i;
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uint8_t h = c_gpio_pull[pin].bit_h;
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uint8_t l = c_gpio_pull[pin].bit_l;
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if(pin < P31)
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subWriteReg(&(AP_AON->IOCTL[i]),h,l,type);
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else
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subWriteReg(&(AP_AON->PMCTL0),h,l,type);
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}
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void hal_gpio_wakeup_set(gpio_pin_e pin, gpio_polarity_e type)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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uint8_t i = c_gpio_pull[pin].reg_i;
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uint8_t p = c_gpio_pull[pin].bit_l-1;
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if (m_gpioCtx.pin_assignments[pin] != GPIO_PIN_ASSI_IN)
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return;
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AP_GPIO->inttype_level |= BIT(pin);//edge sensitive
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if(pin < P31)
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{
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if(POL_FALLING == type)
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AP_AON->IOCTL[i] |= BIT(p);
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else
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AP_AON->IOCTL[i] &= ~BIT(p);
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}
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else
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{
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if(POL_FALLING == type)
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AP_AON->PMCTL0 |= BIT(p);
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else
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AP_AON->PMCTL0 &= ~BIT(p);
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}
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hal_gpio_wakeup_control(pin,Bit_ENABLE);//enable wakeup function
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}
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void hal_gpio_pin2pin3_control(gpio_pin_e pin, uint8_t en)//0:sw,1:other func
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{
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if(en)
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AP_IOMUX->gpio_pad_en |= BIT(pin-2);
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else
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AP_IOMUX->gpio_pad_en &= ~BIT(pin-2);
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}
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#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
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static void hal_gpio_retention_enable(gpio_pin_e pin,uint8_t en)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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if(en)
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{
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if((pin == P32)||(pin == P33)||(pin == P34))
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{
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AP_AON->PMCTL0 |= BIT(retention_reg[pin][1]);
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}
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else
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{
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AP_AON->IOCTL[retention_reg[pin][0]] |= BIT(retention_reg[pin][1]);
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}
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}
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else
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{
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if((pin == P32)||(pin == P33)||(pin == P34))
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{
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AP_AON->PMCTL0 &= ~BIT(retention_reg[pin][1]);
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}
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else
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{
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AP_AON->IOCTL[retention_reg[pin][0]] &= ~BIT(retention_reg[pin][1]);
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}
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}
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}
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#endif
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int hal_gpioin_disable(gpio_pin_e pin)
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{
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gpioin_Ctx_t* p_irq_ctx = &(m_gpioCtx.irq_ctx[0]);
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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p_irq_ctx[pin].enable = FALSE;
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m_gpioCtx.pin_assignments[pin] = GPIO_PIN_ASSI_NONE;
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hal_gpio_pin_init(pin, GPIO_INPUT);
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return hal_gpio_interrupt_disable(pin);
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}
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static int hal_gpio_interrupt_enable(gpio_pin_e pin, gpio_polarity_e type)
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{
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uint32_t gpio_tmp;
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if (pin > (NUMBER_OF_PINS - 1))
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return PPlus_ERR_NOT_SUPPORTED;
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gpio_tmp = AP_GPIO->inttype_level;
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gpio_tmp |= (1 << pin); //edge sensitive
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AP_GPIO->inttype_level = gpio_tmp;
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gpio_tmp = AP_GPIO->intmask;
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gpio_tmp &= ~(1 << pin); //unmask interrupt
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AP_GPIO->intmask = gpio_tmp;
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gpio_tmp = AP_GPIO->int_polarity;
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if (type == POL_RISING )
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gpio_tmp |= (1 << pin);
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else
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gpio_tmp &= ~(1 << pin);
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AP_GPIO->int_polarity = gpio_tmp;
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gpio_tmp = AP_GPIO->inten;
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gpio_tmp |= (1 << pin); //enable interrupt
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AP_GPIO->inten = gpio_tmp;
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return PPlus_SUCCESS;
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}
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static void hal_gpioin_event_pin(gpio_pin_e pin, gpio_polarity_e type)
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{
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gpioin_Ctx_t* p_irq_ctx = &(m_gpioCtx.irq_ctx[0]);
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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if (p_irq_ctx[pin].posedgeHdl && (type == POL_RISING ))
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{
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p_irq_ctx[pin].posedgeHdl(pin,POL_RISING );//LOG("POS\n");
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}
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else if (p_irq_ctx[pin].negedgeHdl && (type == POL_FALLING))
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{
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p_irq_ctx[pin].negedgeHdl(pin,POL_FALLING);//LOG("NEG\n");
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}
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}
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#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
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static void hal_gpioin_wakeup_trigger(gpio_pin_e pin)
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{
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if (pin > (NUMBER_OF_PINS - 1))
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return;
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uint8_t pin_state = (uint8_t)hal_gpio_read(pin);
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gpio_polarity_e type = pin_state ? POL_RISING : POL_FALLING;
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if (m_gpioCtx.irq_ctx[pin].pin_state != pin_state)
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hal_gpioin_event_pin(pin, type);
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}
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#endif
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static void hal_gpioin_event(uint32 int_status, uint32 polarity)
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{
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int i;
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gpioin_Ctx_t* p_irq_ctx = &(m_gpioCtx.irq_ctx[0]);
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// LOG("GI:%x,%x\n",int_status,polarity);
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for (i = 0; i < NUMBER_OF_PINS; i++)
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{
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if (int_status & (1ul << i))
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{
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gpio_polarity_e type = (polarity & BIT(i)) ? POL_RISING : POL_FALLING;
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hal_gpioin_event_pin((gpio_pin_e)i, type);
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//reconfig interrupt
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if (p_irq_ctx[i].posedgeHdl && p_irq_ctx[i].negedgeHdl) //both raise and fall
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{
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type = (type == POL_RISING) ? POL_FALLING : POL_RISING ;
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hal_gpio_interrupt_enable((gpio_pin_e)i, type);
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}
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else if (p_irq_ctx[i].posedgeHdl) //raise
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{
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hal_gpio_interrupt_enable((gpio_pin_e)i, POL_RISING );
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}
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else if (p_irq_ctx[i].negedgeHdl) //fall
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{
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hal_gpio_interrupt_enable((gpio_pin_e)i, POL_FALLING);
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}
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}
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}
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}
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#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
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static void hal_gpio_sleep_handler(void)
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{
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int i;
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gpio_polarity_e pol;
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for (i = 0; i < NUMBER_OF_PINS; i++)
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{
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//config wakeup
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if ((m_gpioCtx.pin_assignments[i] == GPIO_PIN_ASSI_OUT) && (m_gpioCtx.pin_retention_status & BIT(i)))
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{
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hal_gpio_retention_enable((gpio_pin_e)i,Bit_ENABLE);
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}
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if (m_gpioCtx.pin_assignments[i] == GPIO_PIN_ASSI_IN)
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{
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#ifdef XOSC_PIN_ALLOW
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if((i==P16)||(i==P17))
|
|
{
|
|
hal_gpio_cfg_analog_io((gpio_pin_e)i,Bit_DISABLE);
|
|
subWriteReg(&(AP_AON->PMCTL2_0),6,6,0x01);
|
|
WaitUs(50);
|
|
pol = hal_gpio_read((gpio_pin_e)i) ? POL_FALLING : POL_RISING ;
|
|
subWriteReg(&(AP_AON->PMCTL2_0),6,6,0x00);
|
|
}
|
|
else
|
|
#endif
|
|
{
|
|
pol = hal_gpio_read((gpio_pin_e)i) ? POL_FALLING : POL_RISING ;
|
|
}
|
|
|
|
hal_gpio_wakeup_set((gpio_pin_e)i, pol);
|
|
m_gpioCtx.irq_ctx[i].pin_state = hal_gpio_read((gpio_pin_e)i);
|
|
}
|
|
}
|
|
}
|
|
|
|
static void hal_gpio_wakeup_handler(void)
|
|
{
|
|
int i;
|
|
NVIC_SetPriority(GPIO_IRQn, IRQ_PRIO_HAL);
|
|
NVIC_EnableIRQ(GPIO_IRQn);
|
|
#ifdef XOSC_PIN_ALLOW
|
|
|
|
if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL)
|
|
{
|
|
subWriteReg(0x4000f01c,16,7,0x3fb); //software control 32k_clk
|
|
subWriteReg(0x4000f01c,6,6,0x01); //enable software control
|
|
}
|
|
else
|
|
{
|
|
subWriteReg(0x4000f01c,9,8,0x03); //software control 32k_clk
|
|
subWriteReg(0x4000f01c,6,6,0x00); //disable software control
|
|
}
|
|
|
|
#endif
|
|
|
|
for (i = 0; i < NUMBER_OF_PINS; i++)
|
|
{
|
|
if(m_gpioCtx.pin_assignments[i] != GPIO_PIN_ASSI_NONE)
|
|
{
|
|
if((i == P2) || (i == P3))
|
|
hal_gpio_pin2pin3_control((gpio_pin_e)i,1);
|
|
|
|
#ifdef XOSC_PIN_ALLOW
|
|
|
|
if((i == P16) ||(i == P17))
|
|
hal_gpio_cfg_analog_io((gpio_pin_e)i, Bit_DISABLE);
|
|
|
|
#endif
|
|
}
|
|
|
|
if ((m_gpioCtx.pin_assignments[i] == GPIO_PIN_ASSI_OUT) && (m_gpioCtx.pin_retention_status & BIT(i)))
|
|
{
|
|
bool pol = hal_gpio_read((gpio_pin_e)i);
|
|
hal_gpio_write((gpio_pin_e)i,pol);
|
|
hal_gpio_retention_enable((gpio_pin_e)i,Bit_DISABLE);
|
|
}
|
|
|
|
if (m_gpioCtx.irq_ctx[i].enable)
|
|
{
|
|
hal_gpioin_enable((gpio_pin_e)i); //resume gpio irq
|
|
hal_gpioin_wakeup_trigger((gpio_pin_e)i);//trigger gpio irq manually
|
|
}
|
|
}
|
|
}
|
|
#endif
|
|
|
|
|
|
void __attribute__((used)) hal_GPIO_IRQHandler(void)
|
|
{
|
|
uint32 polarity = AP_GPIO->int_polarity;
|
|
uint32 st = AP_GPIO->int_status;
|
|
AP_GPIO->porta_eoi = st;//clear interrupt
|
|
hal_gpioin_event(st, polarity);
|
|
}
|
|
|
|
int hal_gpioin_enable(gpio_pin_e pin)
|
|
{
|
|
gpioin_Ctx_t* p_irq_ctx = &(m_gpioCtx.irq_ctx[0]);
|
|
gpio_polarity_e type = POL_FALLING;
|
|
uint32 pinVal = 0;
|
|
|
|
if (pin > (NUMBER_OF_PINS - 1))
|
|
return PPlus_ERR_NOT_SUPPORTED;
|
|
|
|
if (p_irq_ctx[pin].posedgeHdl == NULL && p_irq_ctx[pin].negedgeHdl == NULL)
|
|
return PPlus_ERR_NOT_REGISTED;
|
|
|
|
m_gpioCtx.pin_assignments[pin] = GPIO_PIN_ASSI_IN;
|
|
p_irq_ctx[pin].enable = TRUE;
|
|
hal_gpio_pin_init(pin, GPIO_INPUT);
|
|
|
|
//hal_gpio_pull_set(pin, PULL_DOWN); //??need disccuss
|
|
if (p_irq_ctx[pin].posedgeHdl && p_irq_ctx[pin].negedgeHdl) //both raise and fall
|
|
{
|
|
pinVal = hal_gpio_read(pin);
|
|
type = pinVal ? POL_FALLING : POL_RISING ;
|
|
}
|
|
else if (p_irq_ctx[pin].posedgeHdl) //raise
|
|
{
|
|
type = POL_RISING ;
|
|
}
|
|
else if (p_irq_ctx[pin].negedgeHdl) //fall
|
|
{
|
|
type = POL_FALLING;
|
|
}
|
|
|
|
hal_gpio_interrupt_enable(pin, type);
|
|
return PPlus_SUCCESS;
|
|
}
|
|
|
|
int hal_gpioretention_register(gpio_pin_e pin)
|
|
{
|
|
if (pin > (NUMBER_OF_PINS - 1))
|
|
return PPlus_ERR_NOT_SUPPORTED;
|
|
|
|
hal_gpio_pin_init(pin, GPIO_OUTPUT);
|
|
m_gpioCtx.pin_assignments[pin] = GPIO_PIN_ASSI_OUT;
|
|
|
|
m_gpioCtx.pin_retention_status |= BIT(pin);
|
|
return PPlus_SUCCESS;
|
|
}
|
|
|
|
|
|
int hal_gpioin_register(gpio_pin_e pin, gpioin_Hdl_t posedgeHdl, gpioin_Hdl_t negedgeHdl)
|
|
{
|
|
int ret;
|
|
gpioin_Ctx_t* p_irq_ctx = &(m_gpioCtx.irq_ctx[0]);
|
|
hal_gpioin_disable(pin);
|
|
p_irq_ctx[pin].posedgeHdl = posedgeHdl;
|
|
p_irq_ctx[pin].negedgeHdl = negedgeHdl;
|
|
ret = hal_gpioin_enable(pin);
|
|
JUMP_FUNCTION(GPIO_IRQ_HANDLER) = (uint32_t)&hal_GPIO_IRQHandler;
|
|
|
|
if (ret != PPlus_SUCCESS)
|
|
hal_gpioin_disable(pin);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int hal_gpio_init(void)
|
|
{
|
|
if (m_gpioCtx.state)
|
|
return PPlus_ERR_INVALID_STATE;
|
|
|
|
memset(&m_gpioCtx, 0, sizeof(m_gpioCtx));
|
|
m_gpioCtx.state = TRUE;
|
|
//disable all channel irq,unmask all channel
|
|
AP_GPIO->inten = 0;
|
|
AP_GPIO->intmask = 0;
|
|
//disable all wakeup pin
|
|
AP_WAKEUP->io_wu_mask_31_0 = 0;
|
|
AP_WAKEUP->io_wu_mask_34_32 = 0;
|
|
NVIC_SetPriority(GPIO_IRQn, IRQ_PRIO_HAL);
|
|
NVIC_EnableIRQ(GPIO_IRQn);
|
|
#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
|
|
hal_pwrmgr_register(MOD_GPIO, hal_gpio_sleep_handler, hal_gpio_wakeup_handler);
|
|
#endif
|
|
return PPlus_SUCCESS;
|
|
}
|
|
|
|
void hal_gpio_debug_mux(Freq_Type_e fre,bool en)
|
|
{
|
|
if(en)
|
|
AP_IOMUX->debug_mux_en |= BIT(fre);
|
|
else
|
|
AP_IOMUX->debug_mux_en &= ~BIT(fre);
|
|
}
|