476 lines
12 KiB
C
476 lines
12 KiB
C
/*******************************************************************************
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@file flash.c
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@brief Contains all functions support for flash driver
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@version 0.0
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@date 27. Nov. 2017
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@author qing.han
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SDK_LICENSE
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*******************************************************************************/
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#include "rom_sym_def.h"
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#include <string.h>
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#include "types.h"
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#include "flash.h"
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#include "log.h"
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#include "pwrmgr.h"
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#include "error.h"
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#define SPIF_WAIT_IDLE_CYC (32)
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#define SPIF_STATUS_WAIT_IDLE(n) \
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do \
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{ \
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while((AP_SPIF->fcmd & 0x02) == 0x02); \
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volatile int delay_cycle = n; \
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while (delay_cycle--){}; \
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while ((AP_SPIF->config & 0x80000000) == 0);\
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} while (0);
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#define HAL_CACHE_ENTER_BYPASS_SECTION() do{ \
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HAL_ENTER_CRITICAL_SECTION();\
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AP_CACHE->CTRL0 = 0x02; \
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AP_PCR->CACHE_RST = 0x02;\
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AP_PCR->CACHE_BYPASS = 1; \
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HAL_EXIT_CRITICAL_SECTION();\
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}while(0);
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#define HAL_CACHE_EXIT_BYPASS_SECTION() do{ \
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HAL_ENTER_CRITICAL_SECTION();\
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AP_CACHE->CTRL0 = 0x00;\
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AP_PCR->CACHE_RST = 0x03;\
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AP_PCR->CACHE_BYPASS = 0;\
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HAL_EXIT_CRITICAL_SECTION();\
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}while(0);
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#define spif_wait_nobusy(flg, tout_ns, return_val) {if(_spif_wait_nobusy_x(flg, tout_ns)){if(return_val){ return return_val;}}}
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static xflash_Ctx_t s_xflashCtx = {
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.spif_ref_clk = SYS_CLK_DLL_64M,
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.rd_instr = XFRD_FCMD_READ_DUAL };
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chipMAddr_t g_chipMAddr;
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__ATTR_SECTION_SRAM__ static inline uint32_t spif_lock() {
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HAL_ENTER_CRITICAL_SECTION();
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uint32_t vic_iser = NVIC->ISER[0];
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//mask all irq
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NVIC->ICER[0] = 0xFFFFFFFF;
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//enable ll irq and tim1 irq
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NVIC->ISER[0] = 0x100010;
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HAL_EXIT_CRITICAL_SECTION();
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return vic_iser;
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}
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__ATTR_SECTION_SRAM__ static inline void spif_unlock(uint32_t vic_iser) {
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HAL_ENTER_CRITICAL_SECTION();
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NVIC->ISER[0] = vic_iser;
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HAL_EXIT_CRITICAL_SECTION();
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}
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static void hal_cache_tag_flush(void) {
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HAL_ENTER_CRITICAL_SECTION();
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uint32_t cb = AP_PCR->CACHE_BYPASS;
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volatile int dly = 8;
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if (cb == 0) {
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AP_PCR->CACHE_BYPASS = 1;
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}
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AP_CACHE->CTRL0 = 0x02;
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while (dly--) {
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;
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};
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AP_CACHE->CTRL0 = 0x03;
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dly = 8;
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while (dly--) {
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;
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};
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AP_CACHE->CTRL0 = 0x00;
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if (cb == 0) {
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AP_PCR->CACHE_BYPASS = 0;
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}
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HAL_EXIT_CRITICAL_SECTION();
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}
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static uint8_t _spif_read_status_reg_x(void) {
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uint8_t status;
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spif_cmd(FCMD_RDST, 0, 2, 0, 0, 0);
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_rddata(&status, 1);
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return status;
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}
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static int _spif_wait_nobusy_x(uint8_t flg, uint32_t tout_ns) {
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uint8_t status;
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volatile int tout = (int) (tout_ns);
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for (; tout; tout--) {
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status = _spif_read_status_reg_x();
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if ((status & flg) == 0)
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return PPlus_SUCCESS;
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//insert polling interval
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//5*32us
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WaitRTCCount(5);
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}
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return PPlus_ERR_BUSY;
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}
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static void hal_cache_init(void) {
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volatile int dly = 100;
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//clock gate
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hal_clk_gate_enable(MOD_HCLK_CACHE);
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hal_clk_gate_enable(MOD_PCLK_CACHE);
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//cache rst ahp
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AP_PCR->CACHE_RST = 0x02;
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while (dly--) {
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};
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AP_PCR->CACHE_RST = 0x03;
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hal_cache_tag_flush();
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//cache enable
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AP_PCR->CACHE_BYPASS = 0;
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}
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FLASH_CHIP_INFO phy_flash = { .init_flag = FALSE, .IdentificationID = 0x00,
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.Capacity = 0x80000, };
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int hal_get_flash_info(void) {
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uint32_t cs;
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uint8_t data[17];
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if (phy_flash.init_flag == TRUE) {
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return PPlus_SUCCESS;
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}
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cs = spif_lock();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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spif_cmd(FCMD_RDID, 0, 3, 0, 0, 0);
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spif_rddata(data, 3);
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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spif_unlock(cs);
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phy_flash.IdentificationID = (data[2] << 16) | (data[1] << 8) | data[0];
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if ((data[2] >= 0x11) && (data[2] <= 0x16)) //most use:256K~2M.reserved:128K,4M
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{
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phy_flash.Capacity = (1ul << data[2]);
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*(volatile int*) 0x1fff0898 = phy_flash.Capacity;
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} else {
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phy_flash.Capacity = 512 * 1024;
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*(volatile int*) 0x1fff0898 = phy_flash.Capacity;
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}
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phy_flash.init_flag = TRUE;
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return PPlus_SUCCESS;
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}
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#if(FLASH_PROTECT_FEATURE == 1)
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int hal_flash_lock(void)
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{
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uint32_t cs = spif_lock();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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AP_SPIF->fcmd = 0x6000001;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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AP_SPIF->fcmd_wrdata[0] = 0x7c;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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AP_SPIF->fcmd = 0x1008001;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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spif_unlock(cs);
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return PPlus_SUCCESS;
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}
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int hal_flash_unlock(void)
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{
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uint32_t cs = spif_lock();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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AP_SPIF->fcmd = 0x6000001;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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AP_SPIF->fcmd_wrdata[0] = 0x00;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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AP_SPIF->fcmd = 0x1008001;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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spif_unlock(cs);
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return PPlus_SUCCESS;
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}
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uint8_t hal_flash_get_lock_state(void)
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{
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uint32_t cs = spif_lock();
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uint8_t status;
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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status = _spif_read_status_reg_x();
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status = (status & 0x7c)>>2;
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spif_unlock(cs);
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return status;
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}
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#endif
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static void hw_spif_cache_config(void)
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{
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spif_config(s_xflashCtx.spif_ref_clk,
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1,
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s_xflashCtx.rd_instr,
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0,
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(s_xflashCtx.rd_instr == XFRD_FCMD_READ_QUAD)? 1 : 0);
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#ifdef XFLASH_HIGH_SPEED
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volatile uint32_t tmp = AP_SPIF->config;
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tmp = (tmp & (~ (0xf << 19))) | (0 << 19);
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AP_SPIF->config = tmp;
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subWriteReg(&AP_SPIF->rddata_capture, 4, 1, 2);
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#endif
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AP_SPIF->wr_completion_ctrl = 0xff010005; //set longest polling interval
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AP_SPIF->low_wr_protection = 0;
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AP_SPIF->up_wr_protection = 0x10;
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AP_SPIF->wr_protection = 0x2;
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NVIC_DisableIRQ(SPIF_IRQn);
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NVIC_SetPriority((IRQn_Type)SPIF_IRQn, IRQ_PRIO_HAL);
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hal_cache_init();
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hal_get_flash_info();
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}
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int hal_spif_cache_init(sysclk_t spif_ref_clk, uint32_t rd_instr) {
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s_xflashCtx.spif_ref_clk = spif_ref_clk;
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s_xflashCtx.rd_instr = rd_instr;
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hw_spif_cache_config();
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hal_pwrmgr_register(MOD_SPIF, NULL, hw_spif_cache_config);
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return PPlus_SUCCESS;
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}
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int hal_flash_read(uint32_t addr, uint8_t *data, uint32_t size) {
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uint32_t cs = spif_lock();
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volatile uint8_t *u8_spif_addr = (volatile uint8_t*) ((addr & 0x7ffff)
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| FLASH_BASE_ADDR);
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uint32_t cb = AP_PCR->CACHE_BYPASS;
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uint32_t remap = 0;
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if (phy_flash.Capacity > 0x80000) {
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remap = addr & 0xf80000;
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if (remap) {
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AP_SPIF->remap = remap;
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AP_SPIF->config |= 0x10000;
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}
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}
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//read flash addr direct access
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//bypass cache
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if (cb == 0) {
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HAL_CACHE_ENTER_BYPASS_SECTION();
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}
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for (uint32_t i = 0; i < size; i++)
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data[i] = u8_spif_addr[i];
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//bypass cache
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if (cb == 0) {
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HAL_CACHE_EXIT_BYPASS_SECTION();
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}
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if (phy_flash.Capacity > 0x80000) {
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if (remap) {
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AP_SPIF->remap = 0;
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AP_SPIF->config &= ~0x10000ul;
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}
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}
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spif_unlock(cs);
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return PPlus_SUCCESS;
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}
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int hal_flash_write(uint32_t addr, uint8_t *data, uint32_t size) {
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uint8_t retval;
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_unlock();
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#endif
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uint32_t cs = spif_lock();
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HAL_CACHE_ENTER_BYPASS_SECTION();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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retval = spif_write(addr, data, size);
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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HAL_CACHE_EXIT_BYPASS_SECTION();
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spif_unlock(cs);
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_lock();
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#endif
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return retval;
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}
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int hal_flash_write_by_dma(uint32_t addr, uint8_t *data, uint32_t size) {
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uint8_t retval;
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_unlock();
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#endif
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uint32_t cs = spif_lock();
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HAL_CACHE_ENTER_BYPASS_SECTION();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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retval = spif_write_dma(addr, data, size);
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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HAL_CACHE_EXIT_BYPASS_SECTION();
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spif_unlock(cs);
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_lock();
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#endif
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return retval;
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}
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int hal_flash_erase_sector(unsigned int addr) {
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uint8_t retval;
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_unlock();
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#endif
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uint32_t cs = spif_lock();
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uint32_t cb = AP_PCR->CACHE_BYPASS;
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HAL_CACHE_ENTER_BYPASS_SECTION();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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retval = spif_erase_sector(addr);
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WELWIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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HAL_CACHE_EXIT_BYPASS_SECTION();
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if (cb == 0) {
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hal_cache_tag_flush();
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}
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spif_unlock(cs);
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_lock();
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#endif
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return retval;
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}
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int hal_flash_erase_block64(unsigned int addr) {
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uint8_t retval;
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_unlock();
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#endif
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uint32_t cs = spif_lock();
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uint32_t cb = AP_PCR->CACHE_BYPASS;
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HAL_CACHE_ENTER_BYPASS_SECTION();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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retval = spif_erase_block64(addr);
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WELWIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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HAL_CACHE_EXIT_BYPASS_SECTION();
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if (cb == 0) {
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hal_cache_tag_flush();
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}
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spif_unlock(cs);
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_lock();
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#endif
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return retval;
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}
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int hal_flash_erase_all(void) {
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uint8_t retval;
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_unlock();
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#endif
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uint32_t cs = spif_lock();
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uint32_t cb = AP_PCR->CACHE_BYPASS;
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HAL_CACHE_ENTER_BYPASS_SECTION();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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retval = spif_erase_all();
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SPIF_STATUS_WAIT_IDLE(SPIF_WAIT_IDLE_CYC);
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spif_wait_nobusy(SFLG_WELWIP, SPIF_TIMEOUT, PPlus_ERR_BUSY);
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HAL_CACHE_EXIT_BYPASS_SECTION();
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if (cb == 0) {
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hal_cache_tag_flush();
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}
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spif_unlock(cs);
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#if(FLASH_PROTECT_FEATURE == 1)
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hal_flash_lock();
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#endif
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return retval;
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}
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int flash_write_word(unsigned int offset, uint32_t value) {
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uint32_t temp = value;
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offset &= 0x00ffffff;
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return (hal_flash_write(offset, (uint8_t*) &temp, 4));
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}
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CHIP_ID_STATUS_e read_chip_mAddr(void) {
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CHIP_ID_STATUS_e ret = CHIP_ID_UNCHECK;
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uint8_t b;
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for (int i = 0; i < CHIP_MADDR_LEN; i++) {
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ret = chip_id_one_bit_hot_convter(&b,
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read_reg(CHIP_MADDR_FLASH_ADDRESS+(i<<2)));
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if (ret == CHIP_ID_VALID) {
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g_chipMAddr.mAddr[CHIP_MADDR_LEN - 1 - i] = b;
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} else {
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if (i > 0 && ret == CHIP_ID_EMPTY) {
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ret = CHIP_ID_INVALID;
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}
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return ret;
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}
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}
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return ret;
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}
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void check_chip_mAddr(void) {
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//chip id check
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for (int i = 0; i < CHIP_MADDR_LEN; i++) {
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g_chipMAddr.mAddr[i] = 0xff;
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}
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g_chipMAddr.chipMAddrStatus = read_chip_mAddr();
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}
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void LOG_CHIP_MADDR(void) {
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LOG("\n");
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if (g_chipMAddr.chipMAddrStatus == CHIP_ID_EMPTY) {
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LOG("[CHIP_MADDR EMPTY]\n");
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} else if (g_chipMAddr.chipMAddrStatus == CHIP_ID_INVALID) {
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LOG("[CHIP_MADDR INVALID]\n");
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} else if (g_chipMAddr.chipMAddrStatus == CHIP_ID_VALID) {
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LOG("[CHIP_MADDR VALID]\n");
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for (int i = 0; i < CHIP_MADDR_LEN; i++) {
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LOG("%02x",g_chipMAddr.mAddr[i]);
|
|
} LOG("\n");
|
|
|
|
} else {
|
|
LOG("[CHIP_MADDR UNCHECKED]\n");
|
|
}
|
|
}
|
|
|