367 lines
14 KiB
C
367 lines
14 KiB
C
/*************
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dma.h
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SDK_LICENSE
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***************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
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@ingroup LPC177x_8xCMSIS_FwLib_Drivers
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@{
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*/
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#ifndef __DMA_H_
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#define __DMA_H_
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/* Includes ------------------------------------------------------------------- */
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#include "bus_dev.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup GPDMA_Public_Macros GPDMA Public Macros
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@{
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*/
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/** DMAC Connection number definitions */
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typedef enum
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{
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DMA_CONN_MEM=0,// ((0)) /*memory*/
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DMA_CONN_SPI0_Tx=1,// ((0UL)) /** SSP0 Tx */
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DMA_CONN_SPI0_Rx,// ((1UL)) /** SSP0 Rx */
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DMA_CONN_SPI1_Tx,// ((2UL)) /** SSP1 Tx */
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DMA_CONN_SPI1_Rx,// ((3UL)) /** SSP1 Rx */
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DMA_CONN_I2C0_Tx=9,// ((8UL)) /** IIC0 Tx */
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DMA_CONN_I2C0_Rx,// ((9UL)) /** IIC0 Rx */
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DMA_CONN_I2C1_Tx,// ((10UL)) /** IIC1 Tx */
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DMA_CONN_I2C1_Rx,// ((11UL)) /** IIC1 Rx */
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DMA_CONN_UART0_Tx,// ((10UL)) /** UART0 Tx */
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DMA_CONN_UART0_Rx,// ((11UL)) /** UART0 Rx */
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DMA_CONN_UART1_Tx,// ((12UL)) /** UART1 Tx */
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DMA_CONN_UART1_Rx,// ((13UL)) /** UART1 Rx */
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} DMA_CONN_e;
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/** Burst size in Source and Destination definitions */
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#define DMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
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#define DMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
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#define DMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
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#define DMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
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#define DMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
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#define DMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
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#define DMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
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#define DMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
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/** Width in Source transfer width and Destination transfer width definitions */
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#define DMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
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#define DMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
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#define DMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
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#define DMA_WIDTH_2WORD ((3UL)) /**< Width = 8 bytes */
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#define DMA_WIDTH_4WORD ((4UL)) /**< Width = 16 bytes */
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#define DMA_WIDTH_8WORD ((5UL)) /**< Width = 32 bytes */
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/** DMAC Address Increment definitions */
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#define DMA_INC_INC ((0UL)) /**< Increment */
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#define DMA_INC_DEC ((1UL)) /**< Decrement */
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#define DMA_INC_NCHG ((2UL)) /**< No change */
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/**
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@}
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*/
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/* Private Macros ------------------------------------------------------------- */
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/** @defgroup GPDMA_Private_Macros GPDMA Private Macros
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@{
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*/
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/* --------------------- BIT DEFINITIONS -------------------------------------- */
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/*********************************************************************//**
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Macro defines for DMA Interrupt Status register
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**********************************************************************/
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#define DMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntStat_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt Terminal Count Request Status register
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**********************************************************************/
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#define DMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntTCStat_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt Terminal Count Request Clear register
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**********************************************************************/
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#define DMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntTCClear_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt Error Status register
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**********************************************************************/
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#define DMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntErrStat_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt Tfr Clear register
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**********************************************************************/
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#define DMA_DMACIntTfrClr_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntTfrClr_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt Block Clear register
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**********************************************************************/
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#define DMA_DMACIntBlockClr_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntBlockClr_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt SrcTran Clear register
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**********************************************************************/
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#define DMA_DMACIntSrcTranClr_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntSrcTranClr_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt DstTran Clear register
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**********************************************************************/
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#define DMA_DMACIntDstTranClr_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntDstTranClr_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Interrupt Error Clear register
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**********************************************************************/
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#define DMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACIntErrClr_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Raw Interrupt Terminal Count Status register
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**********************************************************************/
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#define DMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACRawIntTCStat_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Raw Error Interrupt Status register
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**********************************************************************/
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#define DMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACRawIntErrStat_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Enabled Channel register
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**********************************************************************/
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#define DMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
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#define DMA_DMACEnbldChns_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Software Burst Request register
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**********************************************************************/
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#define DMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
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#define DMA_DMACSoftBReq_BITMASK ((0xFFFF))
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/*********************************************************************//**
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Macro defines for DMA Software Single Request register
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**********************************************************************/
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#define DMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
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#define DMA_DMACSoftSReq_BITMASK ((0xFFFF))
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/*********************************************************************//**
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Macro defines for DMA Software Last Burst Request register
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**********************************************************************/
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#define DMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
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#define DMA_DMACSoftLBReq_BITMASK ((0xFFFF))
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/*********************************************************************//**
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Macro defines for DMA Software Last Single Request register
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**********************************************************************/
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#define DMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
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#define DMA_DMACSoftLSReq_BITMASK ((0xFFFF))
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/*********************************************************************//**
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Macro defines for DMA Configuration register
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**********************************************************************/
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#define DMA_DMAC_E ((0x01)) /**< DMA Controller enable*/
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#define DMA_DMAC_D ((0x00)) /**< DMA Controller disable*/
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#define DMA_DMAC_INT_E ((0x01)) /**< DMA Controller Interrupt enable*/
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/*********************************************************************//**
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Macro defines for DMA Synchronization register
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**********************************************************************/
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#define DMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
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#define DMA_DMACSync_BITMASK ((0xFFFF))
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/*********************************************************************//**
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Macro defines for DMA Request Select register
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**********************************************************************/
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#define DMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
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#define DMA_DMAReqSel_BITMASK ((0xFF))
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/*********************************************************************//**
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Macro defines for DMA Channel Linked List Item registers
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**********************************************************************/
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/** DMAC Channel Linked List Item registers bit mask*/
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#define DMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
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/*********************************************************************//**
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Macro defines for DMA channel control registers
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**********************************************************************/
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/** Transfer size*/
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#define DMA_DMACCxControl_TransferSize(n) (n&0x7FF)
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/** Source burst size*/
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#define DMA_DMACCxControl_SMSize(n) (((n&0x07)<<14))
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/** Destination burst size*/
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#define DMA_DMACCxControl_DMSize(n) (((n&0x07)<<11))
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/** Source transfer width*/
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#define DMA_DMACCxControl_SWidth(n) (((n&0x07)<<4))
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/** Destination transfer width*/
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#define DMA_DMACCxControl_DWidth(n) (((n&0x07)<<1))
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/** Source increment*/
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#define DMA_DMACCxControl_SInc(n) (((n&0x03)<<9))
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/** Destination increment*/
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#define DMA_DMACCxControl_DInc(n) (((n&0x03)<<7))
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/*********************************************************************//**
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Macro defines for DMA Channel Configuration registers
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**********************************************************************/
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/** DMAC channel write bit enable*/
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#define DMA_DMACCxConfig_E(n) ((0x100UL<<n))
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/** DMAC channel int mask bit enable*/
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#define DMA_DMACCxIntMask_E(n) ((0x100UL<<n))
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/** Source peripheral*/
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#define DMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)))
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/** Destination peripheral*/
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#define DMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<4))
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/** This value indicates the type of transfer*/
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#define DMA_DMACCxConfig_TransferType(n) (((n&0x7)<<20))
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/** Interrupt error mask*/
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#define DMA_DMACCxConfig_IE ((1UL<<14))
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/** Terminal count interrupt mask*/
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#define DMA_DMACCxConfig_ITC ((1UL<<15))
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/** Lock*/
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#define DMA_DMACCxConfig_L ((1UL<<16))
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/** Active*/
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#define DMA_DMACCxConfig_A ((1UL<<17))
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/** Halt*/
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#define DMA_DMACCxConfig_H ((1UL<<18))
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/** DMAC Channel Configuration registers bit mask */
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#define DMA_DMACCxConfig_BITMASK ((0x7FFFF))
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/**
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@}
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*/
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#define DMA_TRANSFERTYPE_M2M ((0UL))
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/** DMAC Transfer type definitions: Memory to peripheral - DMA control */
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#define DMA_TRANSFERTYPE_M2P ((1UL))
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/** DMAC Transfer type definitions: Peripheral to memory - DMA control */
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#define DMA_TRANSFERTYPE_P2M ((2UL))
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/** DMAC Source peripheral to destination peripheral - DMA control */
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#define DMA_TRANSFERTYPE_P2P ((3UL))
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/** If dstnation address is flash, should set this bit- DMA control */
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#define DMA_DST_XIMT_IS_FLASH ((0UL))
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/** DMAC Source peripheral to destination peripheral - DMA control */
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#define DMA_DST_XIMT_NOT_FLASH ((1UL))
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#define DMA_GET_MAX_TRANSPORT_SIZE(ch) ((ch == DMA_CH_0) ? 0x7ff : 0x1f)
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/**
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@brief DMAC Interrupt clear status enumeration
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*/
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typedef enum
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{
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DMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
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DMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
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} DMA_StateClear_Type;
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/**
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@brief DMAC Channel configuration structure type definition
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*/
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typedef struct
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{
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uint32_t transf_size; /**< Length/Size of transfer */
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uint8_t sinc;
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uint8_t src_tr_width;
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uint8_t src_msize;
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uint32_t src_addr;
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uint8_t dinc;
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uint8_t dst_tr_width;
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uint8_t dst_msize;
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uint32_t dst_addr;
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bool enable_int;
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} DMA_CH_CFG_t;
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typedef enum
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{
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DMA_CH_0 = 0,
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DMA_CH_1,
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DMA_CH_2,
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DMA_CH_3,
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DMA_CH_NUM,
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} DMA_CH_t;
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/**
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@brief DMAC Linker List Item structure type definition
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*/
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typedef struct
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{
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uint32_t src_addr; /**< Source Address */
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uint32_t dst_addr; /**< Destination address */
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uint32_t lli; /**< Next LLI address, otherwise set to '0' */
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uint32_t ctrl; /**< GPDMA Control of this LLI */
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} DMA_LLI_t;
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/**
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@brief DMAC callback definition
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*/
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typedef void (*DMA_Hdl_t)(DMA_CH_t);
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typedef struct
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{
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DMA_CH_t dma_channel;
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DMA_Hdl_t evt_handler;
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} HAL_DMA_t;
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typedef struct
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{
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uint8_t init_ch;
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uint8_t interrupt;
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uint8_t xmit_busy;
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uint8_t xmit_flash;
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DMA_Hdl_t evt_handler;
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} DMA_CH_Ctx_t;
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int hal_dma_init_channel(HAL_DMA_t cfg);
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int hal_dma_config_channel(DMA_CH_t ch, DMA_CH_CFG_t* cfg);
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int hal_dma_start_channel(DMA_CH_t ch);
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int hal_dma_stop_channel(DMA_CH_t ch);
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int hal_dma_wait_channel_complete(DMA_CH_t ch);
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int hal_dma_status_control(DMA_CH_t ch);
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int hal_dma_init(void);
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int hal_dma_deinit(void);
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void __attribute__((used)) hal_DMA_IRQHandler(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __LPC177X_8X_GPDMA_H_ */
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/**
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@}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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