665 lines
16 KiB
C
665 lines
16 KiB
C
/*******************************************************************************
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@file adc.c
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@brief Contains all functions support for adc driver
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@version 0.0
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@date 18. Oct. 2017
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@author qing.han
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SDK_LICENSE
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*******************************************************************************/
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#include <string.h>
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#include "error.h"
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#include "gpio.h"
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#include "pwrmgr.h"
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#include "clock.h"
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#include "adc.h"
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#include "log.h"
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#include "jump_function.h"
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#include "version.h"
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typedef struct _adc_Contex_t
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{
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bool enable;
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uint8_t all_channel;
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uint8_t chs_en_shadow;
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bool continue_mode;
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//sysclk_t clk_src;
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uint16_t adc_cal_postive;
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uint16_t adc_cal_negtive;
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adc_Hdl_t evt_handler;
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} adc_Ctx_t;
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static adc_Ctx_t mAdc_Ctx =
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{
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.enable = FALSE,
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.all_channel = 0x00,
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.chs_en_shadow = 0x00,
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.continue_mode = FALSE,
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.adc_cal_postive = 0xFFF,
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.adc_cal_negtive = 0xFFF,
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.evt_handler = NULL
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};
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gpio_pin_e s_pinmap[ADC_CH_NUM] =
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{
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GPIO_DUMMY, //ADC_CH0 =0,
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GPIO_DUMMY, //ADC_CH1 =1,
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P11, //ADC_CH1N =2,
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P23, //ADC_CH1P =3, ADC_CH1DIFF = 3,
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P24, //ADC_CH2N =4,
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P14, //ADC_CH2P =5, ADC_CH2DIFF = 5,
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P15, //ADC_CH3N =6,
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P20, //ADC_CH3P =7, ADC_CH3DIFF = 7,
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GPIO_DUMMY, //ADC_CH_VOICE =8,
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};
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/**************************************************************************************
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@fn hal_adc_value
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@brief This function process for get adc value
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input parameters
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@param ADC_CH_e adc_pin: adc pin select;ADC_CH0~ADC_CH7 and ADC_CH_VOICE
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output parameters
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@param None.
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@return ADC value
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**************************************************************************************/
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static void hal_adc_load_calibration_value(void)
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{
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uint32_t adc_cal = read_reg(SPIF_RSVD1_ADC_CALIBRATE);
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mAdc_Ctx.adc_cal_negtive = (uint16_t)(adc_cal & 0x0fff);
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mAdc_Ctx.adc_cal_postive = (uint16_t)((adc_cal >> 16) & 0x0fff);
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LOG("AD_CAL[%x %x]\n", mAdc_Ctx.adc_cal_negtive, mAdc_Ctx.adc_cal_postive);
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if((mAdc_Ctx.adc_cal_negtive < 0x733) || (mAdc_Ctx.adc_cal_negtive > 0x8cc) ||
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(mAdc_Ctx.adc_cal_postive < 0x733) || (mAdc_Ctx.adc_cal_postive > 0x8cc))
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{
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mAdc_Ctx.adc_cal_negtive = 0xfff;
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mAdc_Ctx.adc_cal_postive = 0xfff;
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LOG("->AD_CAL[%x %x]\n",mAdc_Ctx.adc_cal_negtive, mAdc_Ctx.adc_cal_postive);
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}
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}
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static void set_sampling_resolution(adc_CH_t channel, bool is_high_resolution,bool is_differential_mode)
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{
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uint8_t aio = 0;
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uint8_t diff_aio = 0;
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switch(channel)
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{
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case ADC_CH1N_P11:
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aio = 0;
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diff_aio = 1;
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break;
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case ADC_CH1P_P23:
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aio = 1;
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diff_aio = 0;
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break;
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case ADC_CH2N_P24:
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aio = 2;
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diff_aio = 3;
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break;
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case ADC_CH2P_P14:
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aio = 3;
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diff_aio = 2;
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break;
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case ADC_CH3N_P15:
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aio = 4;
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diff_aio = 7;
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break;
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case ADC_CH3P_P20:
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aio = 7;
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diff_aio = 4;
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break;
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default:
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return;
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}
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if(is_high_resolution)
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{
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if(is_differential_mode)
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{
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subWriteReg(&(AP_AON->PMCTL2_1),(diff_aio+8),(diff_aio+8),0);
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subWriteReg(&(AP_AON->PMCTL2_1),diff_aio,diff_aio,1);
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}
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subWriteReg(&(AP_AON->PMCTL2_1),(aio+8),(aio+8),0);
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subWriteReg(&(AP_AON->PMCTL2_1),aio,aio,1);
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}
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else
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{
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if(is_differential_mode)
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{
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subWriteReg(&(AP_AON->PMCTL2_1),(diff_aio+8),(diff_aio+8),1);
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subWriteReg(&(AP_AON->PMCTL2_1),diff_aio,diff_aio,0);
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}
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subWriteReg(&(AP_AON->PMCTL2_1),(aio+8),(aio+8),1);
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subWriteReg(&(AP_AON->PMCTL2_1),aio,aio,0);
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}
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}
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static void set_sampling_resolution_auto(uint8_t channel, uint8_t is_high_resolution,uint8_t is_differential_mode)
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{
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uint8_t i_channel;
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adc_CH_t a_channel;
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AP_AON->PMCTL2_1 = 0x00;
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for(i_channel =MIN_ADC_CH; i_channel<=MAX_ADC_CH; i_channel++)
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{
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if(channel & BIT(i_channel))
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{
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a_channel = (adc_CH_t)i_channel;
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set_sampling_resolution(a_channel,
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(is_high_resolution & BIT(i_channel)),
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(is_differential_mode & BIT(i_channel)));
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}
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}
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}
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static void set_differential_mode(void)
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{
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subWriteReg(&( AP_PCRM->ANA_CTL),8,8,0);
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subWriteReg(&( AP_PCRM->ANA_CTL),11,11,0);
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}
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static void disable_analog_pin(adc_CH_t channel)
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{
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int index = (int)channel;
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gpio_pin_e pin = s_pinmap[index];
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if(pin == GPIO_DUMMY)
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return;
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hal_gpio_cfg_analog_io(pin,Bit_DISABLE);
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hal_gpio_pin_init(pin,GPIO_INPUT); //ie=0,oen=1 set to imput
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hal_gpio_pull_set(pin,GPIO_FLOATING); //
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}
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static void clear_adcc_cfg(void)
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{
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mAdc_Ctx.all_channel = 0x00;
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mAdc_Ctx.chs_en_shadow = 0x00;
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mAdc_Ctx.continue_mode = FALSE;
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mAdc_Ctx.evt_handler = NULL;
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}
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#if 0
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static void disable_channel(adc_CH_t ch)
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{
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switch (ch)
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{
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case ADC_CH1N_P11:
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AP_PCRM->ADC_CTL1 &= ~BIT(20);
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break;
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case ADC_CH1P_P23:
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AP_PCRM->ADC_CTL1 &= ~BIT(4);
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break;
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case ADC_CH2N_P24:
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AP_PCRM->ADC_CTL2 &= ~BIT(20);
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break;
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case ADC_CH2P_P14:
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AP_PCRM->ADC_CTL2 &= ~BIT(4);
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break;
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case ADC_CH3N_P15:
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AP_PCRM->ADC_CTL3 &= ~BIT(20);
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break;
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case ADC_CH3P_P20:
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AP_PCRM->ADC_CTL3 &= ~BIT(4);
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break;
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}
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}
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#endif
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/////////////// adc ////////////////////////////
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/**************************************************************************************
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@fn hal_ADC_IRQHandler
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@brief This function process for adc interrupt
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input parameters
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@param None.
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output parameters
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@param None.
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@return None.
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**************************************************************************************/
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void __attribute__((used)) hal_ADC_IRQHandler(void)
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{
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int ch,ch2,status =0,n;
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uint16_t adc_data[MAX_ADC_SAMPLE_SIZE-2];
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status = GET_IRQ_STATUS;
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for (ch = MIN_ADC_CH; ch <= MAX_ADC_CH; ch++)
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{
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if ((mAdc_Ctx.all_channel & BIT(ch)) &&(status & BIT(ch)))
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{
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ch2=(ch%2)?(ch-1):(ch+1);
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if(mAdc_Ctx.continue_mode == FALSE)
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{
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AP_ADCC->intr_mask &= ~ BIT(ch); //MASK coresponding channel
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mAdc_Ctx.all_channel &= ~BIT(ch);//disable channel
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}
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for (n = 0; n < (MAX_ADC_SAMPLE_SIZE-3); n++)
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{
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adc_data[n] = (uint16_t)(read_reg(ADC_CH_BASE + (ch * 0x80) + ((n+2) * 4))&0xfff);
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adc_data[n+1] = (uint16_t)((read_reg(ADC_CH_BASE + (ch * 0x80) + ((n+2) * 4))>>16)&0xfff);
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}
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AP_ADCC->intr_clear = BIT(ch);
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if(mAdc_Ctx.enable == FALSE)
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continue;
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if (mAdc_Ctx.evt_handler)
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{
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adc_Evt_t evt;
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evt.type = HAL_ADC_EVT_DATA;
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evt.ch = (adc_CH_t)ch2;
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evt.data = adc_data;
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evt.size = MAX_ADC_SAMPLE_SIZE-3;
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mAdc_Ctx.evt_handler(&evt);
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}
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}
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}
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//LOG("> %x\n",mAdc_Ctx.all_channel);
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if((mAdc_Ctx.all_channel == 0) && (mAdc_Ctx.continue_mode == FALSE))//
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{
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hal_adc_stop();
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}
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}
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static void adc_wakeup_hdl(void)
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{
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NVIC_SetPriority((IRQn_Type)ADCC_IRQn, IRQ_PRIO_HAL);
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}
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/**************************************************************************************
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@fn hal_adc_init
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@brief This function process for adc initial
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input parameters
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@param ADC_MODE_e mode: adc sample mode select;1:SAM_MANNUAL(mannual mode),0:SAM_AUTO(auto mode)
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ADC_CH_e adc_pin: adc pin select;ADC_CH0~ADC_CH7 and ADC_CH_VOICE
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ADC_SEMODE_e semode: signle-ended mode negative side enable; 1:SINGLE_END(single-ended mode) 0:DIFF(Differentail mode)
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IO_CONTROL_e amplitude: input signal amplitude, 0:BELOW_1V,1:UP_1V
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output parameters
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@param None.
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@return None.
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**************************************************************************************/
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void hal_adc_init(void)
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{
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hal_pwrmgr_register(MOD_ADCC,NULL,adc_wakeup_hdl);
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clear_adcc_cfg();
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hal_adc_load_calibration_value();
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mAdc_Ctx.enable = TRUE;
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}
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int hal_adc_clock_config(adc_CLOCK_SEL_t clk)
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{
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if(mAdc_Ctx.enable == FALSE)
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{
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return PPlus_ERR_NOT_REGISTED;
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}
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subWriteReg(&(AP_PCRM->ADC_CTL4),2,1,clk);
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return PPlus_SUCCESS;
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}
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int hal_adc_start(void)
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{
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uint8_t all_channel2 = (((mAdc_Ctx.chs_en_shadow&0x80)>>1)|\
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((mAdc_Ctx.chs_en_shadow&0x40)<<1)|\
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((mAdc_Ctx.chs_en_shadow&0x20)>>1)|\
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((mAdc_Ctx.chs_en_shadow&0x10)<<1)|\
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((mAdc_Ctx.chs_en_shadow&0x08)>>1)|\
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((mAdc_Ctx.chs_en_shadow&0x04)<<1));
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if(mAdc_Ctx.enable == FALSE)
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{
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return PPlus_ERR_NOT_REGISTED;
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}
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//LOG("all_channel2:0x%x\n",all_channel2);
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hal_pwrmgr_lock(MOD_ADCC);
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JUMP_FUNCTION(ADCC_IRQ_HANDLER) = (uint32_t)&hal_ADC_IRQHandler;
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for(int i=MIN_ADC_CH; i<=MAX_ADC_CH; i++)
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{
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if(all_channel2 & (BIT(i)))
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{
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switch (i)
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{
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case ADC_CH1N_P11:
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AP_PCRM->ADC_CTL1 |= BIT(20);
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break;
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case ADC_CH1P_P23:
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AP_PCRM->ADC_CTL1 |= BIT(4);
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break;
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case ADC_CH2N_P24:
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AP_PCRM->ADC_CTL2 |= BIT(20);
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break;
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case ADC_CH2P_P14:
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AP_PCRM->ADC_CTL2 |= BIT(4);
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break;
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case ADC_CH3N_P15:
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AP_PCRM->ADC_CTL3 |= BIT(20);
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break;
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case ADC_CH3P_P20:
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AP_PCRM->ADC_CTL3 |= BIT(4);
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break;
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}
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}
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}
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AP_PCRM->ANA_CTL |= BIT(3);//ENABLE_ADC;
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AP_PCRM->ANA_CTL |= BIT(0);//new
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NVIC_EnableIRQ((IRQn_Type)ADCC_IRQn); //ADC_IRQ_ENABLE;
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AP_ADCC->intr_mask = mAdc_Ctx.all_channel; //ENABLE_ADC_INT;
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//disableSleep();
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return PPlus_SUCCESS;
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}
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int hal_adc_config_channel(adc_Cfg_t cfg, adc_Hdl_t evt_handler)
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{
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uint8_t i;
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uint8_t chn_sel;
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gpio_pin_e pin,pin_neg;
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if(mAdc_Ctx.enable == FALSE)
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{
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return PPlus_ERR_NOT_REGISTED;
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}
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if(evt_handler == NULL)
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{
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return PPlus_ERR_INVALID_PARAM;
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}
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if((cfg.channel & BIT(0)) || (cfg.channel & BIT(1)))
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{
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return PPlus_ERR_NOT_SUPPORTED;
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}
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if((!cfg.channel & BIT(1))&&(cfg.is_differential_mode && (cfg.channel & BIT(1))))
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{
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return PPlus_ERR_INVALID_PARAM;
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}
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if(cfg.is_differential_mode != 0)
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{
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if((cfg.is_differential_mode != 0x80) && (cfg.is_differential_mode != 0x20) && (cfg.is_differential_mode != 0x08))
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{
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return PPlus_ERR_INVALID_PARAM;
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}
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}
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clear_adcc_cfg();
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AP_AON->PMCTL2_1 = 0x00;
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AP_PCRM->ANA_CTL &= ~BIT(0);
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AP_PCRM->ANA_CTL &= ~BIT(3);
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hal_clk_gate_disable(MOD_ADCC);
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hal_clk_reset(MOD_ADCC);
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mAdc_Ctx.continue_mode = cfg.is_continue_mode;
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mAdc_Ctx.all_channel = cfg.channel & 0x03;
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for(i=2; i<8; i++)
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{
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if(cfg.channel & BIT(i))
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{
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if(i%2)
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{
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mAdc_Ctx.all_channel |= BIT(i-1);
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}
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else
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{
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mAdc_Ctx.all_channel |= BIT(i+1);
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}
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}
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}
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mAdc_Ctx.chs_en_shadow = mAdc_Ctx.all_channel;
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//LOG("cfg.channel:0x%x\n",cfg.channel);
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LOG("mAdc_Ctx.all_channel:0x%x\n",mAdc_Ctx.all_channel);
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if((AP_PCR->SW_CLK & BIT(MOD_ADCC)) == 0)
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{
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hal_clk_gate_enable(MOD_ADCC);
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}
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//CLK_1P28M_ENABLE;
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AP_PCRM->CLKSEL |= BIT(6);
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//ENABLE_XTAL_OUTPUT; //enable xtal 16M output,generate the 32M dll clock
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AP_PCRM->CLKHF_CTL0 |= BIT(18);
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//ENABLE_DLL; //enable DLL
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AP_PCRM->CLKHF_CTL1 |= BIT(7);
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//ADC_DBLE_CLOCK_DISABLE; //disable double 32M clock,we are now use 32M clock,should enable bit<13>, diable bit<21>
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AP_PCRM->CLKHF_CTL1 &= ~BIT(21);//check
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//subWriteReg(0x4000F044,21,20,3);
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//ADC_CLOCK_ENABLE; //adc clock enbale,always use clk_32M
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AP_PCRM->CLKHF_CTL1 |= BIT(13);
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//subWriteReg(0x4000f07c,4,4,1); //set adc mode,1:mannual,0:auto mode
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AP_PCRM->ADC_CTL4 |= BIT(4);
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AP_PCRM->ADC_CTL4 |= BIT(0);
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set_sampling_resolution_auto(cfg.channel, cfg.is_high_resolution,cfg.is_differential_mode);
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AP_PCRM->ADC_CTL0 &= ~BIT(20);
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AP_PCRM->ADC_CTL0 &= ~BIT(4);
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AP_PCRM->ADC_CTL1 &= ~BIT(20);
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AP_PCRM->ADC_CTL1 &= ~BIT(4);
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AP_PCRM->ADC_CTL2 &= ~BIT(20);
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AP_PCRM->ADC_CTL2 &= ~BIT(4);
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AP_PCRM->ADC_CTL3 &= ~BIT(20);
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AP_PCRM->ADC_CTL3 &= ~BIT(4);
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AP_PCRM->ANA_CTL &= ~BIT(23);//disable micbias
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if(cfg.is_differential_mode == 0)
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{
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AP_PCRM->ADC_CTL4 &= ~BIT(4); //enable auto mode
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mAdc_Ctx.evt_handler = evt_handler;
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for(i=MIN_ADC_CH; i<=MAX_ADC_CH; i++)
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{
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if(cfg.channel & BIT(i))
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|
{
|
|
gpio_pin_e pin = s_pinmap[i];
|
|
hal_gpio_pull_set(pin,GPIO_FLOATING);
|
|
hal_gpio_ds_control(pin, Bit_ENABLE);
|
|
hal_gpio_cfg_analog_io(pin, Bit_ENABLE);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch(cfg.is_differential_mode)
|
|
{
|
|
case 0x80:
|
|
pin = P20;
|
|
pin_neg = P15;
|
|
chn_sel = 0x04;
|
|
break;
|
|
|
|
case 0x20:
|
|
pin = P14;
|
|
pin_neg = P24;
|
|
chn_sel = 0x03;
|
|
break;
|
|
|
|
case 0x08:
|
|
pin = P23;
|
|
pin_neg = P11;
|
|
chn_sel = 0x02;
|
|
break;
|
|
|
|
case 0x02:
|
|
pin = P18;
|
|
pin_neg = P25;
|
|
chn_sel = 0x01;
|
|
*(volatile int*)(0x4000F020) = 0x0060;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
hal_gpio_ds_control(pin, Bit_ENABLE);
|
|
subWriteReg(&(AP_PCRM->ANA_CTL),7,5,chn_sel);
|
|
set_differential_mode();
|
|
//LOG("%d %d %x\n",pin,pin_neg,*(volatile int*)0x40003800);
|
|
hal_gpio_pull_set(pin,GPIO_FLOATING);
|
|
hal_gpio_pull_set(pin_neg,GPIO_FLOATING);
|
|
hal_gpio_cfg_analog_io(pin,Bit_ENABLE);
|
|
hal_gpio_cfg_analog_io(pin_neg,Bit_ENABLE);
|
|
//LOG("%d %d %x\n",pin,pin_neg,*(volatile int*)0x40003800);
|
|
mAdc_Ctx.all_channel = (cfg.is_differential_mode >> 1);
|
|
mAdc_Ctx.evt_handler = evt_handler;
|
|
}
|
|
|
|
return PPlus_SUCCESS;
|
|
}
|
|
|
|
int hal_adc_stop(void)
|
|
{
|
|
int i;
|
|
uint8_t all_channel2 = (((mAdc_Ctx.chs_en_shadow&0x80)>>1)|\
|
|
((mAdc_Ctx.chs_en_shadow&0x40)<<1)|\
|
|
((mAdc_Ctx.chs_en_shadow&0x20)>>1)|\
|
|
((mAdc_Ctx.chs_en_shadow&0x10)<<1)|\
|
|
((mAdc_Ctx.chs_en_shadow&0x08)>>1)|\
|
|
((mAdc_Ctx.chs_en_shadow&0x04)<<1));
|
|
|
|
if(mAdc_Ctx.enable == FALSE)
|
|
{
|
|
return PPlus_ERR_NOT_REGISTED;
|
|
}
|
|
|
|
AP_AON->PMCTL2_1 = 0x00;
|
|
NVIC_DisableIRQ((IRQn_Type)ADCC_IRQn);
|
|
JUMP_FUNCTION(ADCC_IRQ_HANDLER) = 0;
|
|
AP_ADCC->intr_clear = 0x1FF;
|
|
|
|
AP_PCRM->ANA_CTL &= ~BIT(3);
|
|
|
|
#include "rf_phy_driver.h"
|
|
if(g_system_clk != SYS_CLK_DBL_32M)
|
|
{
|
|
AP_PCRM->CLKHF_CTL1 &= ~BIT(13);
|
|
}
|
|
|
|
for(i = MIN_ADC_CH; i<= MAX_ADC_CH; i++)
|
|
{
|
|
if(all_channel2 & BIT(i))
|
|
{
|
|
disable_analog_pin((adc_CH_t)i);
|
|
}
|
|
}
|
|
|
|
AP_PCRM->ANA_CTL &= ~BIT(0);//Power down analog LDO
|
|
hal_clk_reset(MOD_ADCC);
|
|
hal_clk_gate_disable(MOD_ADCC);
|
|
clear_adcc_cfg();
|
|
//enableSleep();
|
|
hal_pwrmgr_unlock(MOD_ADCC);
|
|
return PPlus_SUCCESS;
|
|
}
|
|
|
|
|
|
#if(SDK_VER_CHIP==__DEF_CHIP_QFN32__)
|
|
const unsigned int adc_Lambda[MAX_ADC_CH - MIN_ADC_CH + 1] =
|
|
{
|
|
4519602,//P11
|
|
4308639,//P23
|
|
4263287,//P24
|
|
4482718,//P14
|
|
4180401,//P15
|
|
4072069,//P20
|
|
};
|
|
|
|
#elif(SDK_VER_CHIP == __DEF_CHIP_TSOP16__)
|
|
const unsigned int adc_Lambda[MAX_ADC_CH - MIN_ADC_CH + 1] =
|
|
{
|
|
4488156,//P11
|
|
4308639,//P23,
|
|
4263287,//P24,
|
|
4467981,//P14
|
|
4142931,//P15
|
|
4054721,//P20
|
|
};
|
|
#endif
|
|
|
|
float hal_adc_value_cal(adc_CH_t ch,uint16_t* buf, uint32_t size, uint8_t high_resol, uint8_t diff_mode)
|
|
{
|
|
uint32_t i;
|
|
int adc_sum = 0;
|
|
volatile float result = 0.0;
|
|
uint16_t adc_cal_postive = mAdc_Ctx.adc_cal_postive;
|
|
uint16_t adc_cal_negtive = mAdc_Ctx.adc_cal_negtive;
|
|
|
|
for (i = 0; i < size; i++)
|
|
{
|
|
adc_sum += (buf[i]&0xfff);
|
|
}
|
|
result = ((float)adc_sum)/size;
|
|
if((adc_cal_postive != 0xfff) && (adc_cal_negtive != 0xfff))
|
|
{
|
|
float delta = ((int)(adc_cal_postive-adc_cal_negtive))/2.0;
|
|
|
|
if(ch&0x01)
|
|
{
|
|
result = (diff_mode) ? ((result-2048-delta)*2/(adc_cal_postive+adc_cal_negtive))
|
|
: ((result-delta) /(adc_cal_postive+adc_cal_negtive));
|
|
}
|
|
else
|
|
{
|
|
result = (diff_mode) ? ((result-2048-delta)*2/(adc_cal_postive+adc_cal_negtive))
|
|
: ((result+delta) /(adc_cal_postive+adc_cal_negtive));
|
|
}
|
|
}
|
|
else
|
|
{
|
|
result = (diff_mode) ? (float)(result / 2048 -1) : (float)(result /4096);
|
|
}
|
|
|
|
if(high_resol == TRUE)
|
|
{
|
|
result *= 800.0;
|
|
}
|
|
else
|
|
{
|
|
result = (float)result *(float)adc_Lambda[ch-2]*0.8/1000;
|
|
}
|
|
return result;
|
|
}
|