add regs AP_AON, correct flash addrs
This commit is contained in:
pvvx
parent
a2f532f3a9
commit
d0fe0ff961
16 changed files with 8493 additions and 8466 deletions
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
Binary file not shown.
BIN
bin/TH05_v12.bin
BIN
bin/TH05_v12.bin
Binary file not shown.
BIN
bin/THB2_v12.bin
BIN
bin/THB2_v12.bin
Binary file not shown.
|
|
@ -219,7 +219,7 @@ void hal_rc32k_clk_tracking_init(void)
|
|||
__ATTR_SECTION_XIP__ void hal_rfPhyFreqOff_Set(void)
|
||||
{
|
||||
int32_t freqPpm=0;
|
||||
freqPpm= *(volatile int32_t*) 0x11004008;
|
||||
freqPpm= *(volatile int32_t*) CHIP_RFEQ_OFF_FLASH_ADDRESS; // было 0x11004008
|
||||
|
||||
if((freqPpm!=-1) && (freqPpm>=-50) && (freqPpm<=50))
|
||||
{
|
||||
|
|
@ -234,7 +234,7 @@ __ATTR_SECTION_XIP__ void hal_rfPhyFreqOff_Set(void)
|
|||
__ATTR_SECTION_XIP__ void hal_xtal16m_cap_Set(void)
|
||||
{
|
||||
uint32_t cap=0;
|
||||
cap= *(volatile int32_t*) 0x1100400c;
|
||||
cap= *(volatile int32_t*) CHIP_XTAK_CAP_FLASH_ADDRESS; // было 0x1100400c
|
||||
|
||||
if((cap!=0xffffffff) && (cap <= 0x1f))
|
||||
{
|
||||
|
|
|
|||
|
|
@ -105,6 +105,8 @@ extern void WaitRTCCount(uint32_t rtcDelyCnt);
|
|||
extern int clk_spif_ref_clk(sysclk_t spif_ref_sel);
|
||||
extern uint32_t getMcuPrecisionCount(void);
|
||||
|
||||
#define CHIP_RFEQ_OFF_FLASH_ADDRESS 0x11001e08
|
||||
#define CHIP_XTAK_CAP_FLASH_ADDRESS 0x11001e0c
|
||||
void hal_rfPhyFreqOff_Set(void);
|
||||
void hal_xtal16m_cap_Set(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -163,7 +163,7 @@ int hal_dma_config_channel(DMA_CH_t ch, DMA_CH_CFG_t* cfg)
|
|||
transf_per = DMA_DMACCxConfig_DestPeripheral(dst_conn-1);
|
||||
}
|
||||
|
||||
if((cfg->dst_addr > 0x11000000) && (cfg->dst_addr <= 0x11080000))
|
||||
if((cfg->dst_addr > 0x11000000) && (cfg->dst_addr <= 0x11080000)) // 512 k
|
||||
{
|
||||
pctx->xmit_flash = DMA_DST_XIMT_IS_FLASH;
|
||||
|
||||
|
|
|
|||
|
|
@ -417,7 +417,7 @@ int hal_pwrmgr_LowCurrentLdo_enable(void)
|
|||
{
|
||||
#ifdef CFG_SRAM_RETENTION_LOW_CURRENT_LDO_ENABLE
|
||||
uint32_t retention_flag;
|
||||
hal_flash_read(0x1100181c,(uint8_t*)&retention_flag,4);
|
||||
hal_flash_read(CHIP_RETENTION_FLG_FLASH_ADDRESS,(uint8_t*)&retention_flag,4);
|
||||
|
||||
if(retention_flag == 0xffffffff)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -46,7 +46,7 @@ typedef struct
|
|||
uint8_t moudle_num:5;
|
||||
} PWRMGR_CFG_BIT;
|
||||
|
||||
|
||||
#define CHIP_RETENTION_FLG_FLASH_ADDRESS 0x1100181c
|
||||
|
||||
extern uint32_t g_system_reset_cause;
|
||||
extern sysclk_t g_system_clk_change;
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ typedef struct
|
|||
__IO uint32_t SW_RESET1; //0x4
|
||||
__IO uint32_t SW_CLK; //0x8
|
||||
__IO uint32_t SW_RESET2; //0xc
|
||||
__IO uint32_t SW_RESET3; //0x10
|
||||
__IO uint32_t SW_RESET3; //0x10 bit 1: M0 cpu reset pulse, bit 0: M0 system reset pulse.
|
||||
__IO uint32_t SW_CLK1; //0x14
|
||||
__IO uint32_t APB_CLK; //0x18
|
||||
__IO uint32_t APB_CLK_UPDATE; //0x1c
|
||||
|
|
@ -464,28 +464,45 @@ typedef struct
|
|||
} IOMUX_TypeDef;
|
||||
|
||||
|
||||
// 0x4000f05C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
|
||||
// 0x4000f064 - RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
|
||||
// uint32_t counter_tracking // 24bit tracking counter, read from 0x4000f064
|
||||
// counter_tracking = g_counter_traking_avg = STD_RC32_16_CYCLE_16MHZ_CYCLE; hal_rc32k_clk_tracking_init()
|
||||
// 0x4000f0C0 - SLEEP_R[0] flags =2 RSTC_OFF_MODE, =4 RSTC_WARM_NDWC
|
||||
// 0x4000f0C4 - SLEEP_R[1] bit7 - first wakeupinit, tracking flags
|
||||
// 0x4000f0C8 - SLEEP_R[2] использую для сохранения UTC счета времени при перезагрузке
|
||||
// 0x4000f0CС - SLEEP_R[3] использую для сохранения UTC счета времени при перезагрузке
|
||||
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t PWROFF; //0x00
|
||||
__IO uint32_t PWRSLP; //0x04
|
||||
__IO uint32_t PWROFF; //0x00 = 0x5a5aa5a5 enter system off mode
|
||||
__IO uint32_t PWRSLP; //0x04 = 0xa5a55a5a system sleep mode
|
||||
__IO uint32_t IOCTL[3]; //0x08 0x0c 0x10
|
||||
__IO uint32_t PMCTL0; //0x14
|
||||
__IO uint32_t PMCTL1; //0x18
|
||||
__IO uint32_t PMCTL2_0; //0x1c
|
||||
__IO uint32_t PMCTL2_0; //0x1c bit6 enable software control 32k_clk
|
||||
__IO uint32_t PMCTL2_1; //0x20
|
||||
__IO uint32_t RTCCTL; //0x24
|
||||
__IO uint32_t RTCCNT; //0x28
|
||||
__IO uint32_t RTCCC0; //0x2c
|
||||
__IO uint32_t RTCCC1; //0x30
|
||||
__IO uint32_t RTCCC2; //0x34
|
||||
__IO uint32_t RTCFLAG; //0x38
|
||||
__IO uint32_t reserved[25];
|
||||
__IO uint32_t RTCCTL; //0x24 bit20 - enable comparator0 envent, bit18 counter overflow interrupt, bit15 enable comparator0 inerrupt,
|
||||
__IO uint32_t RTCCNT; //0x28 current RTC counter
|
||||
__IO uint32_t RTCCC0; //0x2c
|
||||
__IO uint32_t RTCCC1; //0x30
|
||||
__IO uint32_t RTCCC2; //0x34
|
||||
__IO uint32_t RTCFLAG; //0x38
|
||||
__IO uint32_t RTCCLK0; //0x3C bit3:0 = sysclk_t: 1 dll 32m, 2 xtal 16m, 3 dll 48m, 4 dll 64m, 5 dll 96m
|
||||
__IO uint32_t RTCCLK1; //0x40 bit18 - xtal output to digital enable
|
||||
__IO uint32_t RTCCFG1; //0x44 - [bit16] enable digclk 96M, [bit7] enable DLL, 25:24 g_rxAdcClkSel 26:25 sel_rxadc_dbl_clk_32M_polarity, 23:22 g_rfPhyClkSel, 6:5 trim dll/dbl ldo vout
|
||||
__IO uint32_t reserved0[5]; //0x48 4c 50 54 58
|
||||
__IO uint32_t RTCCFG2; //0x5C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
|
||||
__IO uint32_t reserved1; //0x60
|
||||
__IO uint32_t RTCTRWPCNT; //0x64 counter_tracking_wakeup
|
||||
__IO uint32_t RTCTRCNT; //0x68 RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
|
||||
__IO uint32_t reserved2[13]; //0x6c 70 74 78 7c 80 84 88 8c 90 94 98 9c
|
||||
__IO uint32_t REG_S9; //0xa0
|
||||
__IO uint32_t REG_S10; //0xa4
|
||||
__IO uint32_t REG_S11; //0xa8
|
||||
__IO uint32_t IDLE_REG; //0xac
|
||||
__IO uint32_t REG_S11; //0xa8 bit0 sleep_flag
|
||||
__IO uint32_t IDLE_REG; //0xac
|
||||
__IO uint32_t GPIO_WAKEUP_SRC[2]; //0xb0 b4
|
||||
__IO uint32_t PCLK_CLK_GATE; //0xb8
|
||||
__IO uint32_t PCLK_CLK_GATE; //0xb8 bit0 pclk_clk_gate_en
|
||||
__IO uint32_t XTAL_16M_CTRL; //0xbc
|
||||
__IO uint32_t SLEEP_R[4]; //0xc0 c4 c8 cc
|
||||
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
#include "rf_phy_driver.h"
|
||||
#include "time.h"
|
||||
|
||||
#define OWN_PUBLIC_ADDR_POS 0x11004000
|
||||
//#define OWN_PUBLIC_ADDR_POS 0x11004000
|
||||
|
||||
extern void clear_timer(AP_TIM_TypeDef* TIMx);
|
||||
extern uint32_t get_timer_count(AP_TIM_TypeDef* TIMx);
|
||||
|
|
|
|||
|
|
@ -64,7 +64,6 @@ static uint8 bSleepAllow = TRUE;
|
|||
|
||||
volatile uint32_t forever_write;
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
EXTERNAL VARIABLES
|
||||
*/
|
||||
|
|
@ -115,7 +114,6 @@ Sleep_Mode getSleepMode(void)
|
|||
|
||||
////////////////////////////
|
||||
// process of enter system sleep mode
|
||||
|
||||
/*******************************************************************************
|
||||
@fn enterSleepProcess0
|
||||
|
||||
|
|
@ -563,5 +561,3 @@ void enter_sleep_off_mode0(Sleep_Mode mode)
|
|||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -5233,7 +5233,7 @@ void ll_scheduler1(uint32 time)
|
|||
#define TRACKING_16M_TICK_MAX (3300) //TRACKING_16M_TICK_MAX*30.5us 3300*30.5 around 100ms
|
||||
#define TRACKING_MAX_SLEEPTIME (1980000) //MAX sleep time is 60 seconds.
|
||||
|
||||
uint32_t g_xtal16M_tmp=0;
|
||||
uint32_t g_xtal16M_tmp=0; // RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
|
||||
extern void hal_pwrmgr_enter_sleep_rtc_reset(uint32_t sleepRtcTick);
|
||||
static void check_16MXtal_by_rcTracking(void)
|
||||
{
|
||||
|
|
@ -5247,21 +5247,23 @@ static void check_16MXtal_by_rcTracking(void)
|
|||
return;
|
||||
}
|
||||
|
||||
uint32_t temp,temp1;
|
||||
uint32_t temp;
|
||||
uint32_t temp31,temp32,temp33;
|
||||
uint32_t temp_min,temp_max;
|
||||
uint32_t tracking_start = rtc_get_counter();
|
||||
// ======== enable tracking 32KHz RC timer with 16MHz crystal clock
|
||||
temp = *(volatile uint32_t*)0x4000f040;
|
||||
*(volatile uint32_t*)0x4000f040 = temp | BIT(18);
|
||||
temp = *(volatile uint32_t*)0x4000f05C;
|
||||
*(volatile uint32_t*)0x4000f05C = (temp & 0xfffefe00) | 0x0028;
|
||||
AP_AON->RTCCLK0 |= BIT(18);
|
||||
//temp = *(volatile uint32_t*)0x4000f040;
|
||||
//*(volatile uint32_t*)0x4000f040 = temp | BIT(18);
|
||||
// [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
|
||||
AP_AON->RTCCFG2 = (AP_AON->RTCCFG2 & 0xfffefe00) | 0x0028;
|
||||
WaitRTCCount(3);
|
||||
temp31 = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
// 0x4000f064 - RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
|
||||
temp31 = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
WaitRTCCount(3);
|
||||
temp32 = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
temp32 = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
WaitRTCCount(3);
|
||||
temp33 = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
temp33 = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
|
||||
while(1)
|
||||
{
|
||||
|
|
@ -5289,7 +5291,7 @@ static void check_16MXtal_by_rcTracking(void)
|
|||
temp31= temp32;
|
||||
temp32 = temp33;
|
||||
WaitRTCCount(3);
|
||||
temp33 = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
temp33 = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
//check tracking cost
|
||||
uint32_t tracking_end = rtc_get_counter();
|
||||
uint32_t tracking_16M_tick = (tracking_end>=tracking_start) ? (tracking_end-tracking_start) : (0xffffffff-tracking_start+tracking_end);
|
||||
|
|
@ -5315,10 +5317,10 @@ static void check_16MXtal_by_rcTracking(void)
|
|||
}
|
||||
|
||||
WaitRTCCount(20);
|
||||
temp1 = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
temp = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
//disable tracking
|
||||
subWriteReg(0x4000f05C,3,3,0);
|
||||
g_xtal16M_tmp = temp1;
|
||||
AP_AON->RTCCFG2 &= ~BIT(3); // subWriteReg(0x4000f05C,3,3,0);
|
||||
g_xtal16M_tmp = temp;
|
||||
}
|
||||
|
||||
#define TRACKING_96M_16M_MULTI6_DELTA_LIMIT (10*6) //96M:16M*6 +- 1%
|
||||
|
|
@ -5331,54 +5333,56 @@ static void check_96MXtal_by_rcTracking(void)
|
|||
uint32_t temp,temp1;
|
||||
|
||||
//for first wakeupinit
|
||||
if(((*(volatile uint32_t*)0x4000f0c4) & 0x80) == 0)
|
||||
if((AP_AON->SLEEP_R[1] & 0x80) == 0)
|
||||
{
|
||||
//enable DLL
|
||||
temp = *(volatile uint32_t*)0x4000f044;
|
||||
*(volatile uint32_t*)0x4000f044 = temp | BIT(7);
|
||||
AP_AON->RTCCFG1 |= BIT(7); // temp = *(volatile uint32_t*)0x4000f044;
|
||||
// *(volatile uint32_t*)0x4000f044 = temp | BIT(7);
|
||||
WaitRTCCount(3);
|
||||
return;
|
||||
}
|
||||
|
||||
DLL_enable_num=0;
|
||||
// ======== enable tracking 32KHz RC timer with 16MHz crystal clock
|
||||
temp = *(volatile uint32_t*)0x4000f040;
|
||||
*(volatile uint32_t*)0x4000f040 = temp | BIT(18);
|
||||
AP_AON->RTCCLK1 |= BIT(18);
|
||||
//temp = *(volatile uint32_t*)0x4000f040;
|
||||
//*(volatile uint32_t*)0x4000f040 = temp | BIT(18);
|
||||
|
||||
while(1)
|
||||
{
|
||||
//enable DLL
|
||||
temp = *(volatile uint32_t*)0x4000f044;
|
||||
*(volatile uint32_t*)0x4000f044 = temp | BIT(7);
|
||||
AP_AON->RTCCFG1 |= BIT(7);
|
||||
//temp = *(volatile uint32_t*)0x4000f044;
|
||||
//*(volatile uint32_t*)0x4000f044 = temp | BIT(7);
|
||||
WaitRTCCount(3);
|
||||
DLL_enable_num++;
|
||||
// gpio_write(P32,1);
|
||||
// gpio_write(P32,0);
|
||||
// //enable digclk 96M
|
||||
temp = *(volatile uint32_t*)0x4000f044;
|
||||
*(volatile uint32_t*)0x4000f044 = temp | BIT(16);
|
||||
// temp = *(volatile uint32_t*)0x4000f044;
|
||||
AP_AON->RTCCFG1 |= BIT(16); // *(volatile uint32_t*)0x4000f044 = temp | BIT(16);
|
||||
|
||||
for(uint8 index=0; index<5; index++)
|
||||
{
|
||||
temp = *(volatile uint32_t*)0x4000f05C;
|
||||
*(volatile uint32_t*)0x4000f05C = (temp & 0xfffefe00) | 0x0028 | BIT(16);
|
||||
temp = AP_AON->RTCCFG2;
|
||||
// [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
|
||||
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0028 | BIT(16);
|
||||
WaitRTCCount(3);
|
||||
temp1 = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
subWriteReg(0x4000f05C,3,3,0);
|
||||
|
||||
temp1 = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
AP_AON->RTCCFG2 &= ~BIT(3); //disable tracking subWriteReg(0x4000f05C,3,3,0);
|
||||
if( (g_xtal16M_tmp*6 >=temp1 ? (g_xtal16M_tmp*6 -temp1):(temp1-g_xtal16M_tmp*6))<TRACKING_96M_16M_MULTI6_DELTA_LIMIT)
|
||||
{
|
||||
//disable 96M
|
||||
subWriteReg(0x4000f05C,16,16,0);
|
||||
subWriteReg(0x4000f044,16,16,0);
|
||||
AP_AON->RTCCFG2 &= ~BIT(16); // disable 16M subWriteReg(0x4000f05C,16,16,0);
|
||||
AP_AON->RTCCFG1 &= ~BIT(16); // subWriteReg(0x4000f044,16,16,0);
|
||||
g_xtal96M_temp = temp1;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
//disable 96M
|
||||
subWriteReg(0x4000f05C,16,16,0);
|
||||
subWriteReg(0x4000f044,16,16,0);
|
||||
AP_AON->RTCCFG2 &= ~BIT(16); // disable 16M subWriteReg(0x4000f05C,16,16,0);
|
||||
AP_AON->RTCCFG1 &= ~BIT(16); // div? subWriteReg(0x4000f044,16,16,0);
|
||||
|
||||
//should not be here
|
||||
if(DLL_enable_num>= DLL_ENABLE_MAX)
|
||||
|
|
@ -5387,14 +5391,16 @@ static void check_96MXtal_by_rcTracking(void)
|
|||
}
|
||||
|
||||
//disable DLL
|
||||
subWriteReg(0x4000f044,7,7,0);
|
||||
AP_AON->RTCCFG1 &= ~BIT(7);
|
||||
WaitRTCCount(3);
|
||||
//update g_xtal16M_tmp
|
||||
temp = *(volatile uint32_t*)0x4000f05C;
|
||||
*(volatile uint32_t*)0x4000f05C = (temp & 0xfffefe00) | 0x0028 ;
|
||||
temp = AP_AON->RTCCFG2;
|
||||
// [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
|
||||
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0028 ;
|
||||
WaitRTCCount(3);
|
||||
g_xtal16M_tmp = (*(volatile uint32_t*)0x4000f064 & 0x1ffff);
|
||||
subWriteReg(0x4000f05C,3,3,0);
|
||||
// RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
|
||||
g_xtal16M_tmp = AP_AON->RTCTRCNT & 0x1ffff;
|
||||
AP_AON->RTCCFG2 &= ~BIT(3); //disable tracking subWriteReg(0x4000f05C,3,3,0);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -5491,7 +5497,7 @@ void wakeup_init1()
|
|||
for hclk=32M DBL
|
||||
switch to 32M RC and reset DBL
|
||||
*/
|
||||
if((read_reg(0x4000f03c)&0x07)==SYS_CLK_DBL_32M)
|
||||
if((AP_AON->RTCCLK0 & 0x07)==SYS_CLK_DBL_32M)
|
||||
{
|
||||
clk_init(SYS_CLK_RC_32M);
|
||||
}
|
||||
|
|
@ -5567,15 +5573,17 @@ void wakeup_init1()
|
|||
ll_hw_set_timing(pktFmt);
|
||||
ll_hw_ign_rfifo(LL_HW_IGN_SSN | LL_HW_IGN_CRC | LL_HW_IGN_EMP);
|
||||
// ======== enable tracking 32KHz RC timer with 16MHz crystal clock
|
||||
temp = *(volatile uint32_t*)0x4000f05C;
|
||||
*(volatile uint32_t*)0x4000f05C = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k
|
||||
temp = AP_AON->RTCCFG2;
|
||||
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k
|
||||
//get wakeup tracking counter
|
||||
// if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW)
|
||||
// {
|
||||
// WaitRTCCount(17);
|
||||
// uint32_t counter_tracking_wakeup = *(volatile uint32_t *)0x4000f064 & 0x1ffff;
|
||||
// counter_tracking = (counter_tracking_wakeup + counter_tracking)>>1;
|
||||
// }
|
||||
#if 0
|
||||
if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW)
|
||||
{
|
||||
WaitRTCCount(17);
|
||||
uint32_t counter_tracking_wakeup = AP_AON->RTCTRWPCNT; // *(volatile uint32_t *)0x4000f064 & 0x1ffff;
|
||||
counter_tracking = (counter_tracking_wakeup + counter_tracking)>>1;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
void config_RTC1(uint32 time)
|
||||
|
|
@ -5588,10 +5596,11 @@ void config_RTC1(uint32 time)
|
|||
// comparator configuration
|
||||
#if TEST_RTC_DELTA
|
||||
do
|
||||
sleep_tick = *(volatile uint32_t*) 0x4000f028; // read current RTC counter
|
||||
while(sleep_tick != *(volatile uint32_t*) 0x4000f028);
|
||||
sleep_tick = AP_AON->RTCCNT; // read current RTC counter
|
||||
while(sleep_tick != AP_AON->RTCCNT);
|
||||
#else
|
||||
sleep_tick = *(volatile uint32_t*) 0x4000f028; // read current RTC counter
|
||||
sleep_tick = AP_AON->RTCCNT; // *(volatile uint32_t*) 0x4000f028; read current RTC counter
|
||||
|
||||
#endif
|
||||
g_TIM2_IRQ_to_Sleep_DeltTick = (g_TIM2_IRQ_TIM3_CurrCount>(AP_TIM3->CurrentCount))
|
||||
? (g_TIM2_IRQ_TIM3_CurrCount-(AP_TIM3->CurrentCount)): 0;
|
||||
|
|
@ -5742,8 +5751,18 @@ void wakeupProcess1(void)
|
|||
// sleep_total = ((((dlt_tick &0xffff0000)>>16)*counter_tracking)<<9)
|
||||
// + (((dlt_tick &0xffff)*counter_tracking)>>7);
|
||||
//counter_tracking default 16 cycle
|
||||
#if TEST_RTC_DELTA
|
||||
// надо перевести в systick 625us
|
||||
// dlt_tick - в 1/32768
|
||||
// counter_tracking - в 16/32768
|
||||
// sleep_total = ;
|
||||
//counter_tracking = STD_RC32_8_CYCLE_16MHZ_CYCLE;
|
||||
sleep_total = ((((dlt_tick &0xffff0000)>>16)*counter_tracking)<<8)
|
||||
+ (((dlt_tick &0xffff)*counter_tracking)>>8);
|
||||
#else
|
||||
sleep_total = ((((dlt_tick &0xffff0000)>>16)*counter_tracking)<<8)
|
||||
+ (((dlt_tick &0xffff)*counter_tracking)>>8);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -7847,7 +7866,7 @@ void init_config(void)
|
|||
pGlobal_config[LL_MASTER_PROCESS_TARGET] = 200; // reserve time for preparing master conn event, delay should be insert if needn't so long time
|
||||
pGlobal_config[LL_MASTER_TIRQ_DELAY] = 0; // timer IRQ -> timer ISR delay
|
||||
pGlobal_config[OSAL_SYS_TICK_WAKEUP_TRIM] = 56; // 0.125us
|
||||
pGlobal_config[MAC_ADDRESS_LOC] = 0x11004000;
|
||||
pGlobal_config[MAC_ADDRESS_LOC] = 0x11001F00;
|
||||
// for simultaneous conn & adv/scan
|
||||
pGlobal_config[LL_NOCONN_ADV_EST_TIME] = 1400*3;
|
||||
pGlobal_config[LL_NOCONN_ADV_MARGIN] = 600;
|
||||
|
|
@ -8391,8 +8410,8 @@ __attribute__((aligned(4))) static uint8_t s_trng_iv[16];
|
|||
__ATTR_SECTION_XIP__ static void TRNG_Output(uint32_t* buf, uint8_t len)
|
||||
{
|
||||
uint32_t temp,temp1,status;
|
||||
temp = *(volatile uint32_t*)0x4000f05c;
|
||||
*(volatile uint32_t*)0x4000f05c = (temp & 0xfffefe00) | 0x0108;
|
||||
temp = AP_AON->RTCCFG2;
|
||||
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0108;
|
||||
|
||||
for(uint8_t j=0; j<len; j++)
|
||||
{
|
||||
|
|
@ -8401,8 +8420,8 @@ __ATTR_SECTION_XIP__ static void TRNG_Output(uint32_t* buf, uint8_t len)
|
|||
for(uint8_t i = 0; i<16; i++)
|
||||
{
|
||||
WaitRTCCount(17);
|
||||
temp1 = *(volatile uint32_t*)0x4000f064 & 0x1ffff;
|
||||
status |= ((temp1&0x03)<<(i<<1));
|
||||
temp1 = AP_AON->RTCTRCNT;
|
||||
status |= ((temp1 & 0x03)<<(i<<1));
|
||||
}
|
||||
|
||||
*buf++ = status;
|
||||
|
|
|
|||
|
|
@ -1340,7 +1340,7 @@ function parseBlkCustom(value) {
|
|||
let sDateTime = (dt.toISOString().slice(0, -5)).replace('T',' ');
|
||||
$('lblTime').innerHTML = sDateTime;
|
||||
let time = Date.now() / 1000 - (new Date()).getTimezoneOffset() * 60;
|
||||
let delta = devTime.cur - time;
|
||||
delta = devTime.cur - time;
|
||||
console.log('Время на устройстве: ' + sDateTime + ', Уход: ' + Math.round(delta) + ' сек');
|
||||
$('lbDeltaTime').innerHTML = 'Уход часов: ' + Math.round(delta) + ' сек';
|
||||
if(len > 18) {
|
||||
|
|
@ -1364,7 +1364,7 @@ function parseBlkCustom(value) {
|
|||
}
|
||||
);
|
||||
if(len < 15) getDevTime();
|
||||
if(delta > 10800 || delta < -10800) {
|
||||
if(delta > 86400 || delta < -86400) {
|
||||
addLog("Авто установка часов устройства...");
|
||||
setDevTime();
|
||||
}
|
||||
|
|
@ -1428,7 +1428,7 @@ function parseBlkCustom(value) {
|
|||
let s = bytesToHex(value.buffer.slice(5), len);
|
||||
$('inpData').value = s;
|
||||
addLog("Данные по адресу 0x" + hex(addr,8) + ': ' + s);
|
||||
showProgress("Считано: " + len + " байт из 0x" + hex(addr,8));
|
||||
//showProgress("Считано: " + len + " байт из 0x" + hex(addr,8));
|
||||
} else if((blkId == 0xda) && (len > 8)) {
|
||||
let addr = value.getUint32(1,true);
|
||||
let reg_data = value.getUint32(5,true);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue