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Start ver1.4, connection stabilization, RTC correction, ...

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pvvx 2024-02-22 08:33:49 +03:00
parent 5c4b98d06a
commit c20424752f
46 changed files with 15085 additions and 15966 deletions
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73
bthome_phy6222/Makefile
View file

@ -33,36 +33,57 @@ INCLUDES = -I$(SRC_PATH)
SRCS = $(addprefix $(SRC_PATH)/, $(SRC_PRJ))
##############################################################################
DEFINES = -D__GCC
DEFINES += -D__GCC
DEFINES += $(POJECT_DEF)
DEFINES += -DDEBUG_INFO=0
DEFINES += -DMTU_SIZE=247
#DEFINES += -DTEST_RTC_DELTA=1
DEFINES += -DCFG_SLEEP_MODE=PWR_MODE_SLEEP
DEFINES += -DADV_NCONN_CFG=0x01
DEFINES += -DADV_CONN_CFG=0x02
DEFINES += -DSCAN_CFG=0x04
DEFINES += -DINIT_CFG=0x08
DEFINES += -DBROADCASTER_CFG=0x01
DEFINES += -DOBSERVER_CFG=0x02
DEFINES += -DPERIPHERAL_CFG=0x04
DEFINES += -DCENTRAL_CFG=0x08
DEFINES += -DHOST_CONFIG=0x4
#DEFINES += -DCFG_SLEEP_MODE=PWR_MODE_NO_SLEEP
DEFINES += -DDEBUG_INFO=0
DEFINES += -DMTU_SIZE=240
DEFINES += -DMAX_NUM_LL_CONN=1
DEFINES += -DDEF_GAPBOND_MGR_ENABLE=0
#Debug:
DEFINES += -DTEST_RTC_DELTA=1
DEFINES += -DLL_DEBUG_NONE=1
DEFINES += -DCLK_16M_ONLY=1
DEFINES += -DSTACK_MAX_SRAM=1
#if Flash HS
#DEFINES += -DXFLASH_HIGH_SPEED=1
#HOST_CONFIG:
DEFINES += -DBROADCASTER_CFG=0x01
DEFINES += -DOBSERVER_CFG=0x02
DEFINES += -DPERIPHERAL_CFG=0x04
DEFINES += -DCENTRAL_CFG=0x08
DEFINES += -DHOST_CONFIG=0x04
DEFINES += -DARMCM0
@DEFINES += -D_RTE_
#DEFINES += -DCFG_CP
#DEFINES += -DOSAL_CBTIMER_NUM_TASKS=1 - > osal_cbtimer.h
#DEFINES += -DHCI_TL_NONE=1
DEFINES += -DOSAL_CBTIMER_NUM_TASKS=1
# osal_cbtimer.h
DEFINES += -DENABLE_LOG_ROM_=0
#osal_heap info:
DEFINES += -DOSALMEM_METRICS=0
DEFINES += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
#osal_snv.c:
DEFINES += -DUSE_FS=0
#Not used:
#DEFINES += -D_RTE_
#DEFINES += -DHCI_TL_NONE=1
#DEFINES += -D_OBJ_DIR_FOR_DTM_=0
#DEFINES += -DDBG_ROM_MAIN=0
DEFINES += -DAPP_CFG=0
DEFINES += -DOSALMEM_METRICS=0
DEFINES += -DPHY_MCU_TYPE=MCU_BUMBEE_M0
DEFINES += -DDEF_GAPBOND_MGR_ENABLE=0
DEFINES += -DUSE_FS=0
DEFINES += -DMAX_NUM_LL_CONN=1
#DEFINES += -DXFLASH_HIGH_SPEED=1
#DEFINES += -DOSALMEM_METRICS=0
#DEFINES += -DAPP_CFG=0
#DEFINES += -DCFG_CP
#CTRL_CONFIG:
#DEFINES += -DADV_NCONN_CFG=0x01
#DEFINES += -DADV_CONN_CFG=0x02
#DEFINES += -DSCAN_CFG=0x04
#DEFINES += -DINIT_CFG=0x08
##############################################################################
BIN_DIR = ./bin
OBJ_DIR = ./build
@ -217,8 +238,8 @@ SRCS += $(SDK_PATH)/components/profiles/Roles/gapgattserver.c
SRCS += $(SDK_PATH)/components/profiles/GATT/gattservapp.c
#SRCS += $(SDK_PATH)/components/profiles/DevInfo/devinfoservice.c
SRCS += $(SDK_PATH)/components/osal/snv/osal_snv.c
SRCS += $(SDK_PATH)/components/libraries/fs/fs.c
#SRCS += $(SDK_PATH)/components/osal/snv/osal_snv.c
#SRCS += $(SDK_PATH)/components/libraries/fs/fs.c
SRCS += $(SDK_PATH)/misc/jump_table.c

7
bthome_phy6222/SDK/components/ble/controller/ll_common.h
View file

@ -247,7 +247,12 @@ uint8 llCheckForLstoDuringSL( llConnState_t *connPtr );
// function in ll_hwItf.c
void ll_hw_process_RTO(uint32 ack_num);
void ll_debug_output(uint32 state);
#if defined(LL_DEBUG_NONE) && (LL_DEBUG_NONE == 1)
#define ll_debug_output(a)
#else
void _ll_debug_output(uint32 state);
#define ll_debug_output(a) _ll_debug_output(a)
#endif
void llAdjSlaveLatencyValue( llConnState_t *connPtr );

1
bthome_phy6222/SDK/components/driver/adc/adc.c
View file

@ -574,6 +574,7 @@ int hal_adc_stop(void)
AP_PCRM->ANA_CTL &= ~BIT(3);
#include "rf_phy_driver.h"
if(g_system_clk != SYS_CLK_DBL_32M)
{
AP_PCRM->CLKHF_CTL1 &= ~BIT(13);

8
bthome_phy6222/SDK/components/driver/clock/clock.c
View file

@ -199,7 +199,7 @@ void hal_system_soft_reset(void)
config reset casue as RSTC_WARM_NDWC
reset path walkaround dwc
*/
AP_AON->SLEEP_R[0]=4;
AP_AON->SLEEP_R[0] = 4;
AON_CLEAR_XTAL_TRACKING_AND_CALIB;
@ -212,8 +212,10 @@ void hal_rc32k_clk_tracking_init(void)
{
extern uint32 counter_tracking;
extern uint32_t g_counter_traking_avg;
counter_tracking = g_counter_traking_avg = STD_RC32_16_CYCLE_16MHZ_CYCLE;
AON_CLEAR_XTAL_TRACKING_AND_CALIB;
if(g_counter_traking_avg == 0) {
counter_tracking = g_counter_traking_avg = STD_RC32_16_CYCLE_16MHZ_CYCLE;
AON_CLEAR_XTAL_TRACKING_AND_CALIB;
}
}
__ATTR_SECTION_XIP__ void hal_rfPhyFreqOff_Set(void)

2
bthome_phy6222/SDK/components/driver/gpio/gpio.c
View file

@ -231,7 +231,7 @@ int hal_gpio_pin_init(gpio_pin_e pin, gpio_dir_t type)
{
AP_GPIO->swporta_ddr &= ~BIT(pin);
m_gpioCtx.pin_assignments[pin] = GPIO_PIN_ASSI_IN;
m_gpioCtx.pin_retention_status &= ~BIT(pin);
m_gpioCtx.pin_retention_status &= ~BIT(pin);
}
return PPlus_SUCCESS;

2
bthome_phy6222/SDK/components/driver/log/log.h
View file

@ -109,4 +109,4 @@ uint32_t log_get_debug_level(void);
#endif
#endif
#endif // ENABLE_LOG_ROM

9
bthome_phy6222/SDK/components/driver/pwrmgr/pwrmgr.c
View file

@ -21,7 +21,7 @@
static uint8_t mPwrMode = PWR_MODE_NO_SLEEP;
#elif(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
static uint8_t mPwrMode = PWR_MODE_SLEEP;
#elif(CFG_SLEEP_MODE == PWR_MODE_PWROFF_NO_SLEEP)
#elif(CFG_SLEEP_MODE == PWR_MODE_PWROFF_NO_SLEEP)
static uint8_t mPwrMode = PWR_MODE_PWROFF_NO_SLEEP;
#else
#error "CFG_SLEEP_MODE define incorrect"
@ -57,6 +57,7 @@ uint32_t s_config_swClk1 = DEF_CLKG_CONFIG_1;
#if(CFG_SLEEP_MODE == PWR_MODE_SLEEP)
uint32_t s_gpio_wakeup_src_group1,s_gpio_wakeup_src_group2;
extern void config_RTC1(uint32 time);
#endif
// /*
@ -423,7 +424,7 @@ int hal_pwrmgr_LowCurrentLdo_enable(void)
{
subWriteReg(0x4000f014,26,26, 1);
}
subWriteReg(0x4000f014,26,26, 1);
return PPlus_SUCCESS;
#else
subWriteReg(0x4000f014,26,26, 0);
@ -470,7 +471,7 @@ __ATTR_SECTION_SRAM__ void hal_pwrmgr_enter_sleep_rtc_reset(uint32_t sleepRtcTic
{
HAL_ENTER_CRITICAL_SECTION();
subWriteReg(0x4000f01c,6,6,0x00); //disable software control
config_RTC(sleepRtcTick);
config_RTC1(sleepRtcTick);
// clear sram retention
hal_pwrmgr_RAM_retention_clr();
/**
@ -478,7 +479,7 @@ __ATTR_SECTION_SRAM__ void hal_pwrmgr_enter_sleep_rtc_reset(uint32_t sleepRtcTic
reset path walkaround dwc
*/
AON_CLEAR_XTAL_TRACKING_AND_CALIB;
AP_AON->SLEEP_R[0]=4;
AP_AON->SLEEP_R[0] = 4;
enter_sleep_off_mode(SYSTEM_SLEEP_MODE);
while(1) {};

2
bthome_phy6222/SDK/components/driver/watchdog/watchdog.c
View file

@ -15,7 +15,7 @@ void hal_WATCHDOG_IRQHandler(void)
{
// volatile uint32_t a;
// a = AP_WDT->EOI;
AP_WDT->EOI;
AP_WDT->EOI;
AP_WDT->CRR = 0x76;
//LOG("WDT IRQ[%08x]\n",rtc_get_counter());
}

29
bthome_phy6222/SDK/components/inc/mcu_phy_bumbee.h
View file

@ -231,63 +231,38 @@ typedef struct
__IO uint8_t LCR; //0xc
uint8_t RESERVED1[3];//Reserved
__IO uint32_t MCR; //0x10
__I uint8_t LSR; //0x14
uint8_t RESERVED2[3];//Reserved
__IO uint32_t MSR; //0x18
__IO uint8_t SCR; //0x1c
uint8_t RESERVED3[3];//Reserved
__IO uint32_t LPDLL; //0x20
__IO uint32_t LPDLH; //0x24
__IO uint32_t recerved[2];
union
{
__IO uint32_t SRBR[16]; // 0x30~60xc
__IO uint32_t STHR[16];
};
__IO uint32_t FAR; //0x70
__IO uint32_t TFR; //0x74
__IO uint32_t RFW; // 0x78
__IO uint32_t USR; // 0x7c
__IO uint32_t TFL;
__IO uint32_t RFL;
__IO uint32_t SRR;
__IO uint32_t SRTS;
__IO uint32_t SBCR;
__IO uint32_t SDMAM;
__IO uint32_t SFE;
__IO uint32_t SRT;
__IO uint32_t STET; //0xa0
__IO uint32_t HTX;
__IO uint32_t DMASA; //0xa8
__IO uint32_t reserved[18];
__IO uint32_t CPR; //0xf4
__IO uint32_t UCV;
__IO uint32_t CTR;
} AP_UART_TypeDef;
@ -494,8 +469,8 @@ typedef struct
__IO uint32_t reserved0[5]; //0x48 4c 50 54 58
__IO uint32_t RTCCFG2; //0x5C - [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
__IO uint32_t reserved1; //0x60
__IO uint32_t RTCTRWPCNT; //0x64 counter_tracking_wakeup
__IO uint32_t RTCTRCNT; //0x68 RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
__IO uint32_t RTCTRCCNT; //0x64 RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle, counter_tracking_wakeup
__IO uint32_t RTCTRCNT; //0x68
__IO uint32_t reserved2[13]; //0x6c 70 74 78 7c 80 84 88 8c 90 94 98 9c
__IO uint32_t REG_S9; //0xa0
__IO uint32_t REG_S10; //0xa4

7
bthome_phy6222/SDK/components/profiles/Roles/gapgattserver.c
View file

@ -109,10 +109,15 @@ static uint8 periConnParamCharProps = GATT_PROP_READ;
// Peripheral Preferred Connection Parameters attribute (8 octets)
gapPeriConnectParams_t periConnParameters =
{
#if 1 // FIX_CONN_INTERVAL
DEFAULT_DESIRED_MIN_CONN_INTERVAL,
DEFAULT_DESIRED_MAX_CONN_INTERVAL,
DEFAULT_DESIRED_SLAVE_LATENCY,
DEFAULT_DESIRED_CONN_TIMEOUT };
DEFAULT_DESIRED_CONN_TIMEOUT
#else
8,80,0,1500
#endif
};
#endif // PERIPHERAL_CFG

10
bthome_phy6222/SDK/components/profiles/multiRole/multi.h
View file

@ -339,7 +339,7 @@ extern "C"
/* -------------------------------------------------------------------
macro define -- multi advertising schedule data update info config
uint8 bit.Number £º meaning
uint8 bit.Number <EFBFBD><EFBFBD> meaning
bit7-bit6:if set means advertising data or
sacn response data shall be updated before
make discoverable
@ -479,7 +479,7 @@ typedef struct
uint16 ExLatency;
uint16 ExTimeOut;
} common;
#if( MAX_CONNECTION_SLAVE_NUM > 0 )
#if( MAX_CONNECTION_SLAVE_NUM > 0 )
struct
{
uint8 EventType;
@ -487,8 +487,8 @@ typedef struct
uint8 FilterPolicy;
uint8 UpdateEnable;
} adv;
#endif
#if( MAX_CONNECTION_MASTER_NUM > 0 )
#endif
#if( MAX_CONNECTION_MASTER_NUM > 0 )
struct
{
uint8 maxScanRes;
@ -504,7 +504,7 @@ typedef struct
// bit value
uint16 actionAfterLink;
} link;
#endif
#endif
} GAPMultiRoleParam_t;
typedef enum

23
bthome_phy6222/SDK/lib/ble_controller/ll_sleep.c
View file

@ -138,7 +138,7 @@ void enterSleepProcess0(uint32 time)
if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW)
{
// 1. read RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
temp = *(volatile uint32_t*)0x4000f064 & 0x1ffff;
temp = AP_AON->RTCTRCCNT & 0x1ffff; // *(volatile uint32_t*)0x4000f064 & 0x1ffff;
// //====== assume the error cnt is (n+1/2) cycle,for this case, it should be 9 or 10
// //LOG("c %d\n",temp);
// error_delt = (temp>STD_CRY32_8_CYCLE_16MHZ_CYCLE)
@ -160,26 +160,27 @@ void enterSleepProcess0(uint32 time)
// temp = ((temp<<9)-(temp<<6)-(temp<<5)-(temp<<3)+(temp<<1)+2048)>>12;
// }
//check for the abnormal temp value
counter_tracking = (temp>CRY32_16_CYCLE_16MHZ_CYCLE_MAX) ? counter_tracking : temp;
counter_tracking = (temp > CRY32_16_CYCLE_16MHZ_CYCLE_MAX) ? counter_tracking : temp;
//20181204 filter the counter_tracking spur, due to the N+1 issue
if(g_counter_traking_cnt<1000)
if(g_counter_traking_cnt < 1000)
{
//before traking converage use hard limitation
counter_tracking = (counter_tracking>CRY32_16_CYCLE_16MHZ_CYCLE_MAX || counter_tracking<CRY32_16_CYCLE_16MHZ_CYCLE_MIN)
counter_tracking = (counter_tracking > CRY32_16_CYCLE_16MHZ_CYCLE_MAX
|| counter_tracking < CRY32_16_CYCLE_16MHZ_CYCLE_MIN)
? g_counter_traking_avg : counter_tracking;
g_counter_traking_cnt++;
}
else
{
//after tracking converage use soft limitation
counter_tracking = ( counter_tracking > g_counter_traking_avg+(g_counter_traking_avg>>8)
|| counter_tracking < g_counter_traking_avg-(g_counter_traking_avg>>8) )
counter_tracking = ( counter_tracking > g_counter_traking_avg + (g_counter_traking_avg >> 8)
|| counter_tracking < g_counter_traking_avg - (g_counter_traking_avg >> 8) )
? g_counter_traking_avg : counter_tracking;
}
//one order filer to tracking the average counter_tracking
g_counter_traking_avg = (7*g_counter_traking_avg+counter_tracking)>>3 ;
g_counter_traking_avg = (7 * g_counter_traking_avg + counter_tracking) >> 3;
// 2. adjust the time according to the bias
step = (counter_tracking) >> 3; // accurate step = 500 for 32768Hz timer
@ -191,7 +192,7 @@ void enterSleepProcess0(uint32 time)
while (total > step)
{
total -= step;
time --;
time--;
}
}
else // RTC is faster, should sleep more RTC tick
@ -202,7 +203,7 @@ void enterSleepProcess0(uint32 time)
while (total > step)
{
total -= step;
time ++;
time++;
}
}
}
@ -259,8 +260,8 @@ void config_RTC0(uint32 time)
#endif
//align to rtc clock edge
WaitRTCCount(1);
g_TIM2_IRQ_to_Sleep_DeltTick = (g_TIM2_IRQ_TIM3_CurrCount>(AP_TIM3->CurrentCount))
? (g_TIM2_IRQ_TIM3_CurrCount-(AP_TIM3->CurrentCount)): 0;
g_TIM2_IRQ_to_Sleep_DeltTick = (g_TIM2_IRQ_TIM3_CurrCount > (AP_TIM3->CurrentCount))
? (g_TIM2_IRQ_TIM3_CurrCount - (AP_TIM3->CurrentCount)) : 0;
AP_AON->RTCCC0 = sleep_tick + time; //set RTC comparatr0 value
// *(volatile uint32_t *) 0x4000f024 |= 1 << 20; //enable comparator0 envent
// *(volatile uint32_t *) 0x4000f024 |= 1 << 18; //counter overflow interrupt

48
bthome_phy6222/SDK/lib/ble_controller/rf_phy_driver.c
View file

@ -305,7 +305,7 @@ void rf_phy_ana_cfg(void)
}
subWriteReg(0x4000f044, 19, 18, 0x03); // Rx adc clk en, rf phy clk en
#if 0
#if 0
//Reserved?????
//20190111 ZQ
@ -320,7 +320,7 @@ void rf_phy_ana_cfg(void)
subWriteReg(0x4000f044,26,25, 0x00);
}
#endif
#endif
if(g_rfPhyClkSel==RF_PHY_CLK_SEL_16M_XTAL && g_system_clk == SYS_CLK_DLL_48M)
subWriteReg( 0x4003008c,23,23,0x01);
@ -508,7 +508,7 @@ void rf_phy_bb_cfg(uint8_t pktFmt)
PHY_REG_WT(0x4003006c, 0x4c2b3137);
PHY_REG_WT(0x40030070, 0x343a4046);
PHY_REG_WT(0x40030074, 0x1c22282e);
#if 0
#if 0
PHY_REG_WT( 0x40030054,0x545c9ca4 );
PHY_REG_WT( 0x40030058,0x03040c4c );
PHY_REG_WT( 0x4003005c,0x464c5202 );
@ -518,8 +518,8 @@ void rf_phy_bb_cfg(uint8_t pktFmt)
PHY_REG_WT( 0x4003006c,0x4c23292f );
PHY_REG_WT( 0x40030070,0x343a4046 );
PHY_REG_WT( 0x40030074,0x191f252b );
#endif
#if(RF_PHY_EXT_PREAMBLE_US)
#endif
#if(RF_PHY_EXT_PREAMBLE_US)
//ext preamble for BLE 1M/2M, nByte
if(pktFmt==PKT_FMT_BLE1M)
@ -596,7 +596,7 @@ void rf_phy_change_cfg0(uint8_t pktFmt)
PHY_REG_WT( 0x40030050,0x22085580);
}
#if(RF_PHY_EXT_PREAMBLE_US)
#if(RF_PHY_EXT_PREAMBLE_US)
//ext preamble for BLE 1M/2M, nByte
if(pktFmt==PKT_FMT_BLE1M)
@ -612,7 +612,7 @@ void rf_phy_change_cfg0(uint8_t pktFmt)
subWriteReg(0x40030040, 7, 5, (0) );
}
#endif
#endif
}
/**************************************************************************************
@fn rf_tp_cal
@ -662,7 +662,8 @@ uint8_t rf_tp_cal(uint8_t rfChn, uint8_t fDev)
// Wait to Read Reslut
// When HCLK 16M --> 10000*3/16 around 2ms
volatile int timeOut = 10000;
#if defined(CLK_16M_ONLY) && CLK_16M_ONLY != 0
#else
switch (g_system_clk)
{
// case SYS_CLK_XTAL_16M:
@ -673,19 +674,19 @@ uint8_t rf_tp_cal(uint8_t rfChn, uint8_t fDev)
case SYS_CLK_DBL_32M:
timeOut <<= 1;
break;
#if (PHY_MCU_TYPE == MCU_BUMBEE_M0 || PHY_MCU_TYPE == MCU_BUMBEE_CK802)
#if (PHY_MCU_TYPE == MCU_BUMBEE_M0 || PHY_MCU_TYPE == MCU_BUMBEE_CK802)
case SYS_CLK_4M:
break;
case SYS_CLK_8M:
break;
#elif ((PHY_MCU_TYPE == MCU_PRIME_A1) ||(PHY_MCU_TYPE == MCU_PRIME_A2))
#elif ((PHY_MCU_TYPE == MCU_PRIME_A1) ||(PHY_MCU_TYPE == MCU_PRIME_A2))
case SYS_CLK_DBL_32M:
timeOut <<= 1;
break;
#endif
#endif
case SYS_CLK_DLL_48M:
timeOut = (timeOut << 1) + timeOut;
@ -699,7 +700,7 @@ uint8_t rf_tp_cal(uint8_t rfChn, uint8_t fDev)
//timeOut = timeOut;
break;
}
#endif
while(timeOut--) {};
uint8_t kCal = (0xff0000 & PHY_REG_RD(0x400300f4))>>16;
@ -714,7 +715,7 @@ uint8_t rf_tp_cal(uint8_t rfChn, uint8_t fDev)
PHY_REG_WT( 0x40030040,0x00032800);
#if(RF_PHY_EXT_PREAMBLE_US)
#if(RF_PHY_EXT_PREAMBLE_US)
//ext preamble for BLE 1M/2M, nByte
if(g_rfPhyPktFmt==PKT_FMT_BLE1M)
@ -730,7 +731,7 @@ uint8_t rf_tp_cal(uint8_t rfChn, uint8_t fDev)
subWriteReg(0x40030040, 7, 5, (0) );
}
#endif
#endif
if(g_rfPhyClkSel==RF_PHY_CLK_SEL_16M_XTAL && g_system_clk == SYS_CLK_DLL_48M)
subWriteReg( 0x4003008c,23,23,0x01);
@ -1710,7 +1711,7 @@ void rf_phy_dtm_trigged(void)
//DCDC_CONFIG_SETTING(0x08);
if(!(g_rfPhyPktFmt==PKT_FMT_ZIGBEE))
{
#if 0
#if 0
//[15:8] payload Len [7:5] preamble len, [4] tx mode, [3:0] payload type
//PHY_REG_WT(0x40030040,(0x00030010|(g_dtmLength<<8)|(preambleLen<<5)|(0x0f & g_dtmPKT)) );
@ -1727,11 +1728,11 @@ void rf_phy_dtm_trigged(void)
PHY_REG_WT(0x40030040,(0x00030010|((g_dtmLength)<<8)|(preambleLen<<5)|(0x0f & g_dtmPKT)) );
}
#else
#else
ll_hw_rst_tfifo();
extern void rf_phy_dtm_ble_pkt_gen(void);
rf_phy_dtm_ble_pkt_gen();
#endif
#endif
}
else
{
@ -1986,7 +1987,6 @@ void rf_phy_set_txPower (uint8 txPower)
RF_PHY_LNA_LDO_SETTING(1);
RF_PHY_PA_VTRIM_SETTING(0);
}
PHY_REG_WT(0x400300b8,(PHY_REG_RD(0x400300b8)&0x0fff) | ((txPower&0x1f)<<12));
}
@ -2023,16 +2023,16 @@ uint8 rc32k_calibration(void)
uint8 delay = 10;
uint32_t temp=0;
*(volatile uint32_t*) 0x4000f05c &= 0xfffffffe; // disable RC32K calibration
*(volatile uint32_t*) 0x4000f05c &= 0xfffffffe; // disable RC32K calibration
WaitRTCCount(6);
// calibrate RC32K clock
*(volatile uint32_t*) 0x4000f018 |= 0x80; // set capbank controlled by calibration
*(volatile uint32_t*) 0x4000f05c |= 0x01; // enable RC32K calibration
*(volatile uint32_t*) 0x4000f018 |= 0x80; // set capbank controlled by calibration
*(volatile uint32_t*) 0x4000f05c |= 0x01; // enable RC32K calibration
while (!(*(volatile uint32_t*) 0x4000f068 & 0x200) // check RC32K calibration OK flag, normally need >200us
&& delay -- > 0)
while (!(*(volatile uint32_t*) 0x4000f068 & 0x200) // check RC32K calibration OK flag, normally need >200us
&& delay-- > 0)
{
WaitRTCCount(8);//30.125*8 us each loop
WaitRTCCount(8); // 30.125*8 us each loop
}
if (delay > 0)

336
bthome_phy6222/SDK/lib/rf/patch.c
View file

@ -5226,7 +5226,8 @@ void ll_scheduler1(uint32 time)
HAL_EXIT_CRITICAL_SECTION();
}
#if defined(CLK_16M_ONLY) && CLK_16M_ONLY != 0
#else
#define CRY32_2_CYCLE_16MHZ_CYCLE_MAX (976 + 98) // tracking value range std +/- 20%
#define CRY32_2_CYCLE_16MHZ_CYCLE_MIN (976 - 98)
#define CRY32_2_CYCLE_DELTA_LMT (19)
@ -5259,11 +5260,11 @@ static void check_16MXtal_by_rcTracking(void)
AP_AON->RTCCFG2 = (AP_AON->RTCCFG2 & 0xfffefe00) | 0x0028;
WaitRTCCount(3);
// 0x4000f064 - RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
temp31 = AP_AON->RTCTRCNT & 0x1ffff;
temp31 = AP_AON->RTCTRCCNT & 0x1ffff;
WaitRTCCount(3);
temp32 = AP_AON->RTCTRCNT & 0x1ffff;
temp32 = AP_AON->RTCTRCCNT & 0x1ffff;
WaitRTCCount(3);
temp33 = AP_AON->RTCTRCNT & 0x1ffff;
temp33 = AP_AON->RTCTRCCNT & 0x1ffff;
while(1)
{
@ -5291,7 +5292,7 @@ static void check_16MXtal_by_rcTracking(void)
temp31= temp32;
temp32 = temp33;
WaitRTCCount(3);
temp33 = AP_AON->RTCTRCNT & 0x1ffff;
temp33 = AP_AON->RTCTRCCNT & 0x1ffff;
//check tracking cost
uint32_t tracking_end = rtc_get_counter();
uint32_t tracking_16M_tick = (tracking_end>=tracking_start) ? (tracking_end-tracking_start) : (0xffffffff-tracking_start+tracking_end);
@ -5317,7 +5318,7 @@ static void check_16MXtal_by_rcTracking(void)
}
WaitRTCCount(20);
temp = AP_AON->RTCTRCNT & 0x1ffff;
temp = AP_AON->RTCTRCCNT & 0x1ffff;
//disable tracking
AP_AON->RTCCFG2 &= ~BIT(3); // subWriteReg(0x4000f05C,3,3,0);
g_xtal16M_tmp = temp;
@ -5328,6 +5329,7 @@ static void check_16MXtal_by_rcTracking(void)
uint32_t g_xtal96M_temp=0;
uint32_t DLL_enable_num=1;
static void check_96MXtal_by_rcTracking(void)
{
uint32_t temp,temp1;
@ -5368,7 +5370,7 @@ static void check_96MXtal_by_rcTracking(void)
// [bit16] 16M [bit8:4] cnt [bit3] track_en_rc32k
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0028 | BIT(16);
WaitRTCCount(3);
temp1 = AP_AON->RTCTRCNT & 0x1ffff;
temp1 = AP_AON->RTCTRCCNT & 0x1ffff;
AP_AON->RTCCFG2 &= ~BIT(3); //disable tracking subWriteReg(0x4000f05C,3,3,0);
if( (g_xtal16M_tmp*6 >=temp1 ? (g_xtal16M_tmp*6 -temp1):(temp1-g_xtal16M_tmp*6))<TRACKING_96M_16M_MULTI6_DELTA_LIMIT)
{
@ -5399,14 +5401,12 @@ static void check_96MXtal_by_rcTracking(void)
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0028 ;
WaitRTCCount(3);
// RC 32KHz tracking counter, calculate 16MHz ticks number per RC32KHz cycle
g_xtal16M_tmp = AP_AON->RTCTRCNT & 0x1ffff;
g_xtal16M_tmp = AP_AON->RTCTRCCNT & 0x1ffff;
AP_AON->RTCCFG2 &= ~BIT(3); //disable tracking subWriteReg(0x4000f05C,3,3,0);
}
}
#if 0
uint32_t rtcCntTemp[10];
#endif
// now we split the initial fucntion to 3 kinds:
// 1. boot init function: which should be init when system boot. note: not include wakeup init function
// 2. wakeup init function: which should be init when wakeup from system sleep
@ -5420,10 +5420,15 @@ static void check_96MXtal_by_rcTracking(void)
uint32_t tracking_cnt=0;
void wakeup_init1()
{
uint8_t pktFmt = PKT_FMT_BLE1M; // packet format 1: BLE 1M
uint32 temp;
efuse_init();
__wdt_init();
uint8_t pktFmt = 1; // packet format 1: BLE 1M
uint32 temp;
//sdk 3.1.3
//hal_system_clock_change_process();
//int int_state;
// =========== clk gate for low power
//*(volatile uint32_t *) 0x40000008 = 0x01e92190;
@ -5461,24 +5466,13 @@ void wakeup_init1()
#endif
//each rtc count is about 30.5us
//after 15count , xtal will be feedout to dll and doubler
//WaitRTCCount(pGlobal_config[WAKEUP_DELAY]);
#if 0
volatile uint32_t delay=0;
for(uint8_t i=0; i<10; i++)
{
delay=500;
rtcCntTemp[i]=rtc_get_counter();
while(delay -- > 0) {};
}
#endif
temp = AP_AON->RTCCFG2;
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k
#if defined(CLK_16M_ONLY) && CLK_16M_ONLY != 0
WaitRTCCount(pGlobal_config[WAKEUP_DELAY]);
#else
if(g_system_clk == SYS_CLK_XTAL_16M )
{
WaitRTCCount(pGlobal_config[WAKEUP_DELAY]);
}
else
{
uint32_t tracking_c1,tracking_c2;
@ -5512,7 +5506,7 @@ void wakeup_init1()
tracking_cnt = (tracking_c2>=tracking_c1) ? (tracking_c2-tracking_c1) : (0xffffffff-tracking_c1+tracking_c2);
pGlobal_config[WAKEUP_ADVANCE] =1650+30*tracking_cnt;
}
#endif
// ============ config BB Top
*(volatile uint32_t*) 0x40030000 = 0x3d068001; // set tx pkt =2
*(volatile uint32_t*) 0x400300bc = 0x834; //[7:0] pll_tm [11:8] rxafe settle
@ -5523,7 +5517,7 @@ void wakeup_init1()
// switch (pGlobal_config[CLOCK_SETTING])
// {
// case SYS_CLK_XTAL_16M:
//// *(int *) 0x4000f03C = 0x18001; // clock selection
//// *(int *) 0x4000f03C = 0x18001; // clock selection
// *(int *) 0x4000f03C = 0x10002; // clock selection
// break;
// case SYS_CLK_DBL_32M:
@ -5545,6 +5539,15 @@ void wakeup_init1()
// }
// ========== init timers
set_timer(AP_TIM2, 625); // OSAL 625us tick
if (1) { //sdk3.1.3
//restart the 625 timer
AP_TIM2->ControlReg = 0x0; //[0x40001014+8]=0
AP_TIM2->ControlReg = 0x2; //[0x40001014+8]=2
AP_TIM2->LoadCount = 2499; //[0x40001014]=2499
AP_TIM2->ControlReg = 0x3; //[0x40001014+8]=3
}
set_timer(AP_TIM3, BASE_TIME_UNITS); // 1s timer
// =========== open interrupt mask
//int_state = 0x14;
@ -5553,7 +5556,7 @@ void wakeup_init1()
NVIC_EnableIRQ(BB_IRQn);
NVIC_EnableIRQ(TIM1_IRQn);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_EnableIRQ(TIM4_IRQn);
NVIC_EnableIRQ(TIM4_IRQn); // нет в sdk3.1.3
// =========== ll HW setting
set_max_length(0xff);
ll_hw_set_empty_head(0x0001);
@ -5570,17 +5573,17 @@ void wakeup_init1()
// ll_hw_set_rx_tx_interval( 57); //T_IFS=150us for BLE 1M
// ll_hw_set_tx_rx_interval( 65); //T_IFS=150us for BLE 1M
// ll_hw_set_trx_settle (57, 8, 52); //TxBB,RxAFE,PLL
ll_hw_set_timing(pktFmt);
ll_hw_set_timing(pktFmt); // =PKT_FMT_BLE1M
ll_hw_ign_rfifo(LL_HW_IGN_SSN | LL_HW_IGN_CRC | LL_HW_IGN_EMP);
// ======== enable tracking 32KHz RC timer with 16MHz crystal clock
temp = AP_AON->RTCCFG2;
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k
// temp = AP_AON->RTCCFG2;
// AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0108; //[16] 16M [8:4] cnt [3] track_en_rc32k
//get wakeup tracking counter
#if 0
if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW)
{
WaitRTCCount(17);
uint32_t counter_tracking_wakeup = AP_AON->RTCTRWPCNT; // *(volatile uint32_t *)0x4000f064 & 0x1ffff;
uint32_t counter_tracking_wakeup = AP_AON->RTCTRCCNT; // *(volatile uint32_t *)0x4000f064 & 0x1ffff;
counter_tracking = (counter_tracking_wakeup + counter_tracking)>>1;
}
#endif
@ -5591,29 +5594,30 @@ void config_RTC1(uint32 time)
// *((volatile uint32_t *)(0xe000e100)) |= INT_BIT_RTC; // remove, we don't use RTC interrupt
//align to rtc clock edge
WaitRTCCount(1);
//update for cal ll next time after wakeup
ll_remain_time = read_LL_remainder_time();
// comparator configuration
#if TEST_RTC_DELTA
do
sleep_tick = AP_AON->RTCCNT; // read current RTC counter
while(sleep_tick != AP_AON->RTCCNT);
#else
sleep_tick = AP_AON->RTCCNT; // *(volatile uint32_t*) 0x4000f028; read current RTC counter
#endif
//update for cal ll next time after wakeup
ll_remain_time = read_LL_remainder_time();
// comparator configuration
g_TIM2_IRQ_to_Sleep_DeltTick = (g_TIM2_IRQ_TIM3_CurrCount > (AP_TIM3->CurrentCount))
? (g_TIM2_IRQ_TIM3_CurrCount - (AP_TIM3->CurrentCount)) : 0;
AP_AON->RTCCC0 = sleep_tick + time; //set RTC comparatr0 value
// *(volatile uint32_t *) 0x4000f024 |= 1 << 20; //enable comparator0 envent
// *(volatile uint32_t *) 0x4000f024 |= 1 << 18; //counter overflow interrupt
// *(volatile uint32_t *) 0x4000f024 |= 1 << 15; //enable comparator0 inerrupt
//*(volatile uint32_t *) 0x4000f024 |= 0x148000; // combine above 3 statement to save MCU time
AP_AON->RTCCTL |= BIT(15)|BIT(18)|BIT(20);
AP_AON->RTCCTL |= BIT(15)|BIT(18)|BIT(20); // |= 0x148000 combine above 3 statement to save MCU time
//compensate for cal wakeup next_time
if (llState != LL_STATE_IDLE)
{
#if defined(CLK_16M_ONLY) && CLK_16M_ONLY != 0
ll_remain_time -= 15;
#else
if(g_system_clk == SYS_CLK_XTAL_16M)
{
ll_remain_time -= 15;
@ -5630,6 +5634,7 @@ void config_RTC1(uint32 time)
{
ll_remain_time -= 3;
}
#endif
}
#if 0
@ -5670,26 +5675,26 @@ void wakeupProcess1(void)
//restore initial_sp according to the app_initial_sp : 20180706 ZQ
__set_MSP(pGlobal_config[INITIAL_STACK_PTR]);
HAL_CRITICAL_SECTION_INIT();
// All memory on
hal_pwrmgr_RAM_retention_clr();
//==== 20180416 commented by ZQ
// to enable flash access after wakeup
// current consumption has been checked. No big different
//rom_set_flash_deep_sleep();
#ifdef STACK_MAX_SRAM
//=======fix sram_rent issue 20180323
// All memory on
//hal_pwrmgr_RAM_retention_clr();
//subWriteReg(0x4000f01c,21,17,0);
subWriteReg(0x4000f01c,21,17,0);
#endif
if (sleep_flag != SLEEP_MAGIC)
{
// enter this branch not in sleep/wakeup scenario
set_sleep_flag(0);
// software reset
*(volatile uint32*)0x40000010 &= ~0x2; // bit 1: M0 cpu reset pulse, bit 0: M0 system reset pulse.
}
} else
set_sleep_flag(0); // sdk 3.1.3
// restore HW registers
wakeup_init1();
//===20180417 added by ZQ
@ -5699,30 +5704,31 @@ void wakeupProcess1(void)
//config the tx2rx timing according to the g_rfPhyPktFmt
ll_hw_tx2rx_timing_config(g_rfPhyPktFmt);
// 20200812 ZQ
// DO NOT Turn OFF 32K Xtal
// if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL)
// {
// subWriteReg(0x4000f01c,16,7,0x3fb); //software control 32k_clk
// subWriteReg(0x4000f01c,6,6 ,0x01); //enable software control
// }
// else
// {
// subWriteReg(0x4000f01c,9,8,0x03); //software control 32k_clk
// subWriteReg(0x4000f01c,6,6,0x00); //disable software control
// }
#if 0 // DO NOT Turn OFF 32K Xtal
if (pGlobal_config[LL_SWITCH] & LL_RC32K_SEL)
{
subWriteReg(0x4000f01c,16,7,0x3fb); //software control 32k_clk
subWriteReg(0x4000f01c,6,6 ,0x01); //enable software control
}
else
{
subWriteReg(0x4000f01c,9,8,0x03); //software control 32k_clk
subWriteReg(0x4000f01c,6,6,0x00); //disable software control
}
#endif
//20181201 by ZQ
//restart the TIM2 to align the RTC
//----------------------------------------------------------
//stop the 625 timer
AP_TIM2->ControlReg=0x0;
AP_TIM2->ControlReg=0x2;
AP_TIM2->LoadCount = 2500;
AP_TIM2->ControlReg = 0x0;
AP_TIM2->ControlReg = 0x2;
AP_TIM2->LoadCount = 2499;
//----------------------------------------------------------
//wait rtc cnt change
WaitRTCCount(1);
//----------------------------------------------------------
//restart the 625 timer
AP_TIM2->ControlReg=0x3;
AP_TIM2->ControlReg = 0x3;
current_RTC_tick = rtc_get_counter();
//g_TIM2_wakeup_delay= (AP_TIM2->CurrentCount)+12; //12 is used to align the rtc_tick
wakeup_time0 = read_current_fine_time();
@ -5730,59 +5736,52 @@ void wakeupProcess1(void)
// rf initial entry, will be set in app
rf_phy_ini();
if(current_RTC_tick>sleep_tick)
{
if(current_RTC_tick > sleep_tick)
dlt_tick = current_RTC_tick - sleep_tick;
}
else
{
//dlt_tick = current_RTC_tick+0x00ffffff - sleep_tick;
dlt_tick = (0xffffffff - sleep_tick)+current_RTC_tick;
}
dlt_tick = (0xffffffff - sleep_tick) + current_RTC_tick;
//dlt_tick += 2; //dlt_tick/190;
//dlt_tick should not over 24bit
//otherwise, sleep_total will overflow !!!
if(dlt_tick>0x3fffff)
dlt_tick &=0x3fffff;
if(dlt_tick > 0x3fffff)
dlt_tick &= 0x3fffff;
// calculate sleep_total in us
if (pGlobal_config[LL_SWITCH] & RC32_TRACKINK_ALLOW)
{
//sleep_total = ((current_RTC_tick - sleep_tick) * counter_tracking) >> 7; // shift 4 for 16MHz -> 1MHz, shift 3 for we count 8 RTC tick
// sleep_total = ((((dlt_tick &0xffff0000)>>16)*counter_tracking)<<9)
// + (((dlt_tick &0xffff)*counter_tracking)>>7);
// TEST_RTC_DELTA?
//counter_tracking default 16 cycle
// TEST_RTC_DELTA
sleep_total = ((((dlt_tick &0xffff0000)>>16)*counter_tracking)<<8)
+ (((dlt_tick &0xffff)*counter_tracking)>>8);
sleep_total = ((((dlt_tick & 0xffff0000) >> 16) * counter_tracking) << 8)
+ (((dlt_tick & 0xffff) * counter_tracking) >> 8);
}
else
{
// time = tick * 1000 0000 / f (us). f = 32000Hz for RC, f = 32768Hz for crystal. We also calibrate 32KHz RC to 32768Hz
//sleep_total = ((current_RTC_tick - sleep_tick) * TIMER_TO_32K_CRYSTAL) >> 2;
//fix sleep timing error
sleep_total = ( ( (dlt_tick<<7)-(dlt_tick<<2)-(dlt_tick<<1) +2) >>2 ) /* dlt_tick * (128-4-2)/4 */
+( ( (dlt_tick<<3)+ dlt_tick +128) >>9 ) ; /* dlt_tick *9/512 */
sleep_total = ( ( (dlt_tick << 7) - (dlt_tick << 2) - (dlt_tick << 1) + 2) >> 2 ) /* dlt_tick * (128-4-2)/4 */
+( ( (dlt_tick << 3) + dlt_tick +128) >> 9 ) ; /* dlt_tick *9/512 */
//+2,+128 for zero-mean quanization noise
}
// restore systick
g_osal_tick_trim = (pGlobal_config[OSAL_SYS_TICK_WAKEUP_TRIM]+g_TIM2_IRQ_to_Sleep_DeltTick+2500-g_TIM2_IRQ_PendingTick)>>2; //16 is used to compensate the cal delay
g_osalTickTrim_mod+=(pGlobal_config[OSAL_SYS_TICK_WAKEUP_TRIM]+g_TIM2_IRQ_to_Sleep_DeltTick+2500-g_TIM2_IRQ_PendingTick)&0x03; //16 is used to compensate the cal delay
g_osal_tick_trim = (pGlobal_config[OSAL_SYS_TICK_WAKEUP_TRIM] + g_TIM2_IRQ_to_Sleep_DeltTick + 2500 - g_TIM2_IRQ_PendingTick) >> 2; //16 is used to compensate the cal delay
g_osalTickTrim_mod += (pGlobal_config[OSAL_SYS_TICK_WAKEUP_TRIM] + g_TIM2_IRQ_to_Sleep_DeltTick + 2500 - g_TIM2_IRQ_PendingTick) & 0x03; //16 is used to compensate the cal delay
if(g_osalTickTrim_mod>4)
if(g_osalTickTrim_mod > 4)
{
g_osal_tick_trim+=1;
g_osalTickTrim_mod = g_osalTickTrim_mod%4;
g_osal_tick_trim += 1;
g_osalTickTrim_mod = g_osalTickTrim_mod % 4;
}
// restore systick
osal_sys_tick += (sleep_total+g_osal_tick_trim) / 625; // convert to 625us systick
rtc_mod_value += ((sleep_total+g_osal_tick_trim)%625);
osal_sys_tick += (sleep_total + g_osal_tick_trim) / 625; // convert to 625us systick
rtc_mod_value += ((sleep_total + g_osal_tick_trim) % 625);
if(rtc_mod_value > 625)
{
osal_sys_tick += 1;
rtc_mod_value = rtc_mod_value%625;
rtc_mod_value = rtc_mod_value % 625;
}
osalTimeUpdate();
@ -5832,16 +5831,19 @@ void wakeupProcess1(void)
g_llSleepContext.isTimer4RecoverRequired = FALSE;
}
#ifdef STACK_MAX_SRAM
__set_MSP((uint32_t)(&g_stack));
#endif
// app could add operation after wakeup
app_wakeup_process();
// uart_tx0(" 111 ");
ll_debug_output(DEBUG_WAKEUP);
set_sleep_flag(0);
// ==== measure value, from RTC counter meet comparator 0 -> here : 260us ~ 270us
// start task loop
osal_start_system();
osal_start_system(); // No Return from here
}
@ -7663,6 +7665,46 @@ llStatus_t LL_StartEncrypt1( uint16 connId,
return( LL_STATUS_SUCCESS );
}
////////////////////////////
// process of enter system sleep mode
/*******************************************************************************
@fn enterSleepProcess
@brief enter system sleep process function.
input parameters
@param time - sleep RTC ticks
output parameters
@param None.
@return None.
*/
void enterSleepProcess1(uint32 time)
{
uint32_t regtrck, regctl, temp;
int x;
regtrck = AP_AON->RTCTRCCNT & 0x1ffff; // [0x4000f064]
regctl = AP_AON->PMCTL1; // [0x4000F018]
if(regtrck >= 8203)
x = -2;
else if(regtrck <= 7420)
x = 2;
else {
enterSleepProcess0(time);
return;
}
// if (regctl & 0x7e) {
temp = regctl + x;
temp &= 0x7e;
if (temp)
AP_AON->PMCTL1 = (regctl & (~0x7e)) | temp;
// }
enterSleepProcess0(time);
}
// global configuration in SRAM, it could be change by application
// ================== VARIABLES ==================================
@ -7682,13 +7724,13 @@ void init_config(void)
//save the app initial_sp which will be used in wakeupProcess 20180706 by ZQ
pGlobal_config[INITIAL_STACK_PTR] = (uint32_t)(&g_irqstack_top);
// LL switch setting
pGlobal_config[LL_SWITCH] = LL_DEBUG_ALLOW | SLAVE_LATENCY_ALLOW | LL_WHITELIST_ALLOW
| SIMUL_CONN_ADV_ALLOW | SIMUL_CONN_SCAN_ALLOW; //RC32_TRACKINK_ALLOW
pGlobal_config[LL_SWITCH] = /*LL_DEBUG_ALLOW |*/ SLAVE_LATENCY_ALLOW | LL_WHITELIST_ALLOW
| SIMUL_CONN_ADV_ALLOW | SIMUL_CONN_SCAN_ALLOW;
if(g_clk32K_config == CLK_32K_XTAL)
pGlobal_config[LL_SWITCH] &= 0xffffffee;
else
pGlobal_config[LL_SWITCH] |= LL_RC32K_SEL | RC32_TRACKINK_ALLOW; // TODO: RTC 32000 Hz or 32768 Hz ?
pGlobal_config[LL_SWITCH] |= LL_RC32K_SEL | RC32_TRACKINK_ALLOW;
// sleep delay
pGlobal_config[MIN_TIME_TO_STABLE_32KHZ_XOSC] = 10; // 10ms, temporary set
@ -7703,25 +7745,19 @@ void init_config(void)
// WAKEUP_ADVANCE should be larger than t1+t2+t3+t4
//------------------------------------------------------------------------
// wakeup advance time, in us
pGlobal_config[WAKEUP_ADVANCE] = 1850;//650;//600;//310;
pGlobal_config[WAKEUP_ADVANCE] = 1850; //1850;//650;//600;//310;
if(g_system_clk==SYS_CLK_XTAL_16M)
{
pGlobal_config[WAKEUP_DELAY] = 16; //16;
/*
if(g_system_clk==SYS_CLK_XTAL_16M) 12520 e803
pGlobal_config[WAKEUP_DELAY] = 16;
}
else if(g_system_clk==SYS_CLK_DBL_32M)
{
pGlobal_config[WAKEUP_DELAY] = 16;
}
else if(g_system_clk==SYS_CLK_DLL_48M)
{
pGlobal_config[WAKEUP_DELAY] = 16;
}
else if(g_system_clk==SYS_CLK_DLL_64M)
{
pGlobal_config[WAKEUP_DELAY] = 16;
}
*/
// sleep time, in us
pGlobal_config[MAX_SLEEP_TIME] = 30000000;
pGlobal_config[MIN_SLEEP_TIME] = 1600;
@ -7775,31 +7811,11 @@ void init_config(void)
pGlobal_config[ADV_CHANNEL_INTERVAL] = 1400;//6250;
pGlobal_config[NON_ADV_CHANNEL_INTERVAL] = 666;//6250;
//20201207 Jie modify
if(g_system_clk==SYS_CLK_XTAL_16M)
{
// scan req -> scan rsp timing
pGlobal_config[SCAN_RSP_DELAY] = 13+RF_PHY_EXT_PREAMBLE_US;//23;
}
else if(g_system_clk==SYS_CLK_DBL_32M)
{
pGlobal_config[SCAN_RSP_DELAY] = 8+RF_PHY_EXT_PREAMBLE_US;//23;
}
else if(g_system_clk==SYS_CLK_DLL_48M)
{
// scan req -> scan rsp timing
pGlobal_config[SCAN_RSP_DELAY] = 6+RF_PHY_EXT_PREAMBLE_US;//20201207 set //4; // 12 // 2019/3/19 A2: 12 --> 9
}
else if(g_system_clk == SYS_CLK_DLL_64M) // 2019/3/26 add
{
pGlobal_config[SCAN_RSP_DELAY] = 4+RF_PHY_EXT_PREAMBLE_US;//2020.12.07 set //3;
}
// conn_req -> slave connection event calibration time, will advance the receive window
pGlobal_config[CONN_REQ_TO_SLAVE_DELAY] = 300;//192;//500;//192;
pGlobal_config[CONN_REQ_TO_SLAVE_DELAY] = 500; //было:300;//192;//500;//192;
// calibration time for 2 connection event, will advance the next conn event receive window
// SLAVE_CONN_DELAY for sync catch, SLAVE_CONN_DELAY_BEFORE_SYNC for sync not catch
pGlobal_config[SLAVE_CONN_DELAY] = 300;//0;//1500;//0;//3000;//0; ---> update 11-20
pGlobal_config[SLAVE_CONN_DELAY] = 1000; //было:300;//0;//1500;//0;//3000;//0; ---> update 11-20
pGlobal_config[SLAVE_CONN_DELAY_BEFORE_SYNC] = 500;//160 NG//500 OK
// RTLP timeout
pGlobal_config[LL_HW_RTLP_LOOP_TIMEOUT] = 50000;
@ -7826,28 +7842,40 @@ void init_config(void)
pGlobal_config[LL_SMART_WINDOW_FIRST_WINDOW] = 5000;
g_smartWindowSize = pGlobal_config[LL_HW_RTLP_1ST_TIMEOUT] ;
#if defined(CLK_16M_ONLY) && CLK_16M_ONLY != 0
// scan req -> scan rsp timing
pGlobal_config[SCAN_RSP_DELAY] = 13+RF_PHY_EXT_PREAMBLE_US;//21;
pGlobal_config[LL_ADV_TO_SCAN_REQ_DELAY] = 18+RF_PHY_EXT_PREAMBLE_US;//26; // 2019/3/19 A2: 20 --> 18
pGlobal_config[LL_ADV_TO_CONN_REQ_DELAY] = 25+RF_PHY_EXT_PREAMBLE_US;//33; // 2019/3/19 A2: 27 --> 25
#else
//====== A2 metal change add, for scanner & initiator
if(g_system_clk==SYS_CLK_XTAL_16M)
{
pGlobal_config[LL_ADV_TO_SCAN_REQ_DELAY] = 18+RF_PHY_EXT_PREAMBLE_US;//20; // 2019/3/19 A2: 20 --> 18
pGlobal_config[LL_ADV_TO_CONN_REQ_DELAY] = 25+RF_PHY_EXT_PREAMBLE_US;//27; // 2019/3/19 A2: 27 --> 25
// scan req -> scan rsp timing
pGlobal_config[SCAN_RSP_DELAY] = 13+RF_PHY_EXT_PREAMBLE_US;//21;
pGlobal_config[LL_ADV_TO_SCAN_REQ_DELAY] = 18+RF_PHY_EXT_PREAMBLE_US;//26; // 2019/3/19 A2: 20 --> 18
pGlobal_config[LL_ADV_TO_CONN_REQ_DELAY] = 25+RF_PHY_EXT_PREAMBLE_US;//33; // 2019/3/19 A2: 27 --> 25
}
else if(g_system_clk==SYS_CLK_DBL_32M)
{
pGlobal_config[SCAN_RSP_DELAY] = 8+RF_PHY_EXT_PREAMBLE_US;//16;
pGlobal_config[LL_ADV_TO_SCAN_REQ_DELAY] = 12+RF_PHY_EXT_PREAMBLE_US; // 2019/3/26 add
pGlobal_config[LL_ADV_TO_CONN_REQ_DELAY] = 16+RF_PHY_EXT_PREAMBLE_US;
}
else if(g_system_clk==SYS_CLK_DLL_48M)
{
// scan req -> scan rsp timing
pGlobal_config[SCAN_RSP_DELAY] = 6+RF_PHY_EXT_PREAMBLE_US;//20201207 set //14; // 12 // 2019/3/19 A2: 12 --> 9
pGlobal_config[LL_ADV_TO_SCAN_REQ_DELAY] = 8+RF_PHY_EXT_PREAMBLE_US;//12; // 2019/3/19 A2: 12 --> 10
pGlobal_config[LL_ADV_TO_CONN_REQ_DELAY] = 11+RF_PHY_EXT_PREAMBLE_US;
}
else if(g_system_clk==SYS_CLK_DLL_64M)
{
pGlobal_config[SCAN_RSP_DELAY] = 4+RF_PHY_EXT_PREAMBLE_US;//2020.12.07 set //12;
pGlobal_config[LL_ADV_TO_SCAN_REQ_DELAY] = 6+RF_PHY_EXT_PREAMBLE_US; // 2019/3/26 add
pGlobal_config[LL_ADV_TO_CONN_REQ_DELAY] = 8+RF_PHY_EXT_PREAMBLE_US;
}
#endif
// TRLP timeout
pGlobal_config[LL_HW_TRLP_LOOP_TIMEOUT] = 50000; // enough for 8Tx + 8Rx : (41 * 8 + 150) * 16 - 150 = 7498us
pGlobal_config[LL_HW_TRLP_TO_GAP] = 1000;
@ -7857,7 +7885,7 @@ void init_config(void)
pGlobal_config[LL_MASTER_PROCESS_TARGET] = 200; // reserve time for preparing master conn event, delay should be insert if needn't so long time
pGlobal_config[LL_MASTER_TIRQ_DELAY] = 0; // timer IRQ -> timer ISR delay
pGlobal_config[OSAL_SYS_TICK_WAKEUP_TRIM] = 56; // 0.125us
pGlobal_config[MAC_ADDRESS_LOC] = 0x11001F00;
pGlobal_config[MAC_ADDRESS_LOC] = (uint32_t)ownPublicAddr; //0x11001F00;
// for simultaneous conn & adv/scan
pGlobal_config[LL_NOCONN_ADV_EST_TIME] = 1400*3;
pGlobal_config[LL_NOCONN_ADV_MARGIN] = 600;
@ -7896,7 +7924,9 @@ void init_config(void)
//JUMP_FUNCTION(LL_PROCESS_TX_DATA) = (uint32_t)&llProcessTxData1;
//JUMP_FUNCTION(OSAL_POWER_CONSERVE) = (uint32_t)&osal_pwrmgr_powerconserve1;
//JUMP_FUNCTION(ENTER_SLEEP_OFF_MODE) = (uint32_t)&enter_sleep_off_mode1;
//JUMP_FUNCTION(ENTER_SLEEP_PROCESS) = (uint32_t)&enterSleepProcess1;
#if TEST_RTC_DELTA
JUMP_FUNCTION(ENTER_SLEEP_PROCESS) = (uint32_t)&enterSleepProcess1;
#endif
JUMP_FUNCTION(CONFIG_RTC) = (uint32_t)&config_RTC1;
//JUMP_FUNCTION(V20_IRQ_HANDLER) = (uint32_t)&TIM1_IRQHandler1;
// JUMP_FUNCTION(LL_SCHEDULER) = (uint32_t)&ll_scheduler1;
@ -7926,6 +7956,7 @@ void init_config(void)
setSleepMode(SYSTEM_SLEEP_MODE);
}
//__ATTR_SECTION_XIP__
void ll_patch_slave(void)
{
JUMP_FUNCTION(LL_SET_ADV_PARAM) = (uint32_t)&LL_SetAdvParam1;
@ -7937,6 +7968,7 @@ void ll_patch_slave(void)
JUMP_FUNCTION(LL_SETUP_NEXT_SLAVE_EVT) = (uint32_t)&llSetupNextSlaveEvent1;
}
//__ATTR_SECTION_XIP__
void ll_patch_master(void)
{
JUMP_FUNCTION(LL_SET_ADV_PARAM) = (uint32_t)&LL_SetAdvParam1;
@ -7952,21 +7984,23 @@ void ll_patch_master(void)
JUMP_FUNCTION(LL_ENC_DECRYPT) = (uint32_t)&LL_ENC_Decrypt1;
JUMP_FUNCTION(LL_PROCESS_MASTER_CTRL_PROC) = (uint32_t)&llProcessMasterControlProcedures1;
JUMP_FUNCTION(LL_PROCESS_SLAVE_CTRL_PROC) = (uint32_t)&llProcessSlaveControlProcedures1;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SRX) = (uint32_t )&ll_processBasicIRQ_SRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SCANTRX) = (uint32_t )&ll_processBasicIRQ_ScanTRX0;
JUMP_FUNCTION(LL_SETUP_SEC_SCAN) = (uint32_t )&llSetupSecScan1;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SRX) = (uint32_t)&ll_processBasicIRQ_SRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SCANTRX) = (uint32_t)&ll_processBasicIRQ_ScanTRX0;
JUMP_FUNCTION(LL_SETUP_SEC_SCAN) = (uint32_t)&llSetupSecScan1;
}
//__ATTR_SECTION_XIP__
void ll_patch_multi(void)
{
ll_patch_slave();
ll_patch_master();
JUMP_FUNCTION(LL_SCHEDULER) = (uint32_t)&ll_scheduler1;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SECADVTRX) = (uint32_t )&ll_processBasicIRQ_secondaryAdvTRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SECSCANSRX) = (uint32_t )&ll_processBasicIRQ_secondaryScanSRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SECINITSRX) = (uint32_t )&ll_processBasicIRQ_secondaryInitSRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SECADVTRX) = (uint32_t)&ll_processBasicIRQ_secondaryAdvTRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SECSCANSRX) = (uint32_t)&ll_processBasicIRQ_secondaryScanSRX0;
JUMP_FUNCTION(LL_PROCESSBASICIRQ_SECINITSRX) = (uint32_t)&ll_processBasicIRQ_secondaryInitSRX0;
}
//__ATTR_SECTION_XIP__
void hal_rom_boot_init(void)
{
extern void _rom_sec_boot_init();
@ -8291,7 +8325,7 @@ hciStatus_t HCI_LE_ConnUpdateCmd( uint16 connHandle,
return( HCI_SUCCESS );
}
__ATTR_SECTION_XIP__
//__ATTR_SECTION_XIP__
CHIP_ID_STATUS_e chip_id_one_bit_hot_convter(uint8_t* b, uint32_t w)
{
uint16 dh = w >> 16;
@ -8395,36 +8429,39 @@ extern const char* s_company_id;
__attribute__((aligned(4))) static uint8_t s_trng_seed[16];
__attribute__((aligned(4))) static uint8_t s_trng_iv[16];
__ATTR_SECTION_XIP__ static void TRNG_Output(uint32_t* buf, uint8_t len)
//__ATTR_SECTION_XIP__
static void TRNG_Output(uint32_t* buf, uint8_t len)
{
uint32_t temp,temp1,status;
temp = AP_AON->RTCCFG2;
AP_AON->RTCCFG2 = (temp & 0xfffefe00) | 0x0108;
for(uint8_t j=0; j<len; j++)
for(uint8_t j=0; j < len; j++)
{
status = 0;
for(uint8_t i = 0; i<16; i++)
for(uint8_t i = 0; i < 16; i++)
{
WaitRTCCount(17);
temp1 = AP_AON->RTCTRCNT;
temp1 = AP_AON->RTCTRCCNT;
status |= ((temp1 & 0x03)<<(i<<1));
}
*buf++ = status;
}
return;
}
__ATTR_SECTION_XIP__ static void TRNG_IV_Updata()
//__ATTR_SECTION_XIP__
static void TRNG_IV_Updata()
{
*(uint32*)(&s_trng_iv[0]) +=read_current_fine_time();
*(uint32*)(&s_trng_iv[4]) +=read_current_fine_time();
*(uint32*)(&s_trng_iv[8]) +=read_current_fine_time();
*(uint32*)(&s_trng_iv[12])+=read_current_fine_time();
}
__ATTR_SECTION_XIP__ void TRNG_INIT(void)
//__ATTR_SECTION_XIP__
void TRNG_INIT(void)
{
static uint8_t init_flag = 0;
@ -8438,7 +8475,8 @@ __ATTR_SECTION_XIP__ void TRNG_INIT(void)
return;
}
__ATTR_SECTION_XIP__ uint8_t TRNG_Rand(uint8_t* buf,uint8_t len)
//__ATTR_SECTION_XIP__
uint8_t TRNG_Rand(uint8_t* buf,uint8_t len)
{
uint32_t t0=0;
uint8_t i;

3
bthome_phy6222/SDK/lib/sec/phy_sec_ext.c
View file

@ -80,6 +80,7 @@ uint8_t PHY_Varify_Platform()
}
extern int flash_load_parition(unsigned char* pflash, int size, unsigned char* micIn,unsigned char* run_addr);
bool _efuse_chip_version_check(void)
{
uint32_t buf[2];
@ -103,12 +104,14 @@ bool _efuse_chip_version_check(void)
return 0;
}
}
void efuse_init(void)
{
write_reg(0x4000f054,0x0);
write_reg(0x4000f140,0x0);
write_reg(0x4000f144,0x0);
}
void _rom_sec_boot_init(void)
{
efuse_init();

64
bthome_phy6222/SDK/misc/CMSIS/device/phyplus/phy6222_cstart.c
View file

@ -2,16 +2,8 @@
/****************************************************************************
Included Files
****************************************************************************/
#if 1
#include "rom_sym_def.h"
#include <stddef.h>
#include "phy6222_cstart.h"
#include "clock.h"
#include "log.h"
#include "flash.h"
#include "jump_function.h"
#include "global_config.h"
#include <stdint.h>
#include <string.h>
/****************************************************************************
Pre-processor Definitions
@ -21,10 +13,6 @@ extern int main(void);
extern const uint32_t _sbss;
extern const uint32_t _ebss;
//extern const uint32_t _eronly;
//extern const uint32_t _sdata;
//extern const uint32_t _edata;
/****************************************************************************
Name: c_start
@ -33,53 +21,23 @@ extern const uint32_t _ebss;
****************************************************************************/
//extern void *osal_memset(void *s, uint8 c, size_t n);
//extern void* osal_memcpy(void* dest, const void* src, size_t n);
//extern uint32 global_config[SOFT_PARAMETER_NUM];
#ifdef __GNUC__
void c_start(void) __attribute__ ((naked));
#endif
void c_start(void)
{
uint8_t* dest;
uint8_t* edest;
/// spif_config(SYS_CLK_DLL_64M, 1, XFRD_FCMD_READ_DUAL, 0, 0);
/// AP_PCR->CACHE_BYPASS = 1; //just bypass cache
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
certain that there are no issues with the state of global variables.
*/
dest = (uint8_t*)&_sbss;
edest = (uint8_t*)&_ebss;
osal_memset(dest, 0, edest - dest);
/* filled in init_config() */
/*
dest = (uint8_t*)0x1fff0400;
osal_memset(dest, 0, SOFT_PARAMETER_NUM * 4);
*/
/* Move the initialized data section from his temporary holding spot in
FLASH into the correct place in SRAM. The correct place in SRAM is
give by _sdata and _edata. The temporary location is in FLASH at the
end of all of the other read-only data (.text, .rodata) at _eronly.
*/
#if 0
const uint8_t* src = (const uint8_t*)&_eronly;
dest = (uint8_t*)&_sdata;
edest = (uint8_t*)&_edata;
osal_memcpy(dest, src, edest - dest);
#endif
uint8_t* dest = (uint8_t*)&_sbss;
uint8_t* edest = (uint8_t*)&_ebss;
memset(dest, 0, edest - dest);
main();
/* Shouldn't get here */
for (; ; );
while(1);
}
#else
void c_start(void)
{
main();
/* Shouldn't get here */
for (; ; );
}
#endif

2
bthome_phy6222/SDK/misc/bb_rom_sym_m0.gcc
View file

@ -584,7 +584,7 @@ ll_adv_scheduler = 0x000105ad;
ll_adv_scheduler_periodic = 0x000105c9;
ll_allocAuxAdvTimeSlot = 0x000105e5;
ll_allocAuxAdvTimeSlot_prd = 0x00010679;
ll_debug_output = 0x00010719;
_ll_debug_output = 0x00010719;
ll_deleteTask = 0x00010731;
ll_delete_adv_task = 0x00010765;
ll_delete_adv_task_periodic = 0x00010781;

5
bthome_phy6222/SDK/misc/jump_table.c
View file

@ -30,6 +30,9 @@ void (*trap_c_callback)(void);
extern void log_printf(const char* format, ...);
void _hard_fault(uint32_t* arg)
{
#if DEBUG_INFO == 0
(void)arg;
#else
uint32_t* stk = (uint32_t*)((uint32_t)arg);
log_printf("[Hard fault handler]\n");
// log_printf("R0 = 0x%08x\n", stk[9]);
@ -50,7 +53,7 @@ void _hard_fault(uint32_t* arg)
log_printf("PC = 0x%08x\n", stk[15]);
log_printf("PSR = 0x%08x\n", stk[16]);
log_printf("ICSR = 0x%08x\n", *(volatile uint32_t*)0xE000ED04);
#endif
if (trap_c_callback)
{
trap_c_callback();

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2
bthome_phy6222/mk_windows.cmd
View file

@ -1,5 +1,5 @@
@set PATH=D:\MCU\GNU_Tools_ARM_Embedded\13.2.rel1\bin;%PATH%
@set SWVER=_v13
@set SWVER=_v14
@del /Q "build\THB2%SWVER%.hex"
@del /Q "build\THB2%SWVER%.bin"
@mkdir .\bin

15
bthome_phy6222/source/battery.c
View file

@ -42,12 +42,15 @@ void __attribute__((used)) hal_ADC_IRQHandler(void) {
NVIC_DisableIRQ((IRQn_Type) ADCC_IRQn);
// JUMP_FUNCTION(ADCC_IRQ_HANDLER) = 0;
// AP_ADCC->intr_clear = 0x1FF;
AP_PCRM->ANA_CTL &= ~BIT(3);
AP_PCRM->ANA_CTL &= ~(BIT(3) | BIT(0)); // ADC disable, Power down analog LDO
#if defined(CLK_16M_ONLY) && CLK_16M_ONLY != 0
AP_PCRM->CLKHF_CTL1 &= ~BIT(13);
#else
if (g_system_clk != SYS_CLK_DBL_32M) {
AP_PCRM->CLKHF_CTL1 &= ~BIT(13);
}
#endif
AP_IOMUX->Analog_IO_en = 0; /// &= ~BIT(ADC_PIN - P11); // hal_gpio_cfg_analog_io(ADC_PIN, Bit_DISABLE);
AP_PCRM->ANA_CTL &= ~BIT(0); // Power down analog LDO
hal_clk_reset(MOD_ADCC);
hal_clk_gate_disable(MOD_ADCC);
AP_IOMUX->pad_ps0 &= ~BIT(ADC_PIN); // hal_gpio_ds_control(ADC_PIN, Bit_ENABLE);
@ -97,8 +100,7 @@ void batt_start_measure(void) {
#elif ADC_VBAT_CHL == VBAT_ADC_P20
AP_PCRM->ADC_CTL3 |= BIT(4);
#endif
AP_PCRM->ANA_CTL |= BIT(3); //ENABLE_ADC;
AP_PCRM->ANA_CTL |= BIT(0); //new
AP_PCRM->ANA_CTL |= BIT(3) | BIT(0); // ADC enable, Power on analog LDO
NVIC_SetPriority((IRQn_Type) ADCC_IRQn, IRQ_PRIO_HAL);
NVIC_EnableIRQ((IRQn_Type) ADCC_IRQn); //ADC_IRQ_ENABLE;
@ -110,9 +112,8 @@ void batt_start_measure(void) {
}
static void init_adc_batt(void) {
AP_AON->PMCTL2_1 = 0x00;
AP_PCRM->ANA_CTL &= ~BIT(0);
AP_PCRM->ANA_CTL &= ~BIT(3);
AP_AON->PMCTL2_1 = 0;
AP_PCRM->ANA_CTL &= ~(BIT(0) | BIT(3)); // ADC disable, Power down analog LDO
hal_clk_gate_disable(MOD_ADCC);
hal_clk_reset(MOD_ADCC);
hal_clk_gate_enable(MOD_ADCC);

4
bthome_phy6222/source/config.c
View file

@ -69,9 +69,13 @@ void restore_utc_time_sec(void) {
uint32_t get_utc_time_sec(void) {
uint32_t new_time_tik;
HAL_ENTER_CRITICAL_SECTION();
#if TEST_RTC_DELTA
do {
new_time_tik = AP_AON->RTCCNT;
} while(new_time_tik != AP_AON->RTCCNT);
#else
new_time_tik = AP_AON->RTCCNT;
#endif
if(new_time_tik <= clkt.utc_time_tik)
clkt.utc_time_add += new_time_tik - clkt.utc_time_tik;
else

6
bthome_phy6222/source/config.h
View file

@ -13,7 +13,7 @@
// #include "bus_dev.h"
#ifndef APP_VERSION
#define APP_VERSION 0x13 // BCD
#define APP_VERSION 0x14 // BCD
#endif
/*
@ -43,7 +43,7 @@
#define DEVICE_TH05V13 24
#ifndef DEVICE
#define DEVICE DEVICE_THB1
#define DEVICE DEVICE_TH05V13
#endif
// supported services by the device (bits)
@ -302,7 +302,7 @@
// Maximum connection interval (units of 1.25ms, 800=1000ms) if automatic parameter update request is enabled
#define DEFAULT_DESIRED_MAX_CONN_INTERVAL 24 // 30 ms
// Slave latency to use if automatic parameter update request is enabled
#define DEFAULT_DESIRED_SLAVE_LATENCY 29 // (29+1)*30 = 900 ms
#define DEFAULT_DESIRED_SLAVE_LATENCY 29 // (29+1)*30 = 900 ms, max MAX_SLAVE_LATENCY 500
// Supervision timeout value (units of 10ms, 1000=10s) if automatic parameter update request is enabled
#define DEFAULT_DESIRED_CONN_TIMEOUT 400 // 4s

30
bthome_phy6222/source/main.c
View file

@ -32,7 +32,7 @@
*/
extern void init_config(void);
extern int app_main(void);
extern void app_main(void);
extern void hal_rom_boot_init(void);
/*********************************************************************
CONNECTION CONTEXT RELATE DEFINITION
@ -280,7 +280,6 @@ const ioinit_cfg_t ioInit[] = {
for (uint8_t i = 0; i < sizeof(ioInit) / sizeof(ioinit_cfg_t); i++) {
hal_gpio_pull_set(ioInit[i].pin, ioInit[i].type);
//hal_gpio_pin_init(ioInit[i].pin, GPIO_INPUT);
}
#ifdef GPIO_SPWR
hal_gpio_write(GPIO_SPWR, 1);
@ -292,8 +291,12 @@ const ioinit_cfg_t ioInit[] = {
DCDC_REF_CLK_SETTING(1);
DIG_LDO_CURRENT_SETTING(1);
#if defined ( __GNUC__ )
#if 0 // test
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2);
#else
extern uint32 g_irqstack_top;
// Check IRQ STACK (1KB) location
/*
if ((uint32_t) &g_irqstack_top > 0x1fffc000) {
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2);
@ -303,16 +306,14 @@ const ioinit_cfg_t ioInit[] = {
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1);
} else {
hal_pwrmgr_RAM_retention(RET_SRAM0); // RET_SRAM0|RET_SRAM1|RET_SRAM2
//test hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2);
}
#endif
#else
#if DEBUG_INFO || SDK_VER_RELEASE_ID != 0x03010102
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1); // RET_SRAM0|RET_SRAM1|RET_SRAM2
#else
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1); // RET_SRAM0|RET_SRAM1|RET_SRAM2
#endif
#endif
hal_pwrmgr_RAM_retention_set();
subWriteReg(0x4000f014,26,26, 1); // hal_pwrmgr_LowCurrentLdo_enable();
@ -414,7 +415,9 @@ int main(void) {
}
#endif // OTA_TYPE == OTA_TYPE_BOOT
watchdog_config(WDG_2S);
#if CFG_SLEEP_MODE == PWR_MODE_SLEEP
// watchdog_config(WDG_32S);
#endif
// spif_config(SYS_CLK_DLL_64M, 1, XFRD_FCMD_READ_DUAL, 0, 0);
@ -429,16 +432,22 @@ int main(void) {
init_config();
#if ( HOST_CONFIG & OBSERVER_CFG )
extern void ll_patch_advscan(void);
ll_patch_advscan();
// ll_patch_advscan();
#else
extern void ll_patch_slave(void);
ll_patch_slave();
// extern void ll_patch_slave(void);
// ll_patch_slave();
// extern void ll_patch_master(void);
// ll_patch_master();
#endif
hal_rfphy_init();
hal_init();
restore_utc_time_sec();
#if 0 //def STACK_MAX_SRAM
extern uint32 g_stack;
__set_MSP((uint32_t)(&g_stack));
#endif
load_eep_config();
LOG("SDK Version ID %08x \n",SDK_VER_RELEASE_ID);
@ -446,7 +455,8 @@ int main(void) {
LOG("sizeof(struct ll_pkt_desc) = %d, buf size = %d\n", sizeof(struct ll_pkt_desc), BLE_CONN_BUF_SIZE);
LOG("sizeof(g_pConnectionBuffer) = %d, sizeof(pConnContext) = %d, sizeof(largeHeap)=%d \n",
sizeof(g_pConnectionBuffer), sizeof(pConnContext),sizeof(g_largeHeap)); LOG("[REST CAUSE] %d\n ",g_system_reset_cause);
app_main();
app_main(); // No Return from here
return 0;
}

4
bthome_phy6222/source/osal_peripheral.c
View file

@ -9,7 +9,7 @@
INCLUDES
**************************************************************************************************/
#include "config.h"
#if (APP_CFG == 0)
//#if (APP_CFG == 0)
#include "OSAL.h"
#include "OSAL_Tasks.h"
@ -132,5 +132,5 @@ void osalInitTasks( void )
/* Application */
SimpleBLEPeripheral_Init( taskID++ );
}
#endif
//#endif // (APP_CFG == 0)

10
bthome_phy6222/source/peripheral_main.c
View file

@ -5,7 +5,7 @@
Description: This file contains the main and callback functions for
the Simple BLE Peripheral sample application.
**************************************************************************************************/
#if (APP_CFG == 0)
// #if (APP_CFG == 0)
/**************************************************************************************************
Includes
**************************************************************************************************/
@ -31,16 +31,18 @@
@return none
**************************************************************************************************
*/
int app_main(void)
#ifdef __GNUC__
void app_main(void) __attribute__ ((naked));
#endif
void app_main(void)
{
/* Initialize the operating system */
osal_init_system();
osal_pwrmgr_device( PWRMGR_BATTERY );
/* Start OSAL */
osal_start_system(); // No Return from here
return 0;
}
#endif
// #endif (APP_CFG == 0)
/**************************************************************************************************
CALL-BACKS
**************************************************************************************************/