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change hal_spif_cache_init()

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pvvx 2024-01-08 16:40:52 +03:00
parent 0baba5110f
commit a48f01f1ce
4 changed files with 2547 additions and 2551 deletions
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5049
TestTHB2.hex
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30
bthome_phy6222/SDK/components/driver/flash/flash.c
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@ -49,8 +49,9 @@
#define spif_wait_nobusy(flg, tout_ns, return_val) {if(_spif_wait_nobusy_x(flg, tout_ns)){if(return_val){ return return_val;}}}
static xflash_Ctx_t s_xflashCtx = { .spif_ref_clk = SYS_CLK_DLL_64M, .rd_instr =
XFRD_FCMD_READ_DUAL };
static xflash_Ctx_t s_xflashCtx = {
.spif_ref_clk = SYS_CLK_DLL_64M,
.rd_instr = XFRD_FCMD_READ_DUAL };
chipMAddr_t g_chipMAddr;
@ -231,22 +232,19 @@ uint8_t hal_flash_get_lock_state(void)
}
#endif
#ifdef XFLASH_HIGH_SPEED
static void hw_spif_config_high_speed(sysclk_t ref_clk)
static void hw_spif_cache_config(void)
{
spif_config(s_xflashCtx.spif_ref_clk,
1,
s_xflashCtx.rd_instr,
0,
(s_xflashCtx.rd_instr == XFRD_FCMD_READ_QUAD)? 1 : 0);
#ifdef XFLASH_HIGH_SPEED
volatile uint32_t tmp = AP_SPIF->config;
tmp = (tmp & (~ (0xf << 19))) | (0 << 19);
AP_SPIF->config = tmp;
subWriteReg(&AP_SPIF->rddata_capture, 4, 1, 2);
}
#endif
static void hw_spif_cache_config(void)
{
spif_config(s_xflashCtx.spif_ref_clk,/*div*/1,s_xflashCtx.rd_instr,0,(s_xflashCtx.rd_instr == XFRD_FCMD_READ_QUAD));
#ifdef XFLASH_HIGH_SPEED
hw_spif_config_high_speed(s_xflashCtx.spif_ref_clk);
#endif
AP_SPIF->wr_completion_ctrl = 0xff010005; //set longest polling interval
AP_SPIF->low_wr_protection = 0;
@ -259,9 +257,9 @@ static void hw_spif_cache_config(void)
}
int hal_spif_cache_init(xflash_Ctx_t cfg) {
memset(&(s_xflashCtx), 0, sizeof(s_xflashCtx));
memcpy(&(s_xflashCtx), &cfg, sizeof(s_xflashCtx));
int hal_spif_cache_init(sysclk_t spif_ref_clk, uint32_t rd_instr) {
s_xflashCtx.spif_ref_clk = spif_ref_clk;
s_xflashCtx.rd_instr = rd_instr;
hw_spif_cache_config();
hal_pwrmgr_register(MOD_SPIF, NULL, hw_spif_cache_config);
return PPlus_SUCCESS;

2
bthome_phy6222/SDK/components/driver/flash/flash.h
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@ -124,7 +124,7 @@ extern int spif_write_protect(bool en);
extern void spif_cmd(uint8_t op, uint8_t addrlen, uint8_t rdlen, uint8_t wrlen, uint8_t mbit, uint8_t dummy);
extern void spif_rddata(uint8_t* data, uint8_t len);
extern int spif_config(sysclk_t ref_clk, uint8_t div, uint32_t rd_instr, uint8_t mode_bit, uint8_t QE);
int hal_spif_cache_init(xflash_Ctx_t cfg);
int hal_spif_cache_init(sysclk_t spif_ref_clk, uint32_t rd_instr);
//static void hal_cache_tag_flush(void);
#if(FLASH_PROTECT_FEATURE == 1)
int hal_flash_lock(void);

9
bthome_phy6222/source/main.c
View file

@ -229,13 +229,8 @@ static void hal_init(void) {
clk_init(g_system_clk); //system init
hal_rtc_clock_config((CLK32K_e) g_clk32K_config);
hal_pwrmgr_init();
xflash_Ctx_t cfg = {
#if SDK_VER_RELEASE_ID == 0x03010102
.spif_ref_clk = SYS_CLK_DLL_64M, // SYS_CLK_RC_32M
#endif
.rd_instr = XFRD_FCMD_READ_DUAL // XFRD_FCMD_READ_QUAD // XFRD_FCMD_READ_DUAL
};
hal_spif_cache_init(cfg);
// g_system_clk, SYS_CLK_DLL_64M, SYS_CLK_RC_32M / XFRD_FCMD_READ_QUAD, XFRD_FCMD_READ_DUAL
hal_spif_cache_init(SYS_CLK_DLL_64M, XFRD_FCMD_READ_DUAL);
hal_gpio_init();
LOG_INIT();
hal_fs_init(0x1103C000, 2);