Merge pull request #6 from froloffw7/master
Оптимизация использования памяти
This commit is contained in:
Victor
GitHub
commit
993db00e2e
9 changed files with 710 additions and 83 deletions
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@ -37,26 +37,32 @@ OBJCOPY = $(GCC_PATH)arm-none-eabi-objcopy
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OBJDUMP = $(GCC_PATH)arm-none-eabi-objdump
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SIZE = $(GCC_PATH)arm-none-eabi-size
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READELF = $(GCC_PATH)arm-none-eabi-readelf
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##############################################################################
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ARCH_FLAGS := -mcpu=cortex-m0 -mthumb -mthumb-interwork
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OPT_CFLAGS ?= -Os
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DEB_CFLAGS ?= -g3 -ggdb
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##############################################################################
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ASFLAGS := $(ARCH_FLAGS) $(OPT_CFLAGS) $(DEB_CFLAGS)
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CFLAGS = -Os
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CFLAGS += -W -Wall --std=gnu99
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CFLAGS += -mcpu=cortex-m0 -mthumb -mthumb-interwork
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CFLAGS += -fno-diagnostics-show-caret
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CFLAGS += -fdata-sections -ffunction-sections
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CFLAGS += -funsigned-char -funsigned-bitfields
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CFLAGS += -specs=nosys.specs
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CFLAGS += -Wl,--gc-sections
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#CFLAGS += -MM $(CFLAGS) $(INCFLAGS) $< -MT $@ -MF $(OBJ_DIR)/$(patsubst %.o,%.d,$@)
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CFLAGS := $(ARCH_FLAGS) $(OPT_CFLAGS) $(DEB_CFLAGS)
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CFLAGS += -W -Wall --std=gnu99
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CFLAGS += -fno-diagnostics-show-caret
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CFLAGS += -fdata-sections -ffunction-sections
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CFLAGS += -funsigned-char -funsigned-bitfields
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CFLAGS += -specs=nosys.specs
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CFLAGS += -Wl,--gc-sections
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#CFLAGS += -MM $(CFLAGS) $(INCFLAGS) $< -MT $@ -MF $(OBJ_DIR)/$(patsubst %.o,%.d,$@)
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LDSCRIPT?= $(SDK_PATH)/misc/phy6222.ld
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LDFLAGS += -mcpu=cortex-m0 -mthumb -mthumb-interwork
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LDFLAGS += --static -nostartfiles -nostdlib
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LDFLAGS += -Wl,--gc-sections
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LDFLAGS += -Wl,--script=$(LDSCRIPT)
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LDFLAGS += -Wl,--no-warn-rwx-segments
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LDFLAGS += -Wl,--just-symbols=$(SDK_PATH)/misc/bb_rom_sym_m0.gcc
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LDFLAGS += -Wl,-Map=$(OBJ_DIR)/$(PROJECT_NAME).map
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LIBS += -Wl,--start-group -lgcc -lnosys -Wl,--end-group
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LDSCRIPT ?= $(SDK_PATH)/misc/phy6222.ld
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LDFLAGS := $(ARCH_FLAGS)
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LDFLAGS += --static -nostartfiles -nostdlib
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LDFLAGS += -Wl,--gc-sections
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LDFLAGS += -Wl,--script=$(LDSCRIPT)
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# LDFLAGS += -Wl,--no-warn-rwx-segments
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LDFLAGS += -Wl,--just-symbols=$(SDK_PATH)/misc/bb_rom_sym_m0.gcc
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LDFLAGS += -Wl,-Map=$(OBJ_DIR)/$(PROJECT_NAME).map
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LIBS += -Wl,--start-group -lgcc -lnosys -Wl,--end-group
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##############################################################################
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INCLUDES += -I$(SDK_PATH)/misc
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INCLUDES += -I$(SDK_PATH)/misc/CMSIS/include
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@ -211,7 +217,7 @@ DEFINES += -DUSE_FS=0
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DEFINES += -DMAX_NUM_LL_CONN=1
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#DEFINES += -DXFLASH_HIGH_SPEED=1
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CFLAGS += $(DEFINES) $(INCLUDES)
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CFLAGS += $(DEFINES) $(INCLUDES)
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#SRC_O = $(patsubst %.c,%.o,$(patsubst sdk/%, $(SDK_PATH)%, $(SRCS)))
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@ -225,7 +231,7 @@ DEPENDENCY_LIST = $(OBJS:%o=%d)
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all: directory $(SRC_O) $(OBJ_DIR)/$(PROJECT_NAME).elf $(OBJ_DIR)/$(PROJECT_NAME).hex $(OBJ_DIR)/$(PROJECT_NAME).asm size
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%.elf: $(SRC_O)
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%.elf %.map: $(SRC_O) $(LDSCRIPT) Makefile
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@echo LD: $@
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@$(CC) $(LDFLAGS) $(OBJS) $(LIBS) -o $@
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@ -21,6 +21,7 @@
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#include "rf_phy_driver.h"
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#include "global_config.h"
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#include "jump_function.h"
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#include "pwrmgr.h"
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#include "uart.h"
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#include "ll_sleep.h"
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#include "ll_debug.h"
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@ -5639,6 +5640,7 @@ void config_RTC1(uint32 time)
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@return None.
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*/
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uint32 sleep_total;
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extern uint32 g_stack;
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#ifdef __GNUC__
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// Indicate that the specified function does not need prologue/epilogue sequences
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// generated by the compiler. And function doesn't return.
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@ -5652,6 +5654,8 @@ void wakeupProcess1(void)
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//restore initial_sp according to the app_initial_sp : 20180706 ZQ
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__set_MSP(pGlobal_config[INITIAL_STACK_PTR]);
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HAL_CRITICAL_SECTION_INIT();
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// All memory on
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hal_pwrmgr_RAM_retention_clr();
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//==== 20180416 commented by ZQ
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// to enable flash access after wakeup
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@ -5812,6 +5816,7 @@ void wakeupProcess1(void)
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g_llSleepContext.isTimer4RecoverRequired = FALSE;
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}
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__set_MSP((uint32_t)(&g_stack));
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// app could add operation after wakeup
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app_wakeup_process();
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// uart_tx0(" 111 ");
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@ -7643,20 +7648,25 @@ llStatus_t LL_StartEncrypt1( uint16 connId,
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// global configuration in SRAM, it could be change by application
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// ================== VARIABLES ==================================
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extern uint32 global_config[];
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extern uint32_t g_irqstack_top;
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// TODO: when integrate, the global_config should be set by APP project
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__ATTR_SECTION_XIP__ void init_config(void)
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__ATTR_SECTION_XIP__
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void init_config(void)
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{
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pGlobal_config = (uint32*)(CONFIG_BASE_ADDR);
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pGlobal_config = global_config;
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int i;
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for (i = 0; i < 256; i ++)
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pGlobal_config[i] = 0;
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//save the app initial_sp which will be used in wakeupProcess 20180706 by ZQ
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// pGlobal_config[INITIAL_STACK_PTR] = 0x400 + (uint32_t)&_ebss; // g_top_irqstack;
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pGlobal_config[INITIAL_STACK_PTR] = (uint32_t)(&g_irqstack_top);
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// LL switch setting
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pGlobal_config[LL_SWITCH] = LL_DEBUG_ALLOW | SLAVE_LATENCY_ALLOW | LL_WHITELIST_ALLOW
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| SIMUL_CONN_ADV_ALLOW | SIMUL_CONN_SCAN_ALLOW; //RC32_TRACKINK_ALLOW
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pGlobal_config[LL_SWITCH] = LL_DEBUG_ALLOW | SLAVE_LATENCY_ALLOW | LL_WHITELIST_ALLOW
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| SIMUL_CONN_ADV_ALLOW | SIMUL_CONN_SCAN_ALLOW; //RC32_TRACKINK_ALLOW
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if(g_clk32K_config == CLK_32K_XTAL)
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pGlobal_config[LL_SWITCH] &= 0xffffffee;
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@ -11,7 +11,7 @@
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.file "phy6222_start.s"
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/* *.ld: g_top_irqstack = ORIGIN(sram) + LENGTH(sram) */
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.global g_top_irqstack
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.global g_stack
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.text
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.align 2
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@ -21,14 +21,14 @@
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.type __start, %function
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__start:
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ldr r1, = g_top_irqstack
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ldr r1, = g_irqstack_top
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msr msp, r1 /* r2>>sp */
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bl c_start /* R0=IRQ, R1=register save area on stack */
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.size __start, .-__start
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#if 0 // Implemented in phy6222_vectors.c
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.section .isr_vector
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.align 4
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.globl __Vectors
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@ -38,7 +38,17 @@ __Vectors:
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.long __start
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.size __Vectors, . - __Vectors
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#endif
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.section .irq_stack
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.align 4
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.global g_irqstack_base
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.global g_irqstack_top
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g_irqstack_base:
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.space 0x400
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g_irqstack_top:
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.end
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@ -1,15 +1,13 @@
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#define locate_data(n) __attribute__ ((section(n)))
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extern unsigned int g_top_irqstack;
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extern unsigned int g_irqstack_top;
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extern void __start(void);
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const unsigned _vectors[] locate_data(".isr_vector") =
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{
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/* Initial stack */
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(unsigned)(&g_top_irqstack),
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(unsigned)(&g_irqstack_top),
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/* Reset exception handler */
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(unsigned)& __start,
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(unsigned)(&__start),
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};
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@ -27,8 +27,13 @@
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#include "l2cap.h"
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// ===================== MACROS =======================
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#if 0
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#define JUMP_BASE_ADDR 0x1fff0000
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#define JUMP_FUNCTION(x) (*(uint32 *)(JUMP_BASE_ADDR + (x << 2)))
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#else
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extern const uint32_t* jump_table_base[];
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#define JUMP_FUNCTION(x) (*(uint32 *)(jump_table_base + x))
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#endif
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// ROM function entries
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592
bthome_phy6222/SDK/misc/jump_function.h.orig
Normal file
592
bthome_phy6222/SDK/misc/jump_function.h.orig
Normal file
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@ -0,0 +1,592 @@
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/**
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****************************************************************************************
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@file jump_fucntion.h
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@brief This file contains the definitions of the macros and functions that are
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architecture dependent. The implementation of those is implemented in the
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appropriate architecture directory.
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$Rev: $
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SDK_LICENSE
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****************************************************************************************
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*/
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#ifndef _JUMP_FUNC_H_
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#define _JUMP_FUNC_H_
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#include <stdint.h>
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#include "types.h"
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#include "ll_def.h"
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#include "ll_sleep.h"
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#include "hci.h"
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#include "l2cap.h"
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// ===================== MACROS =======================
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#define JUMP_BASE_ADDR 0x1fff0000
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#define JUMP_FUNCTION(x) (*(uint32 *)(JUMP_BASE_ADDR + (x << 2)))
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// ROM function entries
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// 0 - 10 for common
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#define OSAL_INIT_TASKS 1
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#define TASKS_ARRAY 2
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#define TASK_COUNT 3
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#define TASK_EVENTS 4
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#define OSAL_MEM_INIT 5
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#define LL_INIT 11
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#define LL_PROCESS_EVENT 12
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#define LL_RESET 13
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#define LL_TXDATA 14
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#define LL_DISCONNECT 15
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#define LL_SET_ADV_PARAM 16
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#define LL_SET_ADV_DATA 17
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#define LL_SET_ADV_CONTROL 18
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#define LL_SET_DEFAULT_CONN_PARAM 19
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#define LL_EXT_SET_TX_POWER 20
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#define LL_CLEAR_WHITE_LIST 21
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#define LL_ADD_WHITE_LIST_DEV 22
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#define LL_REMOVE_WHITE_LIST_DEV 23
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#define LL_READ_WHITE_LIST_SIZE 24
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#define LL_NUM_EMPTY_WL_ENTRIES 25
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#define LL_SLAVE_EVT_ENDOK 26
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#define LL_SETUP_NEXT_SLAVE_EVT 27
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#define LL_CHK_LSTO_DURING_SL 28
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#define LL_PROCESS_SLAVE_CTRL_PROC 29
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#define LL_PROCESS_SLAVE_CTRL_PKT 30
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#define LL_SLAVE_EVT_ABORT 31
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#define LL_PROCESS_RX_DATA 32
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#define LL_PROCESS_TX_DATA 33
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#define LL_CONN_TERMINATE 34
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#define LL_WRITE_TX_DATA 35
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#define LL_EVT_SCHEDULE 36
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#define LL_MOVE_TO_SLAVE_FUNCTION 37
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#define LL_SLAVE_CONN_EVENT 38
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#define LL_SETUP_ADV 39
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#define LL_SETUP_UNDIRECT_ADV 40
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#define LL_SETUP_NOCONN_ADV 41
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#define LL_SETUP_SCAN_ADV 42
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#define LL_SETUP_DIRECT_ADV 43
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#define LL_CALC_TIMER_DRIFT 44
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#define LL_GENERATE_TX_BUFFER 45
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#define LL_READ_RX_FIFO 46
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#define LL_READ_TX_FIFO_RTLP 47
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#define LL_READ_TX_FIFO_PKT 48
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#define LL_HW_PROCESS_RTO 49
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#define LL_HW_SET_TIMING 50
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#define LL_RELEASE_CONN_ID 51
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#define LL_READ_TX_PWR_LVL 52 // A1 ROM metal change add
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#define LL_READ_ADV_TX_PWR_LVL 53 // A1 ROM metal change add
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#define LL_READ_RSSI 54 // A1 ROM metal change add
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#define LL_READ_REMOTE_USE_FEATURES 55 // A1 ROM metal change add
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#define LL_ENCRYPT 56 // A1 ROM metal change add
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#define LL_DIRECT_TEST_END 57 // A1 ROM metal change add
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#define LL_DIRECT_TEST_TX_TEST 58 // A1 ROM metal change add
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#define LL_DIRECT_TEST_RX_TEST 59 // A1 ROM metal change add
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#define OSAL_POWER_CONSERVE 60
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#define ENTER_SLEEP_PROCESS 61
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#define WAKEUP_PROCESS 62
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#define CONFIG_RTC 63
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#define ENTER_SLEEP_OFF_MODE 64 // A1 ROM metal change add
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#define HAL_PROCESS_POLL 65 // A1 ROM metal change add
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#define LL_HW_GO 66 // A1 ROM metal change add
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#define LL_HW_TRIGGER 67 // A1 ROM metal change add
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#define LL_SET_TX_PWR_LVL 68 // A1 ROM metal change add
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// LL AES
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#define LL_AES128_ENCRYPT 70 // A1 ROM metal change add
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#define LL_GEN_TRUE_RANDOM 71 // A1 ROM metal change add
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#define LL_GEN_DEVICE_SKD 72 // A1 ROM metal change add
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#define LL_GEN_DEVICE_IV 73 // A1 ROM metal change add
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#define LL_GENERATE_NOUNCE 74 // A1 ROM metal change add
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#define LL_ENC_ENCRYPT 75 // A1 ROM metal change add
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#define LL_ENC_DECRYPT 76 // A1 ROM metal change add
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// host entries
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#define SMP_INIT 80
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#define SMP_PROCESS_EVENT 81
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// l2cap entries
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#define L2CAP_PARSE_PACKET 82
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#define L2CAP_ENCAP_PACKET 83
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#define L2CAP_PKT_TO_SEGBUFF 84
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#define L2CAP_SEGBUFF_TO_LINKLAYER 85
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#define L2CAP_PROCESS_FREGMENT_TX_DATA 86
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//gap linkmgr entries
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#define GAP_LINK_MGR_PROCESS_CONNECT_EVT 87
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#define GAP_LINK_MGR_PROCESS_DISCONNECT_EVT 88
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// hci tl
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#define HCI_INIT 90 // A1 ROM metal change add
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#define HCI_PROCESS_EVENT 91 // A1 ROM metal change add
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// app entries
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#define APP_SLEEP_PROCESS 100
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#define APP_WAKEUP_PROCESS 101
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#define RF_INIT 102
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#define WAKEUP_INIT 103
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#define BOOT_INIT 104
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#define DEBUG_PRINT 105
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#define RF_CALIBRATTE 106 // A1 ROM metal change add
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#define RF_PHY_CHANGE 107 // A1 ROM metal change add
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// LL master, A2 ROM metal change add
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#define LL_MASTER_EVT_ENDOK 110
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#define LL_SETUP_NEXT_MASTER_EVT 111
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#define LL_PROCESS_MASTER_CTRL_PROC 112
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#define LL_PROCESS_MASTER_CTRL_PKT 113
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#define LL_MOVE_TO_MASTER_FUNCTION 114
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#define LL_MASTER_CONN_EVENT 115
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#define LL_SET_SCAN_CTRL 116
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#define LL_SET_SCAN_PARAM 117
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#define LL_CREATE_CONN 118
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#define LL_CREATE_CONN_CANCEL 119
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#define LL_START_ENCRYPT 120
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#define LL_SETUP_SCAN 121
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#define LL_SETUP_SEC_NOCONN_ADV 122
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#define LL_SETUP_SEC_SCAN 123
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#define LL_SEC_ADV_ALLOW 124
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#define LL_CALC_MAX_SCAN_TIME 125
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// A2 multi-connection
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#define LL_SETUP_SEC_ADV_ENTRY 126
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#define LL_SETUP_SEC_CONN_ADV 127
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#define LL_SETUP_SEC_SCANNABLE_ADV 128
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//DLE
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#define LL_SET_DATA_LENGTH 130
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#define LL_PDU_LENGTH_UPDATE 131
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#define LL_TRX_NUM_ADJUST 132
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//PHY UPDATE
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#define LL_SET_PHY_MODE 133
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#define LL_PHY_MODE_UPDATE 134
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#define LL_SET_NEXT_PHY_MODE 135
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#define LL_ADP_ADJ_NEXT_TIME 136
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#define LL_ADP_SMART_WINDOW 137
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#define LL_SET_NEXT_DATA_CHN 138
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#define LL_PLUS_DISABLE_LATENCY 139
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#define LL_PLUS_ENABLE_LATENCY 140
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#define LL_SETUP_EXT_ADV_EVENT 141
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#define LL_SETUP_PRD_ADV_EVENT 142
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#define LL_SETUP_ADV_EXT_IND_PDU 143
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#define LL_SETUP_AUX_ADV_IND_PDU 144
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#define LL_SETUP_AUX_SYNC_IND_PDU 145
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#define LL_SETUP_AUX_CHAIN_IND_PDU 146
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#define LL_SETUP_AUX_CONN_REQ_PDU 147
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#define LL_SETUP_AUX_CONN_RSP_PDU 148
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#define LL_SCHEDULER 149
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#define LL_ADD_TASK 150
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#define LL_DEL_TASK 151
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#define LL_ADV_SCHEDULER 152
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||||
#define LL_ADV_ADD_TASK 153
|
||||
#define LL_ADV_DEL_TASK 154
|
||||
|
||||
#define LL_ADV_SCHEDULER_PRD 155
|
||||
#define LL_ADV_ADD_TASK_PRD 156
|
||||
#define LL_ADV_DEL_TASK_PRD 157
|
||||
|
||||
#define LL_GET_NEXT_AUX_CHN 158
|
||||
#define LL_SETUP_AUX_SCAN_RSP_PDU 159
|
||||
|
||||
#define LL_PROCESSBASICIRQ_SRX 160
|
||||
#define LL_PROCESSBASICIRQ_SECADVTRX 161
|
||||
#define LL_PROCESSBASICIRQ_SCANTRX 162
|
||||
#define LL_PROCESSBASICIRQ_SECSCANSRX 163
|
||||
#define LL_PROCESSBASICIRQ_SECINITSRX 164
|
||||
|
||||
// 2020-02-13 Add for CTE
|
||||
#define LL_CONNLESS_CTE_TX_PARAM 203
|
||||
#define LL_CONNLESS_CTE_TX_ENABLE 204
|
||||
#define LL_CONNLESS_IQ_SAMPLE_ENABLE 205
|
||||
#define LL_CONN_CTE_RECV_PARAM 206
|
||||
#define LL_CONN_CTE_REQ_EN 207
|
||||
#define LL_CONN_CTE_TX_PARAM 208
|
||||
#define LL_CONN_CTE_RSP_EN 209
|
||||
|
||||
//OSAL
|
||||
#define OSAL_SET_EVENT 210
|
||||
#define OSAL_MSG_SEND 211
|
||||
#define HAL_DRV_IRQ_INIT 212
|
||||
#define HAL_DRV_IRQ_ENABLE 213
|
||||
#define HAL_DRV_IRQ_DISABLE 214
|
||||
|
||||
#define HAL_WATCHDOG_INIT 215
|
||||
|
||||
// interrupt request handler
|
||||
#define NMI_HANDLER 219
|
||||
#define HARDFAULT_HANDLER 220
|
||||
#define SVC_HANDLER 221
|
||||
#define PENDSV_HANDLER 222
|
||||
#define SYSTICK_HANDLER 223
|
||||
|
||||
#define V0_IRQ_HANDLER 224
|
||||
#define V1_IRQ_HANDLER 225
|
||||
#define V2_IRQ_HANDLER 226
|
||||
#define V3_IRQ_HANDLER 227
|
||||
#define V4_IRQ_HANDLER 228
|
||||
#define V5_IRQ_HANDLER 229
|
||||
#define V6_IRQ_HANDLER 230
|
||||
#define V7_IRQ_HANDLER 231
|
||||
#define V8_IRQ_HANDLER 232
|
||||
#define V9_IRQ_HANDLER 233
|
||||
#define V10_IRQ_HANDLER 234
|
||||
#define V11_IRQ_HANDLER 235
|
||||
#define V12_IRQ_HANDLER 236
|
||||
#define V13_IRQ_HANDLER 237
|
||||
#define V14_IRQ_HANDLER 238
|
||||
#define V15_IRQ_HANDLER 239
|
||||
#define V16_IRQ_HANDLER 240
|
||||
#define V17_IRQ_HANDLER 241
|
||||
#define V18_IRQ_HANDLER 242
|
||||
#define V19_IRQ_HANDLER 243
|
||||
#define V20_IRQ_HANDLER 244
|
||||
#define V21_IRQ_HANDLER 245
|
||||
#define V22_IRQ_HANDLER 246
|
||||
#define V23_IRQ_HANDLER 247
|
||||
#define V24_IRQ_HANDLER 248
|
||||
#define V25_IRQ_HANDLER 249
|
||||
#define V26_IRQ_HANDLER 250
|
||||
#define V27_IRQ_HANDLER 251
|
||||
#define V28_IRQ_HANDLER 252
|
||||
#define V29_IRQ_HANDLER 253
|
||||
#define V30_IRQ_HANDLER 254
|
||||
#define V31_IRQ_HANDLER 255
|
||||
|
||||
// ================== FUNCTIONS ==================================
|
||||
void move_to_slave_function0(void);
|
||||
void LL_slave_conn_event0(void);
|
||||
llStatus_t llSetupAdv0(void);
|
||||
void llSetupUndirectedAdvEvt0(void);
|
||||
void llSetupNonConnectableAdvEvt0( void );
|
||||
void llSetupScannableAdvEvt0( void );
|
||||
void llSetupDirectedAdvEvt0( void );
|
||||
void LL_evt_schedule0(void);
|
||||
|
||||
void llCalcTimerDrift0( uint32 connInterval,
|
||||
uint16 slaveLatency,
|
||||
uint8 sleepClkAccuracy,
|
||||
uint32* timerDrift ) ;
|
||||
|
||||
uint16 ll_generateTxBuffer0(int txFifo_vacancy, uint16* pSave_ptr);
|
||||
|
||||
void ll_hw_read_tfifo_rtlp0(void);
|
||||
|
||||
void ll_read_rxfifo0(void);
|
||||
|
||||
int ll_hw_read_tfifo_packet0(uint8* pkt);
|
||||
|
||||
void ll_hw_process_RTO0(uint32 ack_num);
|
||||
|
||||
void LL_set_default_conn_params0(llConnState_t* connPtr);
|
||||
|
||||
// =====
|
||||
void enterSleepProcess0(uint32 time);
|
||||
|
||||
void wakeupProcess0(void);
|
||||
|
||||
void config_RTC0(uint32 time);
|
||||
|
||||
void enter_sleep_off_mode0(Sleep_Mode mode);
|
||||
|
||||
void llSlaveEvt_TaskEndOk0( void );
|
||||
|
||||
uint8 llSetupNextSlaveEvent0( void );
|
||||
|
||||
uint8 llCheckForLstoDuringSL0( llConnState_t* connPtr );
|
||||
|
||||
uint8 llProcessSlaveControlProcedures0( llConnState_t* connPtr );
|
||||
|
||||
void llProcessSlaveControlPacket0( llConnState_t* connPtr,
|
||||
uint8* pBuf );
|
||||
|
||||
void llSlaveEvt_TaskAbort0(void );
|
||||
|
||||
// ------
|
||||
void llMasterEvt_TaskEndOk0( void );
|
||||
void llProcessMasterControlPacket0( llConnState_t* connPtr,
|
||||
uint8* pBuf );
|
||||
uint8 llProcessMasterControlProcedures0( llConnState_t* connPtr );
|
||||
uint8 llSetupNextMasterEvent0( void );
|
||||
|
||||
void move_to_master_function0(void);
|
||||
void LL_master_conn_event0(void);
|
||||
|
||||
llStatus_t LL_SetScanControl0( uint8 scanMode,
|
||||
uint8 filterReports );
|
||||
llStatus_t LL_SetScanParam0( uint8 scanType,
|
||||
uint16 scanInterval,
|
||||
uint16 scanWindow,
|
||||
uint8 ownAddrType,
|
||||
uint8 scanWlPolicy );
|
||||
|
||||
llStatus_t LL_CreateConn0( uint16 scanInterval,
|
||||
uint16 scanWindow,
|
||||
uint8 initWlPolicy,
|
||||
uint8 peerAddrType,
|
||||
uint8* peerAddr,
|
||||
uint8 ownAddrType,
|
||||
uint16 connIntervalMin,
|
||||
uint16 connIntervalMax,
|
||||
uint16 connLatency,
|
||||
uint16 connTimeout,
|
||||
uint16 minLength,
|
||||
uint16 maxLength );
|
||||
llStatus_t LL_CreateConnCancel0( void );
|
||||
|
||||
llStatus_t LL_StartEncrypt0( uint16 connId,
|
||||
uint8* rand,
|
||||
uint8* eDiv,
|
||||
uint8* ltk );
|
||||
|
||||
void llSetupScan0( uint8 chan );
|
||||
|
||||
// ================== ll.c
|
||||
void LL_Init0( uint8 taskId );
|
||||
uint16 LL_ProcessEvent0( uint8 task_id, uint16 events );
|
||||
llStatus_t LL_Reset0( void );
|
||||
llStatus_t LL_TxData0( uint16 connId, uint8* pBuf, uint8 pktLen, uint8 fragFlag );
|
||||
llStatus_t LL_Disconnect0( uint16 connId, uint8 reason );
|
||||
llStatus_t LL_SetAdvParam0( uint16 advIntervalMin,
|
||||
uint16 advIntervalMax,
|
||||
uint8 advEvtType,
|
||||
uint8 ownAddrType,
|
||||
uint8 directAddrType,
|
||||
uint8* directAddr,
|
||||
uint8 advChanMap,
|
||||
uint8 advWlPolicy );
|
||||
llStatus_t LL_SetAdvData0( uint8 advDataLen, uint8* advData );
|
||||
llStatus_t LL_SetAdvControl0( uint8 advMode );
|
||||
|
||||
llStatus_t LL_EXT_SetTxPower0( uint8 txPower, uint8* cmdComplete );
|
||||
|
||||
llStatus_t LL_ClearWhiteList0( void );
|
||||
llStatus_t LL_AddWhiteListDevice0( uint8* devAddr, uint8 addrType );
|
||||
llStatus_t LL_RemoveWhiteListDevice0( uint8* devAddr, uint8 addrType );
|
||||
llStatus_t LL_ReadWlSize0( uint8* numEntries );
|
||||
llStatus_t LL_ReadTxPowerLevel0( uint8 connId, uint8 type, int8* txPower );
|
||||
llStatus_t LL_SetTxPowerLevel0( int8 txPower );
|
||||
llStatus_t LL_ReadAdvChanTxPower0( int8* txPower );
|
||||
llStatus_t LL_ReadRssi0( uint16 connId, int8* lastRssi );
|
||||
llStatus_t LL_ReadRemoteUsedFeatures0( uint16 connId );
|
||||
llStatus_t LL_Encrypt0( uint8* key, uint8* plaintextData, uint8* encryptedData );
|
||||
|
||||
llStatus_t LL_DirectTestEnd0( void );
|
||||
llStatus_t LL_DirectTestTxTest0( uint8 txFreq, uint8 payloadLen, uint8 payloadType );
|
||||
llStatus_t LL_DirectTestRxTest0( uint8 rxFreq );
|
||||
|
||||
// ================ ll_common.c
|
||||
void llProcessTxData0( llConnState_t* connPtr, uint8 context );
|
||||
uint8 llProcessRxData0( void );
|
||||
uint8 llWriteTxData0( llConnState_t* connPtr,
|
||||
uint8 pktHdr,
|
||||
uint8 pktLen,
|
||||
uint8* pBuf );
|
||||
void llConnTerminate0( llConnState_t* connPtr, uint8 reason );
|
||||
void llReleaseConnId0( llConnState_t* connPtr );
|
||||
|
||||
// ================ ll_enc.c
|
||||
void LL_ENC_AES128_Encrypt0( uint8* key,
|
||||
uint8* plaintext,
|
||||
uint8* ciphertext );
|
||||
uint8 LL_ENC_GenerateTrueRandNum0( uint8* buf,
|
||||
uint8 len );
|
||||
void LL_ENC_GenDeviceSKD0( uint8* SKD );
|
||||
void LL_ENC_GenDeviceIV0( uint8* IV );
|
||||
void LL_ENC_GenerateNonce0( uint32 pktCnt,
|
||||
uint8 direction,
|
||||
uint8* nonce );
|
||||
void LL_ENC_Encrypt0( llConnState_t* connPtr,
|
||||
uint8 pktHdr,
|
||||
uint8 pktLen,
|
||||
uint8* pBuf );
|
||||
uint8 LL_ENC_Decrypt0( llConnState_t* connPtr,
|
||||
uint8 pktHdr,
|
||||
uint8 pktLen,
|
||||
uint8* pBuf );
|
||||
|
||||
// =================== osal
|
||||
void osal_pwrmgr_powerconserve0( void ) ;
|
||||
|
||||
// =================== ll_hw_drv.c
|
||||
void ll_hw_set_timing0(uint8 pktFmt);
|
||||
void ll_hw_go0(void);
|
||||
void ll_hw_trigger0(void);
|
||||
|
||||
// ================== SMP functions
|
||||
void SM_Init0( uint8 task_id );
|
||||
uint16 SM_ProcessEvent0( uint8 task_id, uint16 events );
|
||||
|
||||
// ================== HCI_TL functions
|
||||
void HCI_Init0( uint8 task_id );
|
||||
uint16 HCI_ProcessEvent0( uint8 task_id, uint16 events );
|
||||
|
||||
|
||||
// ======= OSAL memory
|
||||
void osal_mem_init0(void);
|
||||
|
||||
// =========== ROM -> APP function
|
||||
void app_sleep_process(void);
|
||||
|
||||
void app_wakeup_process(void);
|
||||
|
||||
void rf_init(void);
|
||||
|
||||
void boot_init0(void);
|
||||
|
||||
void wakeup_init0(void);
|
||||
|
||||
void debug_print(uint32 state);
|
||||
|
||||
void rf_calibrate0(void);
|
||||
|
||||
void rf_phy_change_cfg(uint8 pktFmt);
|
||||
|
||||
// ========== A2, for conn-adv, conn-scan
|
||||
uint8 llSetupSecNonConnectableAdvEvt0( void );
|
||||
uint8 llSecAdvAllow0(void);
|
||||
uint32 llCalcMaxScanTime0(void);
|
||||
void llSetupSecScan0( uint8 chan );
|
||||
|
||||
uint8 llSetupSecAdvEvt0( void );
|
||||
uint8 llSetupSecConnectableAdvEvt0( void );
|
||||
uint8 llSetupSecScannableAdvEvt0( void );
|
||||
|
||||
|
||||
|
||||
//=============== gap_linkmgr.c
|
||||
void gapProcessDisconnectCompleteEvt0( hciEvt_DisconnComplete_t* pPkt );
|
||||
void gapProcessConnectionCompleteEvt0( hciEvt_BLEConnComplete_t* pPkt );
|
||||
|
||||
|
||||
//=============== l2cap_util.c
|
||||
uint8 l2capParsePacket0( l2capPacket_t* pPkt, hciDataEvent_t* pHciMsg );
|
||||
uint8 l2capEncapSendData0( uint16 connHandle, l2capPacket_t* pPkt );
|
||||
uint8 l2capPktToSegmentBuff0(uint16 connHandle, l2capSegmentBuff_t* pSegBuf, uint8 blen,uint8* pBuf);
|
||||
void l2capPocessFragmentTxData0(uint16 connHandle);
|
||||
uint8 l2capSegmentBuffToLinkLayer0(uint16 connHandle, l2capSegmentBuff_t* pSegBuf);
|
||||
void l2capPocessFragmentTxData0(uint16 connHandle);
|
||||
|
||||
//=============== DLE
|
||||
llStatus_t LL_SetDataLengh0( uint16 connId,uint16 TxOctets,uint16 TxTime );
|
||||
void llPduLengthUpdate0(uint16 connHandle);
|
||||
void llTrxNumAdaptiveConfig0(void);
|
||||
|
||||
//===============LL ADJ WINDOW
|
||||
void ll_adptive_adj_next_time0(uint32 nextTime);
|
||||
void ll_adptive_smart_window0(uint32 irq_status,uint32 anchor_point);
|
||||
void llSetNextDataChan0( llConnState_t* connPtr );
|
||||
|
||||
//=============== PHY UPDATE
|
||||
llStatus_t LL_SetPhyMode0( uint16 connId,uint8 allPhy,uint8 txPhy, uint8 rxPhy,uint16 phyOptions);
|
||||
llStatus_t LL_PhyUpdate0( uint16 connId );
|
||||
void llSetNextPhyMode0( llConnState_t* connPtr );
|
||||
|
||||
llStatus_t LL_PLUS_DisableSlaveLatency0(uint8 connId);
|
||||
llStatus_t LL_PLUS_EnableSlaveLatency0(uint8 connId);
|
||||
|
||||
// ================= BBB
|
||||
void ll_scheduler0(uint32 time);
|
||||
void ll_addTask0(uint8 connId, uint32 time);
|
||||
void ll_deleteTask0(uint8 connId);
|
||||
|
||||
void ll_adv_scheduler0(void);
|
||||
void ll_add_adv_task0(extAdvInfo_t* pExtAdv);
|
||||
void ll_delete_adv_task0(uint8 index);
|
||||
|
||||
void ll_adv_scheduler_periodic0(void);
|
||||
void ll_add_adv_task_periodic0(periodicAdvInfo_t* pPrdAdv, extAdvInfo_t* pExtAdv);
|
||||
void ll_delete_adv_task_periodic0(uint8 index);
|
||||
uint8 llSetupExtAdvEvent0(extAdvInfo_t* pAdvInfo);
|
||||
uint8 llSetupPrdAdvEvent0(periodicAdvInfo_t* pPrdAdv, extAdvInfo_t* pExtAdv);
|
||||
|
||||
void llSetupAdvExtIndPDU0(extAdvInfo_t* pAdvInfo, periodicAdvInfo_t* pPrdAdv);
|
||||
void llSetupAuxAdvIndPDU0(extAdvInfo_t* pAdvInfo, periodicAdvInfo_t* pPrdAdv);
|
||||
void llSetupAuxChainIndPDU0(extAdvInfo_t* pAdvInfo, periodicAdvInfo_t* pPrdAdv);
|
||||
void llSetupAuxSyncIndPDU0(extAdvInfo_t* pAdvInfo, periodicAdvInfo_t* pPrdAdv);
|
||||
void llSetupAuxConnectReqPDU0(void);
|
||||
void llSetupAuxScanRspPDU0(extAdvInfo_t* pAdvInfo);
|
||||
void llSetupAuxConnectRspPDU0(extAdvInfo_t* pAdvInfo);
|
||||
|
||||
uint8 llGetNextAuxAdvChn0(uint8 current);
|
||||
|
||||
|
||||
//=============== OSAL
|
||||
uint8 osal_set_event0( uint8 task_id, uint16 event_flag );
|
||||
uint8 osal_msg_send0( uint8 destination_task, uint8* msg_ptr );
|
||||
|
||||
//=============== _HAL_IRQ_
|
||||
void drv_irq_init0(void);
|
||||
int drv_enable_irq0(void);
|
||||
int drv_disable_irq0(void);
|
||||
|
||||
// 2020-02-13 cte jumpfunction
|
||||
llStatus_t LL_ConnectionlessCTE_TransmitParam0( uint8 advertising_handle,
|
||||
uint8 len,
|
||||
uint8 type,
|
||||
uint8 count,
|
||||
uint8 Pattern_LEN,
|
||||
uint8* AnaIDs);
|
||||
|
||||
llStatus_t LL_ConnectionlessCTE_TransmitEnable0( uint8 advertising_handle,uint8 enable);
|
||||
llStatus_t LL_ConnectionlessIQ_SampleEnable0( uint16 sync_handle,
|
||||
uint8 enable,
|
||||
uint8 slot_Duration,
|
||||
uint8 MaxSampledCTEs,
|
||||
uint8 pattern_len,
|
||||
uint8* AnaIDs);
|
||||
llStatus_t LL_Set_ConnectionCTE_ReceiveParam0( uint16 connHandle,
|
||||
uint8 enable,
|
||||
uint8 slot_Duration,
|
||||
uint8 pattern_len,
|
||||
uint8* AnaIDs);
|
||||
llStatus_t LL_Connection_CTE_Request_Enable0( uint16 connHandle,
|
||||
uint8 enable,
|
||||
uint16 Interval,
|
||||
uint8 len,
|
||||
uint8 type);
|
||||
|
||||
llStatus_t LL_Set_ConnectionCTE_TransmitParam0( uint16 connHandle,
|
||||
uint8 type,
|
||||
uint8 pattern_len,
|
||||
uint8* AnaIDs);
|
||||
|
||||
llStatus_t LL_Connection_CTE_Response_Enable0( uint16 connHandle,uint8 enable);
|
||||
|
||||
|
||||
#endif // _JUMP_FUNC_H_
|
||||
|
|
@ -73,7 +73,7 @@ void hard_fault(void)
|
|||
// item 1 - 4 for OSAL task entry
|
||||
// item 224 - 255 for ISR(Interrupt Service Routine) entry
|
||||
// others are reserved by ROM code
|
||||
const uint32_t* const jump_table_base[256] __attribute__((section("jump_table_mem_area"))) =
|
||||
const uint32_t* jump_table_base[256] __attribute__((section("jump_table_mem_area"))) =
|
||||
{
|
||||
(const uint32_t*)0, // 0. write Log
|
||||
(const uint32_t*)osalInitTasks, // 1. init entry of app
|
||||
|
|
@ -138,8 +138,4 @@ const uint32_t* const jump_table_base[256] __attribute__((section("jump_table_me
|
|||
/*********************************************************************
|
||||
EXTERNAL VARIABLES
|
||||
*/
|
||||
//uint32 global_config[SOFT_PARAMETER_NUM] __attribute__((section("global_config_area")));
|
||||
|
||||
|
||||
|
||||
|
||||
uint32 global_config[SOFT_PARAMETER_NUM] __attribute__((section("global_config_area")));
|
||||
|
|
|
|||
|
|
@ -1,11 +1,20 @@
|
|||
|
||||
/* SRAM + XIP linker script */
|
||||
/* https://docs.oracle.com/cd/E19120-01/open.solaris/819-0690/6n33n7fds/index.html */
|
||||
PHDRS
|
||||
{
|
||||
romdata PT_LOAD FLAGS(6);
|
||||
text PT_LOAD FLAGS(5);
|
||||
data PT_LOAD FLAGS(6);
|
||||
xip PT_LOAD FLAGS(5);
|
||||
rodata PT_LOAD FLAGS(4);
|
||||
}
|
||||
|
||||
MEMORY
|
||||
{
|
||||
jumptbl (rwx) : ORIGIN = 0x1fff0000, LENGTH = 0x00400
|
||||
jumptbl (rw) : ORIGIN = 0x1fff0000, LENGTH = 0x00400
|
||||
gcfgtbl (rw) : ORIGIN = 0x1fff0400, LENGTH = 0x00400
|
||||
flash (rx) : ORIGIN = 0x11020000, LENGTH = 0x20000
|
||||
sram (rwx) : ORIGIN = 0x1fff1838, LENGTH = 0x0E7C8
|
||||
sram (rwx) : ORIGIN = 0x1fff1838, LENGTH = 0x0E7C8
|
||||
flash (rx) : ORIGIN = 0x11020000, LENGTH = 0x20000
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
|
|
@ -15,20 +24,21 @@ ENTRY(__start)
|
|||
SECTIONS
|
||||
{
|
||||
.jumptbl : {
|
||||
KEEP(*(jump_table_mem_area))
|
||||
} > jumptbl
|
||||
*(jump_table_mem_area)
|
||||
} > jumptbl : romdata
|
||||
|
||||
.gcfgtbl : {
|
||||
*(global_config_area)
|
||||
.gcfgtbl (NOLOAD) : {
|
||||
*(global_config_area)
|
||||
} > gcfgtbl
|
||||
|
||||
.textentry : {
|
||||
*(*.isr_vector)
|
||||
} > sram
|
||||
} > sram : text
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
_sdata = ABSOLUTE(.);
|
||||
.text : {
|
||||
_stextram = ABSOLUTE(.);
|
||||
|
||||
*phy6222_start.o(.text)
|
||||
*.o(_section_standby_code_)
|
||||
*.o(_section_sram_code_)
|
||||
|
|
@ -48,13 +58,15 @@ SECTIONS
|
|||
*libgcc.a:*.o(.text .text.*)
|
||||
|
||||
_etextram = ABSOLUTE(.);
|
||||
} > sram : text
|
||||
|
||||
.data : {
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram
|
||||
} > sram : data
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
|
|
@ -65,20 +77,23 @@ SECTIONS
|
|||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/*
|
||||
.int_stack : {
|
||||
. = ALIGN(4);
|
||||
*(int_stack)
|
||||
. = ALIGN(4);
|
||||
_stack_top = ABSOLUTE(.);
|
||||
.irq_stack : {
|
||||
*(g_irqstack_base)
|
||||
} > sram
|
||||
*/
|
||||
|
||||
g_top_irqstack = ORIGIN(sram) + LENGTH(sram);
|
||||
g_stack = ORIGIN(sram) + LENGTH(sram);
|
||||
|
||||
.common_text : {
|
||||
.xip : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
|
||||
*.o(_func_xip_code_)
|
||||
*.o(_section_xip_code_)
|
||||
*(.text .text.*)
|
||||
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash : xip
|
||||
|
||||
.rodata : {
|
||||
*(.rodata .rodata.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
|
|
@ -89,29 +104,27 @@ SECTIONS
|
|||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
} > flash : rodata
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
*(.init_array .init_array.*)
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
} > flash : rodata
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
} > flash : rodata
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
} > flash : rodata
|
||||
|
||||
._sjtblsstore : {
|
||||
_sjtblss = ABSOLUTE(.);
|
||||
} > flash
|
||||
} > flash : rodata
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
|
|
|
|||
|
|
@ -152,19 +152,16 @@ static void hal_low_power_io_init(void) {
|
|||
DCDC_REF_CLK_SETTING(1);
|
||||
DIG_LDO_CURRENT_SETTING(0x01);
|
||||
#if defined ( __GNUC__ )
|
||||
extern int _ebss;
|
||||
/*
|
||||
if ((uint32_t) &_ebss >= (0x20000000 - 0x400)) { // - INITIAL_STACK 1kbytes
|
||||
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2); // RET_SRAM0|RET_SRAM1|RET_SRAM2
|
||||
pGlobal_config[INITIAL_STACK_PTR] = 0x20000000;
|
||||
} else
|
||||
*/
|
||||
if ((uint32_t) &_ebss >= (0x1fff8000 - 0x400)) { // - INITIAL_STACK 1kbytes
|
||||
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1); // RET_SRAM0|RET_SRAM1|RET_SRAM2
|
||||
pGlobal_config[INITIAL_STACK_PTR] = 0x1fffC000;
|
||||
extern uint32 g_irqstack_top;
|
||||
// Check IRQ STACK (1KB) location
|
||||
if ((uint32_t) &g_irqstack_top > 0x1fff8000) {
|
||||
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1);
|
||||
// pGlobal_config[INITIAL_STACK_PTR] = 0x1fffC000;
|
||||
} else if ((uint32_t) &g_irqstack_top > 0x1fffc000) {
|
||||
hal_pwrmgr_RAM_retention(RET_SRAM0 | RET_SRAM1 | RET_SRAM2);
|
||||
} else {
|
||||
hal_pwrmgr_RAM_retention(RET_SRAM0); // RET_SRAM0|RET_SRAM1|RET_SRAM2
|
||||
pGlobal_config[INITIAL_STACK_PTR] = 0x1fff8000;
|
||||
// pGlobal_config[INITIAL_STACK_PTR] = 0x1fff8000;
|
||||
}
|
||||
#else
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue