329 lines
11 KiB
C++
329 lines
11 KiB
C++
/*---------------------------------------------------------*\
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| KingstonFuryDRAMControllerDetect.cpp |
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| Detection of Kingston Fury DDR4/5 RAM modules |
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| Geofrey Mon (geofbot) 14 Jul 2024 |
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| Milan Cermak (krysmanta) |
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| This file is part of the OpenRGB project |
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| SPDX-License-Identifier: GPL-2.0-only |
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\*---------------------------------------------------------*/
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#include <vector>
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#include "Detector.h"
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#include "KingstonFuryDRAMController.h"
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#include "LogManager.h"
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#include "RGBController_KingstonFuryDRAM.h"
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#include "i2c_smbus.h"
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#include "pci_ids.h"
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using namespace std::chrono_literals;
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typedef enum
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{
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RESULT_PASS = 0,
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RESULT_FAIL = 1,
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RESULT_ERROR = 2
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} TestResult;
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typedef enum
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{
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SPD_RESERVED = 0,
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SPD_FPM_DRAM = 1,
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SPD_EDO = 2,
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SPD_NIBBLE = 3,
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SPD_SDR_SDRAM = 4,
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SPD_MUX_ROM = 5,
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SPD_DDR_SGRAM = 6,
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SPD_DDR_SDRAM = 7,
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SPD_DDR2_SDRAM = 8,
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SPD_FB_DIMM = 9,
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SPD_FB_PROBE = 10,
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SPD_DDR3_SDRAM = 11,
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SPD_DDR4_SDRAM = 12,
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SPD_RESERVED2 = 13,
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SPD_DDR4E_SDRAM = 14,
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SPD_LPDDR3_SDRAM = 15,
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SPD_LPDDR4_SDRAM = 16,
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SPD_LPDDR4X_SDRAM = 17,
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SPD_DDR5_SDRAM = 18,
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SPD_LPDDR5_SDRAM = 19
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} SPDMemoryType;
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// DDR5 SPD hub detection
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TestResult TestForSPDHub(i2c_smbus_interface *bus, int spd_address, int &mem_type)
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{
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int ddr5Magic = bus->i2c_smbus_read_byte_data(spd_address, 0x00);
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int ddr5Sensor = bus->i2c_smbus_read_byte_data(spd_address, 0x01);
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std::this_thread::sleep_for(1ms);
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if(ddr5Magic < 0 || ddr5Sensor < 0)
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{
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return RESULT_ERROR;
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}
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if(ddr5Magic == 0x51 && (ddr5Sensor & 0xEF) == 0x08)
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{
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// These values are invalid for any other memory type
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mem_type = SPD_DDR5_SDRAM;
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return RESULT_PASS;
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}
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return RESULT_FAIL;
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}
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TestResult TestSPDForKingston(i2c_smbus_interface *bus, SPDMemoryType &fury_type, std::vector<int> &slots)
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{
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int mem_type = -1;
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for(int slot_index = 0; slot_index < FURY_MAX_SLOTS; slot_index++)
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{
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int spd_address = 0x50 + slot_index;
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TestResult result = TestForSPDHub(bus, spd_address, mem_type);
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if(result == RESULT_ERROR)
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{
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LOG_TRACE("[%s] SPD Hub check [0x%02X] failed. No device.",
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FURY_CONTROLLER_NAME, spd_address);
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continue;
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}
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if(mem_type != SPD_DDR4_SDRAM && mem_type != SPD_DDR5_SDRAM)
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{
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// Get memory type from SPD for DDR4 or older
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bus->i2c_smbus_write_byte_data(0x36, 0x00, 0xFF);
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std::this_thread::sleep_for(1ms);
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mem_type = bus->i2c_smbus_read_byte_data(spd_address, 0x02);
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}
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if(mem_type != SPD_DDR4_SDRAM && mem_type != SPD_DDR5_SDRAM)
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{
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LOG_TRACE("[%s] SPD check [0x%02X] - wrong memory type => %02X",
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FURY_CONTROLLER_NAME, spd_address, mem_type);
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continue;
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}
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fury_type = static_cast<SPDMemoryType>(mem_type);
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LOG_TRACE("[%s] SPD check [0x%02X]: memory type => %02X, ",
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FURY_CONTROLLER_NAME, spd_address, mem_type);
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// Switch SPD page
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if(mem_type == SPD_DDR4_SDRAM)
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{
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bus->i2c_smbus_write_byte_data(0x37, 0x00, 0xFF);
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}
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else
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{
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bus->i2c_smbus_write_byte_data(spd_address, 0x0B, 4);
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}
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std::this_thread::sleep_for(1ms);
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// Get ManufacturerID
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int vendorHi, vendorLo;
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if(mem_type == SPD_DDR4_SDRAM)
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{
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vendorHi = bus->i2c_smbus_read_byte_data(spd_address, 0x40);
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vendorLo = bus->i2c_smbus_read_byte_data(spd_address, 0x41);
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}
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else
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{
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vendorHi = bus->i2c_smbus_read_byte_data(spd_address, 0x80);
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vendorLo = bus->i2c_smbus_read_byte_data(spd_address, 0x81);
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}
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std::this_thread::sleep_for(1ms);
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LOG_DEBUG("[%s] SPD check [0x%02X]: vendorHi => %02X, vendorLo => %02X, ",
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FURY_CONTROLLER_NAME, spd_address, vendorHi, vendorLo);
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// Switch SPD page back to 0
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if(mem_type == SPD_DDR4_SDRAM)
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{
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bus->i2c_smbus_write_byte_data(0x36, 0x00, 0xFF);
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}
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else
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{
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bus->i2c_smbus_write_byte_data(spd_address, 0x0B, 0);
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}
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std::this_thread::sleep_for(1ms);
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if(vendorHi == 0x01 && vendorLo == 0x98)
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{
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slots.push_back(slot_index);
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}
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}
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return RESULT_PASS;
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}
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bool TestDDR4Models(char code)
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{
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return (code == FURY_MODEL_BEAST_WHITE_DDR4 ||
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code == FURY_MODEL_BEAST_DDR4);
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}
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bool TestDDR5Models(char code)
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{
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return (code == FURY_MODEL_BEAST_DDR5 ||
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code == FURY_MODEL_RENEGADE_DDR5 ||
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code == FURY_MODEL_BEAST_RGB_WHITE_DDR5);
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}
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// Checking Fury signature in the RGB address space
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TestResult TestForFurySignature(i2c_smbus_interface *bus, unsigned int slot_addr, bool (*modelChecker)(char))
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{
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bool passed = true;
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char test_str[] = "FURY";
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int res;
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// Start transaction
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res = bus->i2c_smbus_write_byte_data(slot_addr, FURY_REG_APPLY, FURY_BEGIN_TRNSFER);
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if(res < 0)
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{
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return RESULT_ERROR;
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}
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std::this_thread::sleep_for(FURY_DELAY);
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LOG_DEBUG("[%s] %02X beginning transaction; res=%02X",
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FURY_CONTROLLER_NAME, slot_addr, res);
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// Read and check the signature
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for(int i = 1; i <= 4; i++)
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{
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for(int retry = 3; retry > 0; retry--)
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{
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res = bus->i2c_smbus_read_word_data(slot_addr, i);
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std::this_thread::sleep_for(FURY_DELAY);
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if(res >= 0)
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{
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break;
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}
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}
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if(res < 0)
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{
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return RESULT_ERROR;
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}
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char shifted = (res >> 8) & 0xFF;
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LOG_DEBUG("[%s] Testing address %02X register %02X, res=%02X",
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FURY_CONTROLLER_NAME, slot_addr, i, shifted);
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if(shifted != test_str[i-1])
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{
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passed = false;
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break;
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}
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}
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if(passed)
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{
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// Get the model code
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res = bus->i2c_smbus_read_word_data(slot_addr, FURY_REG_MODEL);
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int model_code = res >> 8;
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std::this_thread::sleep_for(FURY_DELAY);
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LOG_DEBUG("[%s] Reading model code at address %02X register %02X, res=%02X",
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FURY_CONTROLLER_NAME, slot_addr, FURY_REG_MODEL, res);
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if(!modelChecker(model_code))
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{
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LOG_INFO("[%s] Unknown model code 0x%02X", FURY_CONTROLLER_NAME, model_code);
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passed = false;
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}
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}
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// Close transaction
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res = bus->i2c_smbus_write_byte_data(slot_addr, FURY_REG_APPLY, FURY_END_TRNSFER);
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if(res < 0)
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{
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return RESULT_ERROR;
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}
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std::this_thread::sleep_for(FURY_DELAY);
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LOG_DEBUG("[%s] %02X ending transaction; res=%02X",
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FURY_CONTROLLER_NAME, slot_addr, res);
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return passed ? RESULT_PASS : RESULT_FAIL;
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}
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/******************************************************************************************\
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* *
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* DetectKingstonFuryDRAMControllers *
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* *
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* Detect Kingston Fury DDR4/5 DRAM controllers on the enumerated I2C busses. *
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* *
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\******************************************************************************************/
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void DetectKingstonFuryDRAMControllers(std::vector<i2c_smbus_interface*> &busses)
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{
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SPDMemoryType fury_type = SPD_RESERVED;
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for(unsigned int bus = 0; bus < busses.size(); bus++)
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{
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IF_DRAM_SMBUS(busses[bus]->pci_vendor, busses[bus]->pci_device)
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{
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TestResult result;
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std::vector<int> occupied_slots, fury_slots;
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int fury_base_addr;
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bool (*modelChecker)(char);
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// Do we have Kingston DRAMs?
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result = TestSPDForKingston(busses[bus], fury_type, occupied_slots);
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if(result != RESULT_PASS || (fury_type != SPD_DDR4_SDRAM && fury_type != SPD_DDR5_SDRAM))
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{
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continue;
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}
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if(fury_type == SPD_DDR4_SDRAM)
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{
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fury_base_addr = FURY_BASE_ADDR_DDR4;
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modelChecker = TestDDR4Models;
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}
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else
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{
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fury_base_addr = FURY_BASE_ADDR_DDR5;
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modelChecker = TestDDR5Models;
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}
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// Are these the Kingston Fury DRAMs
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for(int slot_index : occupied_slots)
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{
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int retries = 0;
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result = RESULT_ERROR;
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while(retries < 3 && result == RESULT_ERROR)
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{
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result = TestForFurySignature(busses[bus],
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fury_base_addr + slot_index, modelChecker);
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if(result == RESULT_PASS)
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{
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break;
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}
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if(result == RESULT_ERROR)
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{
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// I/O error - wait for a bit and retry
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retries++;
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std::this_thread::sleep_for(100ms);
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}
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}
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// RAM module successfully detected in the slot 'slot_index'
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if(result == RESULT_PASS)
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{
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LOG_DEBUG("[%s] detected at slot index %d",
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FURY_CONTROLLER_NAME, slot_index);
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fury_slots.push_back(slot_index);
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}
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}
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if(!fury_slots.empty())
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{
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unsigned char base_addr =
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(fury_type == SPD_DDR4_SDRAM) ? FURY_BASE_ADDR_DDR4 : FURY_BASE_ADDR_DDR5;
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KingstonFuryDRAMController* controller =
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new KingstonFuryDRAMController(busses[bus], base_addr, fury_slots);
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RGBController_KingstonFuryDRAM* rgb_controller =
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new RGBController_KingstonFuryDRAM(controller);
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rgb_controller->name =
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(fury_type == SPD_DDR4_SDRAM) ? "Kingston Fury DDR4 RGB" : "Kingston Fury DDR5 RGB";
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ResourceManager::get()->RegisterRGBController(rgb_controller);
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}
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}
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}
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}
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REGISTER_I2C_DETECTOR("Kingston Fury DDR4/5 DRAM", DetectKingstonFuryDRAMControllers);
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