576 lines
18 KiB
C++
576 lines
18 KiB
C++
/*-----------------------------------------*\
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| i2c_smbus_i801.cpp |
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| i801 SMBUS driver for Windows |
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| Adam Honse (CalcProgrammer1) 1/29/2019 |
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| Portions based on Linux source code |
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| GNU GPL v2 |
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\*-----------------------------------------*/
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#include "i2c_smbus_i801.h"
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#include <Windows.h>
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#include "OlsApi.h"
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#include "LogManager.h"
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using namespace std::chrono_literals;
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/* Return negative errno on error. */
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s32 i2c_smbus_i801::i801_access(u16 addr, char read_write, u8 command, int size, i2c_smbus_data *data)
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{
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int hwpec = 0;
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int block = 0;
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int ret = 0, xact = 0;
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//struct i801_priv *priv = i2c_get_adapdata(adap);
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//mutex_lock(&priv->acpi_lock);
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//if (priv->acpi_reserved) {
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// mutex_unlock(&priv->acpi_lock);
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// return -EBUSY;
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//}
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//pm_runtime_get_sync(&priv->pci_dev->dev);
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//hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
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// && size != I2C_SMBUS_QUICK
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// && size != I2C_SMBUS_I2C_BLOCK_DATA;
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switch (size)
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{
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case I2C_SMBUS_QUICK:
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WriteIoPortByte(SMBHSTADD, ((addr & 0x7f) << 1) | (read_write & 0x01));
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xact = I801_QUICK;
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break;
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case I2C_SMBUS_BYTE:
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WriteIoPortByte(SMBHSTADD, ((addr & 0x7f) << 1) | (read_write & 0x01));
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if (read_write == I2C_SMBUS_WRITE)
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WriteIoPortByte(SMBHSTCMD, command);
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xact = I801_BYTE;
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break;
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case I2C_SMBUS_BYTE_DATA:
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WriteIoPortByte(SMBHSTADD, ((addr & 0x7f) << 1) | (read_write & 0x01));
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WriteIoPortByte(SMBHSTCMD, command);
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if (read_write == I2C_SMBUS_WRITE)
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WriteIoPortByte(SMBHSTDAT0, data->byte);
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xact = I801_BYTE_DATA;
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break;
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case I2C_SMBUS_WORD_DATA:
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WriteIoPortByte(SMBHSTADD, ((addr & 0x7f) << 1) | (read_write & 0x01));
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WriteIoPortByte(SMBHSTCMD, command);
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if (read_write == I2C_SMBUS_WRITE)
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{
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WriteIoPortByte(SMBHSTDAT0, data->word & 0xff);
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WriteIoPortByte(SMBHSTDAT1, (data->word & 0xff00) >> 8);
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}
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xact = I801_WORD_DATA;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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WriteIoPortByte(SMBHSTADD, ((addr & 0x7f) << 1) | (read_write & 0x01));
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WriteIoPortByte(SMBHSTCMD, command);
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block = 1;
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break;
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case I2C_SMBUS_I2C_BLOCK_DATA:
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/*
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* NB: page 240 of ICH5 datasheet shows that the R/#W
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* bit should be cleared here, even when reading.
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* However if SPD Write Disable is set (Lynx Point and later),
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* the read will fail if we don't set the R/#W bit.
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*/
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WriteIoPortByte(SMBHSTADD, ((addr & 0x7f) << 1) | (read_write & 0x01));
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if (read_write == I2C_SMBUS_READ)
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{
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/* NB: page 240 of ICH5 datasheet also shows
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* that DATA1 is the cmd field when reading */
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WriteIoPortByte(SMBHSTDAT1, command);
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}
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else
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{
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WriteIoPortByte(SMBHSTCMD, command);
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}
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block = 1;
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break;
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default:
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ret = -EOPNOTSUPP;
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goto out;
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}
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//if (hwpec) /* enable/disable hardware PEC */
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// outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
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//else
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WriteIoPortByte(SMBAUXCTL, ReadIoPortByte(SMBAUXCTL) & (~SMBAUXCTL_CRC));
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if (block)
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ret = i801_block_transaction(data, read_write, size, hwpec);
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else
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ret = i801_transaction(xact);
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/* Some BIOSes don't like it when PEC is enabled at reboot or resume
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time, so we forcibly disable it after every transaction. Turn off
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E32B for the same reason. */
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//if (hwpec || block)
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WriteIoPortByte(SMBAUXCTL, ReadIoPortByte(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B));
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if (block)
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goto out;
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if (ret)
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goto out;
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if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
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goto out;
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switch (xact & 0x7f)
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{
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case I801_BYTE: /* Result put in SMBHSTDAT0 */
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case I801_BYTE_DATA:
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data->byte = ReadIoPortByte(SMBHSTDAT0);
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break;
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case I801_WORD_DATA:
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data->word = ReadIoPortByte(SMBHSTDAT0) + (ReadIoPortByte(SMBHSTDAT1) << 8);
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break;
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}
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out:
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//pm_runtime_mark_last_busy(&priv->pci_dev->dev);
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//pm_runtime_put_autosuspend(&priv->pci_dev->dev);
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//mutex_unlock(&priv->acpi_lock);
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return ret;
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}
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/* Block transaction function */
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int i2c_smbus_i801::i801_block_transaction(i2c_smbus_data *data, char read_write, int command, int hwpec)
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{
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int result = 0;
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unsigned char hostc;
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//if (command == I2C_SMBUS_I2C_BLOCK_DATA)
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//{
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// if (read_write == I2C_SMBUS_WRITE)
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// {
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// /* set I2C_EN bit in configuration register */
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// pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
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// pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
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// hostc | SMBHSTCFG_I2C_EN);
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// }
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// else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
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// dev_err(&priv->pci_dev->dev,
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// "I2C block read is unsupported!\n");
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// return -EOPNOTSUPP;
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// }
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//}
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if (read_write == I2C_SMBUS_WRITE || command == I2C_SMBUS_I2C_BLOCK_DATA)
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{
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if (data->block[0] < 1)
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data->block[0] = 1;
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if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
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data->block[0] = I2C_SMBUS_BLOCK_MAX;
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}
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else
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{
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data->block[0] = 32; /* max for SMBus block reads */
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}
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/* Experience has shown that the block buffer can only be used for
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SMBus (not I2C) block transactions, even though the datasheet
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doesn't mention this limitation. */
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//if ((priv->features & FEATURE_BLOCK_BUFFER)
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// && command != I2C_SMBUS_I2C_BLOCK_DATA
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// && i801_set_block_buffer_mode(priv) == 0)
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// result = i801_block_transaction_by_block(priv, data,
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// read_write, hwpec);
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//else
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result = i801_block_transaction_byte_by_byte(data, read_write, command, hwpec);
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//if (command == I2C_SMBUS_I2C_BLOCK_DATA
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// && read_write == I2C_SMBUS_WRITE) {
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// /* restore saved configuration register value */
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// pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
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//}
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return result;
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}
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/*
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* For "byte-by-byte" block transactions:
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* I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
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* I2C read uses cmd=I801_I2C_BLOCK_DATA
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*/
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int i2c_smbus_i801::i801_block_transaction_byte_by_byte(i2c_smbus_data *data, char read_write, int command, int hwpec)
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{
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int i, len;
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int smbcmd;
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int status;
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int result;
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result = i801_check_pre();
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if (result < 0)
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return result;
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len = data->block[0];
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if (read_write == I2C_SMBUS_WRITE)
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{
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WriteIoPortByte(SMBHSTDAT0, len);
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WriteIoPortByte(SMBBLKDAT, data->block[1]);
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}
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if (command == I2C_SMBUS_I2C_BLOCK_DATA && read_write == I2C_SMBUS_READ)
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smbcmd = I801_I2C_BLOCK_DATA;
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else
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smbcmd = I801_BLOCK_DATA;
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//if (priv->features & FEATURE_IRQ) {
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// priv->is_read = (read_write == I2C_SMBUS_READ);
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// if (len == 1 && priv->is_read)
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// smbcmd |= SMBHSTCNT_LAST_BYTE;
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// priv->cmd = smbcmd | SMBHSTCNT_INTREN;
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// priv->len = len;
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// priv->count = 0;
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// priv->data = &data->block[1];
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//
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// outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
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// result = wait_event_timeout(priv->waitq,
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// (status = priv->status),
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// adap->timeout);
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// if (!result) {
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// status = -ETIMEDOUT;
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// dev_warn(&priv->pci_dev->dev,
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// "Timeout waiting for interrupt!\n");
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// }
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// priv->status = 0;
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// return i801_check_post(priv, status);
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//}
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for (i = 1; i <= len; i++)
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{
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if (i == len && read_write == I2C_SMBUS_READ)
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smbcmd |= SMBHSTCNT_LAST_BYTE;
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WriteIoPortByte(SMBHSTCNT, smbcmd);
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if (i == 1)
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WriteIoPortByte(SMBHSTCNT, ReadIoPortByte(SMBHSTCNT) | SMBHSTCNT_START);
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status = i801_wait_byte_done();
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if (status)
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goto exit;
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if (i == 1 && read_write == I2C_SMBUS_READ && command != I2C_SMBUS_I2C_BLOCK_DATA)
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{
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len = ReadIoPortByte(SMBHSTDAT0);
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if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
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{
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/* Recover */
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while (ReadIoPortByte(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
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WriteIoPortByte(SMBHSTSTS, SMBHSTSTS_BYTE_DONE);
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WriteIoPortByte(SMBHSTSTS, SMBHSTSTS_INTR);
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return -EPROTO;
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}
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data->block[0] = len;
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}
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/* Retrieve/store value in SMBBLKDAT */
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if (read_write == I2C_SMBUS_READ)
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data->block[i] = ReadIoPortByte(SMBBLKDAT);
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if (read_write == I2C_SMBUS_WRITE && i + 1 <= len)
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WriteIoPortByte(SMBBLKDAT, data->block[i + 1]);
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/* signals SMBBLKDAT ready */
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WriteIoPortByte(SMBHSTSTS, SMBHSTSTS_BYTE_DONE);
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}
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status = i801_wait_intr();
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exit:
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return i801_check_post(status);
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}
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/*
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* Convert the status register to an error code, and clear it.
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* Note that status only contains the bits we want to clear, not the
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* actual register value.
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*/
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int i2c_smbus_i801::i801_check_post(int status)
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{
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int result = 0;
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/*
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* If the SMBus is still busy, we give up
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* Note: This timeout condition only happens when using polling
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* transactions. For interrupt operation, NAK/timeout is indicated by
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* DEV_ERR.
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*/
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if (status < 0)
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{
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/* try to stop the current command */
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WriteIoPortByte(SMBHSTCNT, ReadIoPortByte(SMBHSTCNT) | SMBHSTCNT_KILL);
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//usleep_range(1000, 2000);
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std::this_thread::sleep_for(1ms);
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WriteIoPortByte(SMBHSTCNT, ReadIoPortByte(SMBHSTCNT) & (~SMBHSTCNT_KILL));
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WriteIoPortByte(SMBHSTSTS, STATUS_FLAGS);
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return -ETIMEDOUT;
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}
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if (status & SMBHSTSTS_FAILED)
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{
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result = -EIO;
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}
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if (status & SMBHSTSTS_DEV_ERR)
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{
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/*
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* This may be a PEC error, check and clear it.
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*
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* AUXSTS is handled differently from HSTSTS.
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* For HSTSTS, i801_isr() or i801_wait_intr()
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* has already cleared the error bits in hardware,
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* and we are passed a copy of the original value
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* in "status".
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* For AUXSTS, the hardware register is left
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* for us to handle here.
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* This is asymmetric, slightly iffy, but safe,
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* since all this code is serialized and the CRCE
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* bit is harmless as long as it's cleared before
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* the next operation.
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*/
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//if ((priv->features & FEATURE_SMBUS_PEC) &&
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// (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
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// outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
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// result = -EBADMSG;
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// dev_dbg(&priv->pci_dev->dev, "PEC error\n");
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//}
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//else {
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result = -ENXIO;
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// dev_dbg(&priv->pci_dev->dev, "No response\n");
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//}
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}
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if (status & SMBHSTSTS_BUS_ERR)
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{
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result = -EAGAIN;
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}
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/* Clear status flags except BYTE_DONE, to be cleared by caller */
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WriteIoPortByte(SMBHSTSTS, status);
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return result;
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}
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/* Make sure the SMBus host is ready to start transmitting.
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Return 0 if it is, -EBUSY if it is not. */
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int i2c_smbus_i801::i801_check_pre()
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{
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int status;
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status = ReadIoPortByte(SMBHSTSTS);
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if (status & SMBHSTSTS_HOST_BUSY)
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{
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return -EBUSY;
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}
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status &= STATUS_FLAGS;
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if (status)
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{
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WriteIoPortByte(SMBHSTSTS, status);
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status = ReadIoPortByte(SMBHSTSTS) & STATUS_FLAGS;
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if (status)
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{
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return -EBUSY;
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}
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}
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/*
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* Clear CRC status if needed.
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* During normal operation, i801_check_post() takes care
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* of it after every operation. We do it here only in case
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* the hardware was already in this state when the driver
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* started.
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*/
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//if (priv->features & FEATURE_SMBUS_PEC) {
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// status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
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// if (status) {
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// dev_dbg(&priv->pci_dev->dev,
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// "Clearing aux status flags (%02x)\n", status);
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// outb_p(status, SMBAUXSTS(priv));
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// status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
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// if (status) {
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// dev_err(&priv->pci_dev->dev,
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// "Failed clearing aux status flags (%02x)\n",
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// status);
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// return -EBUSY;
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// }
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// }
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//}
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return 0;
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}
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int i2c_smbus_i801::i801_transaction(int xact)
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{
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int status;
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int result;
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result = i801_check_pre();
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if (result < 0)
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return result;
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WriteIoPortByte(SMBHSTCNT, ReadIoPortByte(SMBHSTCNT) & ~SMBHSTCNT_INTREN);
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//if (priv->features & FEATURE_IRQ)
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//{
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// outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
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// SMBHSTCNT(priv));
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// result = wait_event_timeout(priv->waitq,
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// (status = priv->status),
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// adap->timeout);
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// if (!result) {
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// status = -ETIMEDOUT;
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// dev_warn(&priv->pci_dev->dev,
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// "Timeout waiting for interrupt!\n");
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// }
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// priv->status = 0;
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// return i801_check_post(priv, status);
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//}
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/* the current contents of SMBHSTCNT can be overwritten, since PEC,
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* SMBSCMD are passed in xact */
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WriteIoPortByte(SMBHSTCNT, xact | SMBHSTCNT_START);
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status = i801_wait_intr();
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return i801_check_post(status);
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}
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/* Wait for either BYTE_DONE or an error flag being set */
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int i2c_smbus_i801::i801_wait_byte_done()
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{
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int timeout = 0;
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int status;
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/* We will always wait for a fraction of a second! */
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do
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{
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std::this_thread::sleep_for(1ms);
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//usleep_range(250, 500);
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status = ReadIoPortByte(SMBHSTSTS);
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} while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && (timeout++ < MAX_RETRIES));
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if (timeout > MAX_RETRIES)
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{
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return -ETIMEDOUT;
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}
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return status & STATUS_ERROR_FLAGS;
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}
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/* Wait for BUSY being cleared and either INTR or an error flag being set */
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int i2c_smbus_i801::i801_wait_intr()
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{
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int timeout = 0;
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int status;
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/* We will always wait for a fraction of a second! */
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do
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{
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//usleep_range(250, 500);
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status = ReadIoPortByte(SMBHSTSTS);
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} while (((status & SMBHSTSTS_HOST_BUSY) || !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && (timeout++ < MAX_RETRIES));
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if (timeout > MAX_RETRIES)
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{
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return -ETIMEDOUT;
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}
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return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
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}
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s32 i2c_smbus_i801::i2c_smbus_xfer(u8 addr, char read_write, u8 command, int size, i2c_smbus_data* data)
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{
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return i801_access(addr, read_write, command, size, data);
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}
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s32 i2c_smbus_i801::i2c_xfer(u8 addr, char read_write, int* size, u8* data)
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{
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return -1;
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}
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#include "Detector.h"
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#include "wmi.h"
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bool i2c_smbus_i801_detect()
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{
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if(!InitializeOls() || GetDllStatus())
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{
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LOG_INFO("WinRing0 is not loaded, i801 I2C bus detection aborted");
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return(false);
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}
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i2c_smbus_interface * bus;
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HRESULT hres;
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Wmi wmi;
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// Query WMI for Win32_PnPSignedDriver entries with names matching "SMBUS" or "SM BUS"
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// These devices may be browsed under Device Manager -> System Devices
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std::vector<QueryObj> q_res_PnPSignedDriver;
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hres = wmi.query("SELECT * FROM Win32_PnPSignedDriver WHERE Description LIKE '\%SMBUS\%' OR Description LIKE '\%SM BUS\%'", q_res_PnPSignedDriver);
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if (hres)
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{
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LOG_INFO("WMI query failed, i801 I2C bus detection aborted");
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return(false);
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}
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// For each detected SMBus adapter, try enumerating it as either AMD or Intel
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for (QueryObj &i : q_res_PnPSignedDriver)
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{
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// Intel SMBus controllers do show I/O resources in Device Manager
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// Analysis of many Intel boards has shown that Intel SMBus adapter I/O space varies between boards
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// We can query Win32_PnPAllocatedResource entries and look up the PCI device ID to find the allocated I/O space
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// Intel SMBus adapters use the i801 driver
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if ((i["Manufacturer"].find("Intel") != std::string::npos)
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|| (i["Manufacturer"].find("INTEL") != std::string::npos))
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{
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std::string rgx1 = ".+" + q_res_PnPSignedDriver[0]["DeviceID"].substr(4, 33) + ".+";
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AdditionalFilters filters;
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filters.emplace("Dependent", rgx1);
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filters.emplace("Antecedent", ".*Port.*");
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std::vector<QueryObj> q_res_PNPAllocatedResource;
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hres = wmi.query("SELECT * FROM Win32_PnPAllocatedResource", q_res_PNPAllocatedResource, &filters);
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std::regex rgx2(".*StartingAddress=\"(\\d+)\".*");
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std::smatch matches;
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// Query the StartingAddress for the matching device ID and use it to enumerate the bus
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if (std::regex_search(q_res_PNPAllocatedResource[0]["Antecedent"], matches, rgx2))
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{
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unsigned int IORangeStart = std::stoi(matches[1].str());
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std::string pnp_str = i["DeviceID"];
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std::size_t ven_loc = pnp_str.find("VEN_");
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std::size_t dev_loc = pnp_str.find("DEV_");
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std::size_t sub_loc = pnp_str.find("SUBSYS_");
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std::string ven_str = pnp_str.substr(ven_loc + 4, 4);
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std::string dev_str = pnp_str.substr(dev_loc + 4, 4);
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std::string sbv_str = pnp_str.substr(sub_loc + 11, 4);
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std::string sbd_str = pnp_str.substr(sub_loc + 7, 4);
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int ven_id = (int)std::stoul(ven_str, nullptr, 16);
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int dev_id = (int)std::stoul(dev_str, nullptr, 16);
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int sbv_id = (int)std::stoul(sbv_str, nullptr, 16);
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int sbd_id = (int)std::stoul(sbd_str, nullptr, 16);
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bus = new i2c_smbus_i801();
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bus->pci_vendor = ven_id;
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bus->pci_device = dev_id;
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bus->pci_subsystem_vendor = sbv_id;
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bus->pci_subsystem_device = sbd_id;
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strcpy(bus->device_name, i["Description"].c_str());
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((i2c_smbus_i801 *)bus)->i801_smba = IORangeStart;
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ResourceManager::get()->RegisterI2CBus(bus);
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}
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}
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}
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return(true);
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}
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REGISTER_I2C_BUS_DETECTOR(i2c_smbus_i801_detect);
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