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Add debug logs to HyperX DRAM detector

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This commit is contained in:
morg 2021-11-12 13:59:00 +01:00
parent 8900cb00e4
commit 08b31e636c
1 changed files with 29 additions and 2 deletions
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31
Controllers/HyperXDRAMController/HyperXDRAMControllerDetect.cpp
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@ -1,5 +1,6 @@
#include "Detector.h"
#include "HyperXDRAMController.h"
#include "LogManager.h"
#include "RGBController.h"
#include "RGBController_HyperXDRAM.h"
#include "i2c_smbus.h"
@ -17,6 +18,7 @@ using namespace std::chrono_literals;
* Tests the given address to see if a HyperX controller exists there. *
* *
\******************************************************************************************/
#define HYPERX_CONTROLLER_NAME "HyperX DRAM"
bool TestForHyperXDRAMController(i2c_smbus_interface* bus, unsigned char address)
{
@ -24,6 +26,8 @@ bool TestForHyperXDRAMController(i2c_smbus_interface* bus, unsigned char address
int res = bus->i2c_smbus_write_quick(address, I2C_SMBUS_WRITE);
LOG_DEBUG("[%s] Writing at address %02X, res=%02X", HYPERX_CONTROLLER_NAME, address, res);
if (res >= 0)
{
pass = true;
@ -66,9 +70,12 @@ void DetectHyperXDRAMControllers(std::vector<i2c_smbus_interface*> &busses)
bool fury_detected = false;
bool pred_detected = false;
LOG_DEBUG("[%s] Checking VID/PID on bus %d...", HYPERX_CONTROLLER_NAME, bus);
IF_DRAM_SMBUS(busses[bus]->pci_vendor, busses[bus]->pci_device)
{
// Check for HyperX controller at 0x27
LOG_DEBUG("[%s] Testing bus %d at address 0x27", HYPERX_CONTROLLER_NAME, bus);
if (TestForHyperXDRAMController(busses[bus], 0x27))
{
busses[bus]->i2c_smbus_write_byte_data(0x37, 0x00, 0xFF);
@ -80,9 +87,16 @@ void DetectHyperXDRAMControllers(std::vector<i2c_smbus_interface*> &busses)
// Test for HyperX SPD at slot_addr
// This test was copied from NGENUITY software
// Tests SPD addresses in order: 0x40, 0x41
if((busses[bus]->i2c_smbus_read_byte_data(slot_addr, 0x40) == 0x01)
&&(busses[bus]->i2c_smbus_read_byte_data(slot_addr, 0x41) == 0x98))
int read_0x40 = busses[bus]->i2c_smbus_read_byte_data(slot_addr, 0x40);
int read_0x41 = busses[bus]->i2c_smbus_read_byte_data(slot_addr, 0x41);
LOG_DEBUG("[%s] SPD check: 0x40 => %02X, 0x41 => %02X, ",
HYPERX_CONTROLLER_NAME, read_0x40, read_0x41);
if((read_0x40 == 0x01) && (read_0x41 == 0x98))
{
LOG_DEBUG("[%s] SPD check success", HYPERX_CONTROLLER_NAME);
slots_valid |= (1 << (slot_addr - 0x50));
if(busses[bus]->i2c_smbus_read_byte_data(slot_addr, 0x67) == 0x01)
@ -94,10 +108,19 @@ void DetectHyperXDRAMControllers(std::vector<i2c_smbus_interface*> &busses)
pred_detected = true;
}
}
else
{
LOG_DEBUG("[%s] SPD check failed", HYPERX_CONTROLLER_NAME);
}
std::this_thread::sleep_for(1ms);
}
LOG_DEBUG("[%s] slots_valid=%d fury_detected=%d pred_detected=%d",
HYPERX_CONTROLLER_NAME, slots_valid, fury_detected, pred_detected);
if(slots_valid != 0)
{
new_hyperx = new HyperXDRAMController(busses[bus], 0x27, slots_valid);
@ -116,6 +139,10 @@ void DetectHyperXDRAMControllers(std::vector<i2c_smbus_interface*> &busses)
}
}
}
else
{
LOG_DEBUG("[%s] IF_DRAM_SMBUS was false for %04X %04X", HYPERX_CONTROLLER_NAME, busses[bus]->pci_vendor, busses[bus]->pci_device);
}
}
} /* DetectHyperXDRAMControllers() */